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| ? 2012 microchip technology inc. ds30684a-page 1 pic18(l)f2x/45k50 universal serial bus features: ? usb v2.0 compliant ? crystal-less full speed (12 mb/s) and low-speed operation (1.5 mb/s) ? supports control, interrupt, isochronous and bulk transfers ? supports up to 32 endpoints (16 bidirectional) ? 1 kbyte dual access ram for usb ? on-chip usb transceiver flexible oscillator structure: ? 3x and 4xpll clock multipliers ? two external clock modes, up to 48 mhz (12 mips) ? internal 31 khz oscillator ? internal oscillator, 31 khz to 16 mhz - factory calibrated to 1% - self-tune to 0.20% max. from usb or secondary oscillator ? secondary oscillator using timer1 @ 32 khz ? fail-safe clock monitor: - allows for safe shutdown if any clock stops peripheral highlights: ? up to 33 i/o pins plus 3 input-only pins: - high-current sink/source 25 ma/25 ma - three programmable external interrupts - 11 programmable interrupts-on-change - 9 programmable weak pull-ups - programmable slew rate ?sr latch ? enhanced capture/compare/pwm (eccp) module: - one, two or four pwm outputs - selectable polarity - programmable dead time - auto-shutdown and auto-restart - pulse steering control ? capture/compare/pwm (ccp) module ? master synchronous serial port (mssp) module supporting 3-wire spi (all 4 modes) and i 2 c? master and slave modes ? two analog comparators with input multiplexing ? 10-bit analog-to-digital (a/d) converter module: - up to 25 input channels - auto-acquisition capability - conversion available during sleep ? digital-to-analog converter (dac) module: - fixed voltage reference (fvr) with 1.024v, 2.048v and 4.096v output levels - 5-bit rail-to-rail resistive dac with positive and negative reference selection ? high/low-voltage detect module ? charge time measurement unit (ctmu): - supports capacitive touch sensing for touch screens and capacitive switches ? enhanced usart module: - supports rs-485, rs-232 and lin/j2602 - auto-wake-up on start bit - auto-baud detect extreme low-power management with xlp: ? sleep mode: 20 na, typical ? watchdog timer: 300 na, typical ? timer1 oscillator: 800 na @ 32 khz ? peripheral module disable special microcontroller features: ? low-power, high-speed cmos flash technology ? c compiler optimized architecture for re-entrant code ? power management features: - run: cpu on, peripherals on, sram on - idle: cpu off, peripherals on, sram on - sleep: cpu off, peripherals off, sram on ? priority levels for interrupts ? self-programmable under software control ? 8 x 8 single-cycle hardware multiplier ? extended watchdog timer (wdt): - programmable period from 4 ms to 131s ? single-supply in-circuit serial programming? (icsp?) via two pins ? in-circuit debug (icd) with three breakpoints via two pins ? optional dedicated icd/icsp port (44-pin tqfp package only) ? wide operating voltage range: - f devices: 2.3v to 5.5v - lf devices: 1.8v to 3.6v ? flash program memory of 10,000 erase/write cycles minimum and 20-year data retention 28/40/44-pin, low-power, high-performance microcontrollers with xlp technology www.datasheet.net/ datasheet pdf - http://www..co.kr/
pic18(l)f2x/45k50 ds30684a-page 2 ? 2012 microchip technology inc. pin diagram pin diagram device program memory data memory pins i/o 10-bit a/d channels comparators ccp/ eccp bor/lvd ctmu mssp eusart timers 8-bit/16-bit usb 2.0 flash (bytes) single-word instructions sram (bytes) data eeprom (bytes) pic18(l)f45k50 32k 16384 2048 256 40/44 36 25-ch 2 1/1 yes yes 1 1 2/2 yes pic18(l)f25k50 32k 16384 2048 256 28 25 14-ch 2 1/1 yes yes 1 1 2/2 yes pic18(l)f24k50 16k 8192 2048 256 28 25 14-ch 2 1/1 yes yes 1 1 2/2 yes 10 11 2 3 4 5 6 1 8 7 9 12 13 14 15 16 17 18 19 20 23 24 25 26 27 28 22 21 mclr /v pp /re3 ra0 ra1 ra2 ra3 ra4 ra5 v ss ra7 ra6 rc0 rc1 rc2 v usb 3 v 3 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 v dd v ss rc7 rc6 d+ d- 28-pin pdip (300 mil), soic, ssop pic18(l)f2xk50 10 11 2 3 6 1 18 19 20 21 27 12 13 14 15 8 7 16 17 26 25 24 23 22 28 9 rc0 5 4 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 v dd v ss rc7 rc6 d+ d- mclr /v pp /re3 ra0 ra1 ra2 ra3 ra4 ra5 v ss ra7 ra6 rc1 rc2 v usb 3 v 3 pic18(l)f2xk50 28-pin qfn www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 3 pic18(l)f2x/45k50 pin diagram pin diagram rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 v dd v ss rd7 rd6 rd5 rd4 rc7 rc6 d+ d- rd3 rd2 mclr /v pp /re3 ra0 ra1 ra2 ra3 ra4 ra5 re0 re1 re2 v dd v ss ra7 ra6 rc0 rc1 rc2 v usb 3 v 3 rd0 rd1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 40-pin pdip (600 mil) pic18(l)f45k50 10 2 3 4 5 6 1 17 18 19 20 11 12 13 14 34 8 7 40 39 38 37 36 35 15 16 27 28 29 30 21 22 23 24 25 26 32 31 9 33 ra3 ra2 ra1 ra0 mclr /v pp /re3 rb3 rb7 rb6 rb5 rb4 rc6 d+ d- rd3 rd2 rd1 rd0 v usb 3 v 3 rc2 rc1 ra6 ra7 v ss v dd re2 re1 re0 ra5 ra4 rc7 rd4 rd5 rd6 rd7 v ss v dd rb0 rb1 rb2 40-pin uqfn pic18(l)f45k50 rc0 www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 4 ? 2012 microchip technology inc. pin diagram 10 11 2 3 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 37 ra3 ra2 ra1 ra0 mclr /v pp /re3 nc/icck (1) /icpgc (1) rb7 rb6 rb5 rb4 nc/icdt (1) /icpgd (1) rc6 d+ d- rd3 rd2 rd1 rd0 v usb 3 v 3 rc2 nc nc/icrst (1) /icv pp (1) rc0 ra6 ra7 v ss v dd re2 re1 re0 ra5 ra4 rc7 rd4 rd5 rd6 v ss v dd rb0 rb1 rb2 rb3 44-pin tqfp rd7 5 4 rc1 pic18(l)f45k50 note 1: special icport programming/debug port features available when icprt = 1 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 5 pic18(l)f2x/45k50 table 1: pic18(l)f2x/45k50 pin summary i/o 28-pin pdip/soic/ssop 28-pin qfn 40-pin pdip 40-pin uqfn 44-pin tqfp analog comparator ctmu sr latch reference usb (e)ccp eusart mssp timers interrupts pull-up basic icd ra0 2 27 2 17 19 an0 c12in0- ra1 3 28 3 18 20 an1 c12in1- ctcmp ra2 4 1 4 19 21 an2 c2in+ v ref - dacout ra3 5 2 5 20 22 an3 c1in+ v ref + ra4 6 3 6 21 23 c1out srq t0cki ra5 7 4 7 22 24 an4 c2out srnq hlvdin ss ra6 10 7 14 29 31 osc2 clko ra7 9 6 13 28 30 osc1 clki rb0 21 18 33 8 8 an12 sri flt0 sdi sda int0 y rb1 22 19 34 9 9 an10 c12in3- p1c (5) sck scl int1 y rb2 23 20 35 10 10 an8 cted1 p1b (5) int2 y rb3 24 21 36 11 11 an9 c12in2- cted2 ccp2 (1) sdo y rb4 25 22 37 12 14 an11 p1d (5) iocb4 y rb5 26 23 38 13 15 an13 t1g t3cki (2) iocb5 y rb6 27 24 39 14 16 iocb6 y pgc rb7 28 25 40 15 17 iocb7 y pgd note 1: alternate ccp2 pin location based on configuration bit. 2: alternate t3cki pin location based on configuration bits. 3: pins are enabled when icprt = 1 , otherwise, they are disabled. 4: location on 40/44-pin parts (pic18(l)f45k50). functi on not on this pin on 28-pin parts (pic18(l)f2xk50). 5: location on 28-pin parts (pic18(l)f2xk50). function not on this pin on 40/44-pin parts (pic18(l)f45k50). 6: alternate sdo pin location based on configuration bits. 7: re3 can be used for digital input only (no output functionality). www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 6 ? 2012 microchip technology inc. rc0 11 8 15 30 32 sosco t1cki t3cki t3g iocc0 rc1 12 9 16 31 35 ccp2 sosci iocc1 rc2 13 10 17 32 36 an14 ctpls ccp1 p1a iocc2 ? 14 11 18 33 37 ? v usb 3 v 3 v ddcore ? 15 12 23 38 42 ? d- iocc4 ? 16 13 24 39 43 ? d+ iocc5 rc6 17 14 25 40 44 an18 tx ck iocc6 rc7 18 15 26 1 1 an19 rx dt sdo (6) iocc7 rd0 ? ? 19 34 38 an20 rd1 ? ? 20 35 39 an21 rd2 ? ? 21 36 40 an22 rd3 ? ? 22 37 41 an23 rd4 ? ? 27 2 2 an24 rd5 ? ? 28 3 3 an25 p1b (4) rd6 ? ? 29 4 4 an26 p1c (4) rd7 ? ? 30 5 5 an27 p1d (4) re0 ?? 823 25 an5 table 1: pic18(l)f2x/45k50 pin summary i/o 28-pin pdip/soic/ssop 28-pin qfn 40-pin pdip 40-pin uqfn 44-pin tqfp analog comparator ctmu sr latch reference usb (e)ccp eusart mssp timers interrupts pull-up basic icd note 1: alternate ccp2 pin location based on configuration bit. 2: alternate t3cki pin location based on configuration bits. 3: pins are enabled when icprt = 1 , otherwise, they are disabled. 4: location on 40/44-pin parts (pic18(l)f45k50). functi on not on this pin on 28-pin parts (pic18(l)f2xk50). 5: location on 28-pin parts (pic18(l)f2xk50). function not on this pin on 40/44-pin parts (pic18(l)f45k50). 6: alternate sdo pin location based on configuration bits. 7: re3 can be used for digital input only (no output functionality). www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 7 pic18(l)f2x/45k50 re1 ? ? 9 24 26 an6 re2 ?? 10 25 27 an7 re3 (7) 1 26 1 16 18 ? y mclr v pp 20 17 11, 32 7, 26 7, 28 v dd 8, 19 5, 16 12, 31 6, 27 6, 29 v ss ??-12 (3) icpgc (3) icck (3) ? ?- 13 (3) icpgd (3) icdt (3) ?- ?- 33 (3) icv pp (3) icrst (3) table 1: pic18(l)f2x/45k50 pin summary i/o 28-pin pdip/soic/ssop 28-pin qfn 40-pin pdip 40-pin uqfn 44-pin tqfp analog comparator ctmu sr latch reference usb (e)ccp eusart mssp timers interrupts pull-up basic icd note 1: alternate ccp2 pin location based on configuration bit. 2: alternate t3cki pin location based on configuration bits. 3: pins are enabled when icprt = 1 , otherwise, they are disabled. 4: location on 40/44-pin parts (pic18(l)f45k50). functi on not on this pin on 28-pin parts (pic18(l)f2xk50). 5: location on 28-pin parts (pic18(l)f2xk50). function not on this pin on 40/44-pin parts (pic18(l)f45k50). 6: alternate sdo pin location based on configuration bits. 7: re3 can be used for digital input only (no output functionality). www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 8 ? 2012 microchip technology inc. table of contents 1.0 device overview ............................................................................................................. .......................................................... 13 2.0 guidelines for getting started with pic18(l)f2x/45k50 microcontrollers ...................................................... .......................... 27 3.0 oscillator module (with fail-safe clock monitor)............................................................................ .......................................... 33 4.0 power-managed modes ......................................................................................................... ................................................... 57 5.0 reset ....................................................................................................................... .................................................................. 69 6.0 memory organization ......................................................................................................... ....................................................... 79 7.0 flash program memory........................................................................................................ ................................................... 101 8.0 data eeprom memory .......................................................................................................... ................................................. 111 9.0 8 x 8 hardware multiplier................................................................................................... ....................................................... 117 10.0 interrupts ................................................................................................................. ................................................................. 119 11.0 i/o ports .................................................................................................................. ................................................................ 137 12.0 timer0 module.............................................................................................................. ........................................................... 163 13.0 timer1/3 module with gate control.......................................................................................... ............................................... 167 14.0 timer2 module.............................................................................................................. ........................................................... 179 15.0 capture/compare/pwm modules................................................................................................ ............................................ 183 16.0 master synchronous serial port (mssp) module ............................................................................... .................................... 215 17.0 enhanced universal synchronous asynchronous receiver transmitter (eusart) .................................................. ............ 271 18.0 analog-to-digital converter (adc) module ................................................................................... .......................................... 301 19.0 comparator module.......................................................................................................... ....................................................... 315 20.0 charge time measurement unit (ctmu)........................................................................................ ........................................ 325 21.0 sr l atch ............................................................................................................................... .................................................. 341 22.0 fixed voltage reference (fvr).............................................................................................. ................................................. 347 23.0 digital-to-analog converter (dac) module ................................................................................... .......................................... 349 24.0 universal serial bus (usb) ................................................................................................. .................................................... 353 25.0 high/low-voltage detect (hlvd) ............................................................................................. ............................................... 381 26.0 special features of the cpu ................................................................................................ ................................................... 387 27.0 instruction set summary .................................................................................................... ..................................................... 407 28.0 development support........................................................................................................ ...................................................... 457 29.0 electrical characteristics ................................................................................................. ........................................................ 461 30.0 dc and ac characteristics graphs and charts ................................................................................ ...................................... 501 31.0 packaging information...................................................................................................... ....................................................... 503 appendix a: revision history................................................................................................... ......................................................... 521 appendix b: device differences................................................................................................. ....................................................... 522 index .......................................................................................................................... ....................................................................... 523 the microchip web site ......................................................................................................... ........................................................... 533 customer change notification service ........................................................................................... .................................................. 533 customer support ............................................................................................................... .............................................................. 533 reader response ................................................................................................................ ............................................................. 534 product identification system.................................................................................................. .......................................................... 535 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 9 pic18(l)f2x/45k50 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please specify which device, re vision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 10 ? 2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 11 pic18(l)f2x/45k50 1.0 device overview this document contains device-specific information for the following devices: this family offers the advantages of all pic18 microcontrollers ? namely, high computational performance at an economical price ? with the addition of high-endurance, flash program memory. on top of these features, the pic18(l)f2x/45k50 family introduces design enhancements that make these microcontrollers a logical choice for many high- performance, power sensitive applications. 1.1 new core features 1.1.1 xlp technology all of the devices in the pic18(l)f2x/45k50 family incorporate a range of features that can significantly reduce power consumption during operation. key items include: ? alternate run modes: by clocking the controller from the timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%. ? multiple idle modes: the controller can also run with its cpu core disabled but the peripherals still active. in these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements. ? peripheral module disable bits: user code can power down individual peripheral modules during run and idle modes for further lowering dynamic power reduction. ? on-the-fly mode switching: the power- managed modes are invoked by user code during operation, allowing the user to incorporate power- saving ideas into their application?s software design. ? low consumption in key modules: the power requirements for both timer1 and the watchdog timer are minimized. see section 29.0 ?electrical characteristics? for values. 1.1.2 universal serial bus (usb) devices in the pic18(l)f2x/45k50 family incorporate a fully-featured usb communications module with a built-in transceiver that is compliant with the usb specification revision 2.0. the module supports both low-speed and full-speed communication for all supported data transfer types. the device incorporates its own on-chip transceiver and 3.3v regulator for usb. 1.1.3 multiple oscillator options and features all of the devices in the pic18(l)f2x/45k50 family offer ten different oscillator options, allowing users a wide range of choices in developing application hardware. these include: ? four crystal modes, using crystals or ceramic resonators ? six external clock modes, offering the option of using two pins (oscillator input and a divide-by-4 clock output) or one pin (oscillator input, with the second pin reassigned as general i/o) ? two external rc oscillator modes with the same pin options as the external clock modes ? an internal oscillator block which contains a 16 mhz hfintosc oscillator and a 31 khz intrc oscillator, which together provide eight user selectable clock frequencies, from 31 khz to 16 mhz. this option frees the two oscillator pins for use as additional general purpose i/o. ? 3x and 4x phase lock loop (pll) frequency multipliers, available to both external and internal oscillator modes, which allows clock speeds of up to 48 mhz. used with the internal oscillator, the pll gives users a complete selection of clock speeds, from 31 khz to 48 mhz ? all without using an external crystal or clock circuit. besides its availability as a clock source, the internal oscillator block provides a stable reference source that gives the family additional features for robust operation: ? active clock tuning: this option allows the internal oscillator to automatically tune itself to match usb host or external 32.768 khz secondary oscillator clock sources. full-speed usb operation can now meet specification requirements without an external crystal, enabling lower-cost designs. ? fail-safe clock monitor: this option constantly monitors the main clock source against a reference signal provided by the intrc. if a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued operation or a safe application shutdown. ? two-speed start-up: this option allows the internal oscillator to serve as the clock source from power-on reset, or wake-up from sleep mode, until the primary clock source is available. ?pic18(l)f45k50 ?pic18(l)f25k50 ?pic18(l)f24k50 www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 12 ? 2012 microchip technology inc. 1.2 other special features ? memory endurance: the flash cells for both program memory and data eeprom are rated to last for many thousands of erase/write cycles ? up to 10k for program memory and 100k for eeprom. data retention without refresh is conservatively estimated to be greater than 40 years. ? self-programmability: these devices can write to their own program memory spaces under inter- nal software control. by using a bootloader routine located in the protected boot block at the top of program memory, it becomes possible to create an application that can update itself in the field. ? extended instruction set: the pic18(l)f2x/ 45k50 family introduces an optional extension to the pic18 instruction set, which adds eight new instructions and an indexed addressing mode. this extension, enabled as a device configuration option, has been specifically designed to optimize re-entrant application code originally developed in high-level languages, such as c. ? enhanced ccp module: in pwm mode, this module provides 1, 2 or 4 modulated outputs for controlling half-bridge and full-bridge drivers. other features include: - auto-shutdown, for disabling pwm outputs on interrupt or other select conditions - auto-restart, to reactivate outputs once the condition has cleared - output steering to selectively enable one or more of four outputs to provide the pwm signal. ? enhanced addressable eusart: this serial communication module is capable of standard rs-232 operation and provides support for the lin bus protocol. other enhancements include automatic baud rate detection and a 16-bit baud rate generator for improved resolution. when the microcontroller is using the internal oscillator block, the eusart provides stable operation for applications that talk to the outside world without using an external crystal (or its accompanying power requirement). ? 10-bit a/d converter: this module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reduce code overhead. ? dedicated icd/icsp? port: these devices introduce the use of debugger and programming pins that are not multiplexed with other microcontroller features. offered as an option in the tqfp packaged devices, this feature allows users to develop i/o intensive applications while retaining the ability to program and debug in the circuit. ? charge time measurement unit (ctmu): ? sr latch output: 1.3 details on individual family members devices in the pic18(l)f2x/45k50 family are available in 28-pin and 40/44-pin packages. the block diagram for the device family is shown in figure 1-1 . the devices have the following differences: 1. flash program memory 2. a/d channels 3. i/o ports 4. input voltage range/power consumption all other features for devices in this family are identical. these are summarized in ta b l e 1 - 1 . the pinouts for all devices are listed in the pin summary table: ta b l e 1 , and i/o description tables: tab l e 1 - 2 and table 1-3 . www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 13 pic18(l)f2x/45k50 table 1-1: device features features pic18(l)f24k50 pic18(l)f25k50 pic18(l)f45k50 program memory (bytes) 16384 32768 32768 program memory (instructions) 8192 16384 16384 data memory (bytes) 2048 2048 2048 data eeprom memory (bytes) 256 256 256 i/o ports a, b, c, e (1) a, b, c, e (1) a, b, c, d, e capture/compare/pwm modules (ccp) 11 1 enhanced ccp modules (eccp) 1 1 1 10-bit analog-to-digital module (adc) 3 internal 14 input 3 internal 14 input 3 internal 25 input packages 28-pin pdip 28-pin soic 28-pin ssop 28-pin qfn 28-pin pdip 28-pin soic 28-pin ssop 28-pin qfn 40-pin pdip 40-pin uqfn 44-pin tqfp interrupt sources 25 timers (16-bit) 2 serial communications mssp, eusart sr latch yes charge time measurement unit module (ctmu) yes programmable high/low-voltage detect (hlvd) yes programmable brown-out reset (bor) yes resets (and delays) por, bor, lpbor reset instruction, stack overflow, stack underflow (pwrt, ost), mclr , wdt instruction set 75 instructions; 83 with extended instruction set enabled operating frequency dc ? 48 mhz note 1: porte contains the single re3 read-only bit. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 14 ? 2012 microchip technology inc. figure 1-1: pic18(l)f2x/45k50 family block diagram instruction decode and control data latch data memory address latch data address<12> 12 access bsr fsr0 fsr1 fsr2 inc/dec logic address 4 12 4 pch pcl pclath 8 31-level stack program counter prodl prodh 8 x 8 multiply 8 bitop 8 8 alu<8> 20 8 8 table pointer<21> inc/dec logic 21 8 data bus<8> table latch 8 ir 12 3 rom latch pclatu pcu note 1: re3 is only available when mclr functionality is disabled. 2: osc1/clkin and osc2/clko are only available in select oscillator modes and when these pins are not being used as digital i/o. refer to section 6.0 ?memory organization? for additional information. eusart comparators mssp 10-bit adc timer2 timer1 ctmu timer0 usb hlvd eccp1 bor data eeprom w instruction bus <16> stkptr bank 8 state machine control signals decode 8 8 power-up timer oscillator start-up timer power-on reset watchdog timer osc1 (2) osc2 (2) brown-out reset internal oscillator fail-safe clock monitor precision reference band gap mclr (1) block intrc oscillator 16 mhz oscillator single-supply programming in-circuit debugger sosco sosci fvr fvr fvr dac address latch program memory (16/32 kbytes) data latch porta ra0:ra7 portb rb0:rb7 portc rc0:rc3 portd rd0:rd7 timer3 sr latch c1/c2 ccp2 porte re0:re2 re3 (1) dac rc6:rc7 dac www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 15 pic18(l)f2x/45k50 table 1-2: pic18(l)f2xk50 pinout i/o descriptions pin number pin name pin type buffer ty pe description pdip, soic, ssop qfn 227 ra0/c12in0-/an0 ra0 i/o ttl/dig digital i/o. c12in0- i analog comparators c1 and c2 inverting input. an0 i analog analog input 0. 328 ra1/c12in1-/an1 ra1 i/o ttl/dig digital i/o. c12in1- i analog comparators c1 and c2 inverting input. an1 i analog analog input 1. 41 ra2/c2in+/an2/dacout/v ref - ra2 i/o ttl/dig digital i/o. c2in+ i analog comparator c2 non-inverting input. an2 i analog analog input 2. dacout o analog dac reference output. v ref - i analog a/d reference voltage (low) input. 52 ra3/c1in+/an3/v ref + ra3 i/o ttl/dig digital i/o. c1in+ i analog comparator c1 non-inverting input. an3 i analog analog input 3. v ref + i analog a/d reference voltage (high) input. 63 ra4/c1out/srq/t0cki ra4 i/o st/dig digital i/o. c1out o dig comparator c1 output. srq o dig sr latch q output. t0cki i st timer0 external clock input. 74 ra5/c2out/srnq/s s /hlvdin/an4 ra5 i/o ttl/dig digital i/o. c2out o dig comparator c2 output. srnq o dig sr latch q output. s s i ttl spi slave select input (mssp). hlvdin i analog high/low-voltage detect input. an4 i analog analog input 4. 10 7 ra6/clko/osc2 ra6 i/o ttl/dig digital i/o. clko o dig outputs 1/4 the frequency of osc1 and denotes the instruction cycle rate. osc2 o ? oscillator crystal output. connects to crystal or resonator in crystal oscillator modes. legend: ttl = ttl compatible input; cmos = cmos compatible input or output; st = schmitt trigger input with cmos levels; i = input; o = output; p = power. note 1: default pin assignment for sdo, t3cki and ccp2 when configuration bits sdomx, t3cmx and ccp2mx are set. 2: alternate pin assignment for sdo, t3cki and ccp2 when configuration bits sdomx, t3cmx and ccp2mx are clear. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 16 ? 2012 microchip technology inc. 9 6 ra7/clki/osc1 ra7 i/o ttl/dig digital i/o. clki i cmos external clock source input. always associated with pin function osc1. osc1 i st oscillator crystal input or external clock source input st buffer when configured in rc mode; cmos otherwise. 21 18 rb0/int0/f lt0 /sri/sdi/sda/an12 rb0 i/o ttl/dig digital output or input with internal pull-up option. int0 i st external interrupt 0. flt0 i st pwm fault input for eccp auto-shutdown. sri i st sr latch input. sdi i st spi data in (mssp). sda i/o i 2 c? i 2 c? data i/o (mssp). an12 i analog analog input 12. 22 19 rb1/int1/p1c/sck/scl/c12in3-/an10 rb1 i/o ttl/dig digital output or input with internal pull-up option. int1 i st external interrupt 1. p1c o dig enhanced ccp1 pwm output. sck i/o st/dig synchronous serial clock input/output for spi mode (mssp). scl i/o i 2 c? synchronous serial clock input/output for i 2 c? mode (mssp). c12in3- i analog comparators c1 and c2 inverting input. an10 i analog analog input 10. 23 20 rb2/int2/cted1/p1b/an8 rb2 i/o ttl/dig digital output or input with internal pull-up option. int2 i st external interrupt 2. cted1 i st ctmu edge 1 input. p1b o dig enhanced ccp1 pwm output. an8 i analog analog input 8. 24 21 rb3/cted2/ccp2/sdo/c12in2-/an9 rb3 i/o ttl/dig digital output or input with internal pull-up option. cted2 i st ctmu edge 2 input. ccp2 (2) i/o st/dig alternate capture 2 input/compare 2 output/pwm 2 output. sdo (1) o dig spi data out (mssp). c12in2- i analog comparators c1 and c2 inverting input. an9 i analog analog input 9. table 1-2: pic18(l)f2 xk50 pinout i/o descriptions (continued) pin number pin name pin type buffer ty pe description pdip, soic, ssop qfn legend: ttl = ttl compatible input; cmos = cmos compatible input or output; st = schmitt trigger input with cmos levels; i = input; o = output; p = power. note 1: default pin assignment for sdo, t3cki and ccp2 when configuration bits sdomx, t3cmx and ccp2mx are set. 2: alternate pin assignment for sdo, t3cki and ccp2 when configuration bits sdomx, t3cmx and ccp2mx are clear. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 17 pic18(l)f2x/45k50 25 22 rb4/iocb4/p1d/an11 rb4 i/o ttl/dig digital output or input with internal pull-up option. iocb4 i ttl interrupt-on-change pin. p1d o dig enhanced ccp1 pwm output. an11 i analog analog input 11. 26 23 rb5/iocb5/t3cki/t1g/an13 rb5 i/o ttl/dig digital output or input with internal pull-up option. iocb5 i ttl interrupt-on-change pin. t3cki (2) i st alternate timer3 clock input. t1g i st timer1 external clock gate input. an13 i analog analog input 13. 27 24 rb6/iocb6/pgc rb6 i/o ttl/dig digital output or input with internal pull-up option. iocb6 i ttl interrupt-on-change pin. pgc i/o st in-circuit debugger and icsp? programming clock pin. 28 25 rb7/iocb7/pgd rb7 i/o ttl/dig digital output or input with internal pull-up option. iocb7 i ttl interrupt-on-change pin. pgd i/o st/dig in-circuit debugger and icsp? programming data pin. 11 8 rc0/iocc0/t3cki/t3g/t1cki/sosco rc0 i/o st/dig digital i/o. iocc0 i ttl interrupt-on-change pin. t3cki (1) i st timer3 clock input. t3g i st timer3 external clock gate input. t1cki i st timer1 clock input. sosco o ? secondary oscillator output. 12 9 rc1/iocc1/ccp2/sosci rc1 i/o st/dig digital i/o. iocc1 i ttl interrupt-on-change pin. ccp2 (1) i/o st/dig capture 2 input/compare 2 output/pwm 2 output. sosci i analog secondary oscillator input. table 1-2: pic18(l)f2xk50 pinout i/o descriptions (continued) pin number pin name pin type buffer ty pe description pdip, soic, ssop qfn legend: ttl = ttl compatible input; cmos = cmos compatible input or output; st = schmitt trigger input with cmos levels; i = input; o = output; p = power. note 1: default pin assignment for sdo, t3cki and ccp2 when configuration bits sdomx, t3cmx and ccp2mx are set. 2: alternate pin assignment for sdo, t3cki and ccp2 when configuration bits sdomx, t3cmx and ccp2mx are clear. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 18 ? 2012 microchip technology inc. 13 10 rc2/ctpls/p1a/ccp1/iocc2/an14 rc2 i/o st/dig digital i/o. ctpls o dig ctmu pulse generator output. p1a o dig enhanced ccp1 pwm output. ccp1 i/o st/dig capture 1 input/compare 1 output/pwm 1 output. iocc2 i ttl interrupt-on-change pin. an14 i analog analog input 14. 14 11 v usb 3 v 3 v usb 3 v 3 p ? internal 3.3v voltage regulator output, positive supply for usb transceiver. 15 12 d-/iocc4 d- i/o ? usb differential minus line input/output. iocc4 i st interrupt-on-change pin. 16 13 d+/iocc5 d+ i/o ? usb differential plus line input/output. iocc5 i st interrupt-on-change pin. 17 14 rc6/iocc6/tx/ck/an18 rc6 i/o st/dig digital i/o. iocc6 i ttl interrupt-on-change pin. tx o dig eusart asynchronous transmit. ck i/o st eusart synchronous clock (see related rx/dt). an18 i analog analog input 18. 18 15 rc7/sdo/iocc7/rx/dt/an19 rc7 i/o st/dig digital i/o. sdo (2) o dig alternate spi data out pin assignment (mssp). iocc7 i ttl interrupt-on-change pin. rx i st eusart asynchronous receive. dt i/o st/dig eusart synchronous data (see related tx/ck). an19 i analog analog input 19. 1 26 re3/v pp /mclr re3 i st digital input. v pp p programming voltage input. mclr i st active-low master clear (device reset) input. 20 17 v dd p ? positive supply for logic and i/o pins. 8, 19 5, 16 v ss p ? ground reference for logic and i/o pins. table 1-2: pic18(l)f2 xk50 pinout i/o descriptions (continued) pin number pin name pin type buffer ty pe description pdip, soic, ssop qfn legend: ttl = ttl compatible input; cmos = cmos compatible input or output; st = schmitt trigger input with cmos levels; i = input; o = output; p = power. note 1: default pin assignment for sdo, t3cki and ccp2 when configuration bits sdomx, t3cmx and ccp2mx are set. 2: alternate pin assignment for sdo, t3cki and ccp2 when configuration bits sdomx, t3cmx and ccp2mx are clear. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 19 pic18(l)f2x/45k50 table 1-3: pic18(l)f45k50 pinout i/o descriptions pin number pin name pin type buffer type description pdip tqfp uqfn 21917 ra0/c12in0-/an0 ra0 i/o ttl/dig digital i/o. c12in0- i analog comparators c1 and c2 inverting input. an0 i analog analog input 0. 32018 ra1/c12in1-/an1 ra1 i/o ttl/dig digital i/o. c12in1- i analog comparators c1 and c2 inverting input. an1 i analog analog input 1. 42119 ra2/c2in+/an2/dacout/v ref - ra2 i/o ttl/dig digital i/o. c2in+ i analog comparator c2 non-inverting input. an2 i analog analog input 2. dacout o analog dac reference output. v ref - i analog a/d reference voltage (low) input. 52220 ra3/c1in+/an3/v ref + ra3 i/o ttl/dig digital i/o. c1in+ i analog comparator c1 non-inverting input. an3 i analog analog input 3. v ref + i analog a/d reference voltage (high) input. 62321 ra4/c1out/srq/t0cki ra4 i/o st/dig digital i/o. c1out o dig comparator c1 output. srq o ttl sr latch q output. t0cki i st timer0 external clock input. 72422 ra5/c2out/srnq/s s /hlvdin/an4 ra5 i/o ttl/dig digital i/o. c2out o dig comparator c2 output. srnq o dig sr latch q output. s s i ttl spi slave select input (mssp). hlvdin i analog high/low-voltage detect input. an4 i analog analog input 4. 14 31 29 ra6/clko/osc2 ra6 i/o ttl/dig digital i/o. clko o dig outputs 1/4 the frequency of osc1 and denotes the instruction cycle rate. osc2 o ? oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. 13 30 28 ra7/clki/osc1 ra7 i/o ttl/dig digital i/o. clki i cmos external clock source input. always associated with pin function osc1. osc1 i st oscillator crystal input or exte rnal clock source input st buffer when configured in rc mode; cmos otherwise. legend: ttl = ttl compatible input; cmos = cmos compatible input or output; st = schmitt trigger input with cmos levels; i = input; o = output; p = power. note 1: default pin assignment for sdo, t3cki and ccp2 when configuration bits sdomx, t3cmx and ccp2mx are set. 2: alternate pin assignment for sdo, t3cki and ccp2 when configuration bits sdomx, t3cmx and ccp2mx are clear. 3: pin is ?no connect?, except on pic18(l)f45k50 tqfp devices with icprt configuration bit set. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 20 ? 2012 microchip technology inc. 33 8 8 rb0/int0/flt0 /sdi/sda/sri/an12 rb0 i/o ttl/dig digital output or input with internal pull-up option. int0 i st external interrupt 0. flt0 i st pwm fault input for eccp auto-shutdown. sdi i st spi data in (mssp). sda i/o i 2 c? i 2 c? data i/o (mssp). sri i st sr latch input. an12 i analog analog input 12. 34 9 9 rb1/int1/p1c/sck/scl/c12in3-/an10 rb1 i/o ttl/dig digital output or input with internal pull-up option. int1 i st external interrupt 1. p1c o dig enhanced ccp1 pwm output. sck i/o st/dig synchronous serial clock input/output for spi mode (mssp). scl i/o i 2 c? synchronous serial clock input/output for i 2 c? mode (mssp). c12in3- i analog comparators c1 and c2 inverting input. an10 i analog analog input 10. 35 10 10 rb2/p1b/int2/cted1/an8 rb2 i/o ttl/dig digital output or input with internal pull-up option. p1b o dig enhanced ccp1 pwm output. int2 i st external interrupt 2. cted1 i st ctmu edge 1 input. an8 i analog analog input 8. 36 11 11 rb3/cted2/sdo/ccp2/c12in2-/an9 rb3 i/o ttl/dig digital output or input with internal pull-up option. cted2 i st ctmu edge 2 input. sdo (1) o dig spi data out (mssp). ccp2 (2) i/o st alternate capture 2 input/compare 2 output/pwm 2 output. c12in2- i analog comparators c1 and c2 inverting input. an9 i analog analog input 9. 37 14 12 rb4/iocb4/p1d/an11 rb4 i/o ttl/dig digital output or input with internal pull-up option. iocb4 i ttl interrupt-on-change pin. p1d o dig enhanced ccp1 pwm output. an11 i analog analog input 11. 38 15 13 rb5/iocb5/t3cki/t1g/an13 rb5 i/o ttl/dig digital output or input with internal pull-up option. iocb5 i ttl interrupt-on-change pin. t3cki (2) i st alternate timer3 clock input. t1g i st timer1 external clock gate input. an13 i analog analog input 13. table 1-3: pic18(l)f45k 50 pinout i/o descriptions (continued) pin number pin name pin type buffer type description pdip tqfp uqfn legend: ttl = ttl compatible input; cmos = cmos compatible input or output; st = schmitt trigger input with cmos levels; i = input; o = output; p = power. note 1: default pin assignment for sdo, t3cki and ccp2 when configuration bits sdomx, t3cmx and ccp2mx are set. 2: alternate pin assignment for sdo, t3cki and ccp2 when configuration bits sdomx, t3cmx and ccp2mx are clear. 3: pin is ?no connect?, except on pic18(l)f45k50 tqfp devices with icprt configuration bit set. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 21 pic18(l)f2x/45k50 39 16 14 rb6/iocb6/pgc rb6 i/o ttl/dig digital output or input with internal pull-up option. iocb6 i ttl interrupt-on-change pin. pgc i/o st in-circuit debugger and icsp? programming clock pin. 40 17 15 rb7/iocb7/pgd rb7 i/o ttl/dig digital output or input with internal pull-up option. iocb7 i ttl interrupt-on-change pin. pgd i/o st in-circuit debugger and icsp? programming data pin. 15 32 30 rc0/iocc0/t3cki/t3g/t1cki/sosco rc0 i/o st/dig digital i/o. iocc0 i ttl interrupt-on-change pin. t3cki (1) i st timer3 clock input. t3g i st timer3 external clock gate input. t1cki i st timer1 clock input. sosco o ? secondary oscillator output. 16 35 31 rc1/iocc1/ccp2/sosci rc1 i/o st/dig digital i/o. iocc1 i ttl interrupt-on-change pin. ccp2 (1) i/o st/dig capture 2 input/compare 2 output/pwm 2 output. sosci i analog secondary oscillator input. 17 36 32 rc2/ctpls/p1a/ccp1/iocc2/an14 rc2 i/o st/dig digital i/o. ctpls o dig ctmu pulse generator output. p1a o dig enhanced ccp1 pwm output. ccp1 i/o st/dig capture 1 input/compare 1 output/pwm 1 output. iocc2 i ttl interrupt-on-change pin. an14 i analog analog input 14. 18 37 33 v usb 3 v 3 v usb 3 v 3 p ? internal 3.3v voltage regulator output, positive supply for usb transceiver. 23 42 38 d-/iocc4 d- i/o ? usb differential minus line input/output. iocc4 i st interrupt-on-change pin. 24 43 39 d+/iocc5 d+ i/o ? usb differential plus line input/output. iocc5 i st interrupt-on-change pin. table 1-3: pic18(l)f45k 50 pinout i/o descriptions (continued) pin number pin name pin type buffer type description pdip tqfp uqfn legend: ttl = ttl compatible input; cmos = cmos compatible input or output; st = schmitt trigger input with cmos levels; i = input; o = output; p = power. note 1: default pin assignment for sdo, t3cki and ccp2 when configuration bits sdomx, t3cmx and ccp2mx are set. 2: alternate pin assignment for sdo, t3cki and ccp2 when configuration bits sdomx, t3cmx and ccp2mx are clear. 3: pin is ?no connect?, except on pic18(l)f45k50 tqfp devices with icprt configuration bit set. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 22 ? 2012 microchip technology inc. 25 44 40 rc6/iocc6/tx/ck/an18 rc6 i/o st/dig digital i/o. iocc6 i ttl interrupt-on-change pin. tx o ? eusart asynchronous transmit. ck i/o st eusart synchronous clock (see related rx/dt). an18 i analog analog input 18. 26 1 1 rc7/rx/dt/sdo/iocc7/an19 rc7 i/o st/dig digital i/o. rx i st eusart asynchronous receive. dt i/o st eusart synchronous data (see related tx/ck). sdo (2) o dig alternate spi data out (mssp). iocc7 i ttl interrupt-on-change pin. an19 i analog analog input 19. 19 38 34 rd0/an20 rd0 i/o st/dig digital i/o. an20 i analog analog input 20. 20 39 35 rd1/an21 rd1 i/o st/dig digital i/o. an21 i analog analog input 21. 21 40 36 rd2/an22 rd2 i/o st/dig digital i/o an22 i analog analog input 22. 22 41 37 rd3/an23 rd3 i/o st/dig digital i/o. an23 i analog analog input 23. 27 2 2 rd4/an24 rd4 i/o st/dig digital i/o. an24 i analog analog input 24. 28 3 3 rd5/p1b/an25 rd5 i/o st/dig digital i/o. p1b o dig enhanced ccp1 pwm output. an25 i analog analog input 25. 29 4 4 rd6/p1c/an26 rd6 i/o st/dig digital i/o. p1c o dig enhanced ccp1 pwm output. an26 i analog analog input 26. 30 5 5 rd7/p1d/an27 rd7 i/o st/dig digital i/o. p1d o dig enhanced ccp1 pwm output. an27 i analog analog input 27. table 1-3: pic18(l)f45k 50 pinout i/o descriptions (continued) pin number pin name pin type buffer type description pdip tqfp uqfn legend: ttl = ttl compatible input; cmos = cmos compatible input or output; st = schmitt trigger input with cmos levels; i = input; o = output; p = power. note 1: default pin assignment for sdo, t3cki and ccp2 when configuration bits sdomx, t3cmx and ccp2mx are set. 2: alternate pin assignment for sdo, t3cki and ccp2 when configuration bits sdomx, t3cmx and ccp2mx are clear. 3: pin is ?no connect?, except on pic18(l)f45k50 tqfp devices with icprt configuration bit set. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 23 pic18(l)f2x/45k50 82523 re0/an5 re0 i/o st/dig digital i/o. an5 i analog analog input 5. 92624 re1/an6 re1 i/o st/dig digital i/o. an6 i analog analog input 6. 10 27 25 re2/an7 re2 i/o st digital i/o. an7 i analog analog input 7. 11816 re3/v pp /mclr re3 i st digital input. v pp p programming voltage input. mclr i st active-low master clear (device reset) input. ? 12 ? icck/icpgc icck i/o st dedicated in-circuit debugger clock. icpgc (3) i/o st dedicated icsp? programming clock. ? 13 ? icdt/icpgd icdt i/o st dedicated in-circuit debugger data. icpgd (3) i/o st dedicated icsp? programming data. ? 33 ? icrst /icv pp icrst i st dedicated master clear reset input. icv pp (3) i p dedicated programming voltage input. 11,32 7, 28 7, 26 v dd p ? positive supply for logic and i/o pins. 12,31 6, 29 6, 27 v ss p ? ground reference for logic and i/o pins. 34 nc table 1-3: pic18(l)f45k 50 pinout i/o descriptions (continued) pin number pin name pin type buffer type description pdip tqfp uqfn legend: ttl = ttl compatible input; cmos = cmos compatible input or output; st = schmitt trigger input with cmos levels; i = input; o = output; p = power. note 1: default pin assignment for sdo, t3cki and ccp2 when configuration bits sdomx, t3cmx and ccp2mx are set. 2: alternate pin assignment for sdo, t3cki and ccp2 when configuration bits sdomx, t3cmx and ccp2mx are clear. 3: pin is ?no connect?, except on pic18(l)f45k50 tqfp devices with icprt configuration bit set. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 24 ? 2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 25 pic18(l)f2x/45k50 2.0 guidelines for getting started with pic18(l)f2x/45k50 microcontrollers 2.1 basic connection requirements getting started with the pic18(l)f2x/45k50 family of 8-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. the following pins must always be connected: ?all v dd and v ss pins (see section 2.2 ?power supply pins? ) ?mclr pin (see section 2.3 ?master clear (mclr) pin? ) ?v usb 3 v 3 pins (see section 2.4 ?voltage regulator pins (v usb 3 v 3)? ) these pins must also be connected if they are being used in the end application: ? pgc/pgd pins used for in-circuit serial programming? (icsp?) and debugging purposes (see section 2.5 ?icsp pins? ) ? osc1 and osc2 pins when an external oscillator source is used (see section 2.6 ?external oscillator pins? ) additionally, the following pins may be required: ?v ref +/v ref - pins are used when external voltage reference for analog modules is implemented the minimum mandatory connections are shown in figure 2-1 . figure 2-1: recommended minimum connections pic18f2x/45k50 v dd v ss v dd v ss v ss v dd v dd v ss c1 r1 v dd mclr v usb 3 v 3 r2 c7 (2) c2 (2) c3 (2) c4 (2) c6 (2) key (all values are recommendations): c1 through c6: 0.1 ? f, 20v ceramic r1: 10 k ? r2: 100 ? to 470 ? note 1: see section 2.4 ?voltage regulator pins (v usb 3 v 3)? for explanation of v usb 3 v 3 pin connections. 2: the example shown is for a pic18f device with five v dd /v ss pairs. other devices may have more or less pairs; adjust the number of decoupling capacitors appropriately. (1) www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 26 ? 2012 microchip technology inc. 2.2 power supply pins 2.2.1 decoupling capacitors the use of decoupling capacitors on every pair of power supply pins, such as v dd and v ss is required. consider the following criteria when using decoupling capacitors: ? value and type of capacitor: a 0.1 ? f (100 nf), 10-20v capacitor is recommended. the capacitor should be a low-esr device, with a resonance frequency in the range of 200 mhz and higher. ceramic capacitors are recommended. ? placement on the printed circuit board: the decoupling capacitors should be placed as close to the pins as possible. it is recommended to place the capacitors on the same side of the board as the device. if space is constricted, the capacitor can be placed on another layer on the pcb using a via; however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch (6 mm). ? handling high-frequency noise: if the board is experiencing high-frequency noise (upward of tens of mhz), add a second ceramic type capaci- tor in parallel to the above described decoupling capacitor. the value of the second capacitor can be in the range of 0.01 ? f to 0.001 ? f. place this second capacitor next to each primary decoupling capacitor. in high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible (e.g., 0.1 ? f in parallel with 0.001 ? f). ? maximizing performance: on the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. this ensures that the decoupling capacitors are first in the power chain. equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing pcb trace inductance. 2.2.2 tank capacitors on boards with power traces running longer than six inches in length, it is suggested to use a tank capac- itor for integrated circuits, including microcontrollers, to supply a local power source. the value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. in other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. typical values range from 4.7 ? f to 47 ? f. 2.3 master clear (mclr ) pin the mclr pin provides two specific device functions: device reset, and device programming and debugging. if programming and debugging are not required in the end application, a direct connection to v dd may be all that is required. the addition of other components, to help increase the application?s resistance to spurious resets from voltage sags, may be beneficial. a typical configuration is shown in figure 2-1 . other circuit designs may be implemented, depending on the application?s requirements. during programming and debugging, the resistance and capacitance that can be added to the pin must be considered. device programmers and debuggers drive the mclr pin. consequently, specific voltage levels (v ih and v il ) and fast signal transitions must not be adversely affected. therefore, specific values of r1 and c1 will need to be adjusted based on the application and pcb requirements. for example, it is recommended that the capacitor, c1, be isolated from the mclr pin during programming and debugging operations by using a jumper ( figure 2-2 ). the jumper is replaced for normal run-time operations. any components associated with the mclr pin should be placed within 0.25 inch (6 mm) of the pin. figure 2-2: example of mclr pin connections note 1: r1 ?? 10 k ? is recommended. a suggested starting value is 10 k ? . ensure that the mclr pin v ih and v il specifications are met. 2: r2 ?? 470 ? will limit any current flowing into mclr from the external capacitor, c, in the event of mclr pin breakdown, due to electrostatic discharge (esd) or electrical overstress (eos). ensure that the mclr pin v ih and v il specifications are met. c1 r2 r1 v dd mclr pic18f2x/45k50 jp www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 27 pic18(l)f2x/45k50 2.4 voltage regulator pins (v usb 3 v 3 ) the on-chip voltage regulator must always be connected directly to either a supply voltage or to an external capacitor. when the regulator is enabled (f devices), a low-esr (< 5 ? ) capacitor is required on the v usb 3 v 3 pin to stabilize the voltage regulator output voltage. the v usb 3 v 3 pin must not be connected to v dd and is recommended to use a ceramic capacitor of between 0.22 to 0.47 f connected to ground. it is recommended that the trace length not exceed 0.25 inch (6 mm). refer to section 29.0 ?electrical characteristics? for additional information. when the regulator is disabled (lf devices), the v usb 3 v 3 pin should be externally tied to a voltage source maintained at the v dd level. refer to section 29.0 ?electrical characteristics? for information on v dd and v usb 3 v 3 . ? lf devices (with the name, pic18lf2x/45k50) permanently disable the voltage regulator. the v dd level of these devices must comply with the ?voltage regulator disabled? specification for parameter d001, in section 29.0 ?electrical characteristics? . ? f devices permanently enable the voltage regulator. these devices require an external capacitor on the v usb 3 v 3 pin. it is recommended that the capacitor be a ceramic cap between 0.22 to 0.47 f. 2.4.1 considerations for ceramic capacitors in recent years, large value, low-voltage, surface-mount ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. the low-esr, small physical size and other properties make ceramic capacitors very attractive in many types of applications. ceramic capacitors are suitable for use with the inter- nal voltage regulator of this microcontroller. however, some care is needed in selecting the capacitor to ensure that it maintains sufficient capacitance over the intended operating range of the application. typical low-cost, ceramic capacitors are available in x5r, x7r and y5v dielectric ratings (other types are also available, but are less common). the initial toler- ance specifications for these types of capacitors are often specified as 10% to 20% (x5r and x7r), or -20%/+80% (y5v). however, the effective capacitance that these capacitors provide in an application circuit will also vary based on additional factors, such as the applied dc bias voltage and the temperature. the total in-circuit tolerance is, therefore, much wider than the initial tolerance specification. the x5r and x7r capacitors typically exhibit satisfac- tory temperature stability (ex: 15% over a wide temperature range, but consult the manufacturer?s data sheets for exact specifications). however, y5v capaci- tors typically have extreme temperature tolerance specifications of +22%/-82%. due to the extreme temperature tolerance, a 10 ? f nominal rated y5v type capacitor may not deliver enough total capacitance to meet minimum internal voltage regulator stability and transient response requirements. therefore, y5v capacitors are not recommended for use with the internal regulator if the application must operate over a wide temperature range. in addition to temperature tolerance, the effective capacitance of large value ceramic capacitors can vary substantially, based on the amount of dc voltage applied to the capacitor. this effect can be very signifi- cant, but is often overlooked or is not always documented. a typical dc bias voltage vs. capacitance graph for x7r type and y5v type capacitors is shown in figure 2-3 . figure 2-3: dc bias voltage vs. capacitance characteristics when selecting a ceramic capacitor to be used with the internal voltage regulator, it is suggested to select a high-voltage rating, so that the operating voltage is a small percentage of the maximum rated capacitor voltage. for example, choose a ceramic capacitor rated at 16v for the 3.3v v usb 3 v 3 voltage. -80 -70 -60 -50 -40 -30 -20 -10 0 10 5 1011121314151617 dc bias voltage (vdc) capacitance change (%) 01234 6789 16v capacitor 10v capacitor 6.3v capacitor www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 28 ? 2012 microchip technology inc. 2.5 icsp pins the pgc and pgd pins are used for in-circuit serial programming? (icsp?) and debugging purposes. it is recommended to keep the trace length between the icsp connector and the icsp pins on the device as short as possible. if the icsp connector is expected to experience an esd event, a series resistor is recom- mended, with the value in the range of a few tens of ohms, not to exceed 100 ? . pull-up resistors, series diodes and capacitors on the pgc and pgd pins are not recommended as they will interfere with the programmer/debugger communica- tions to the device. if such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. alter- natively, refer to the ac/dc characteristics and timing requirements information in the respective device flash programming specification for information on capacitive loading limits, and pin input voltage high (v ih ) and input low (v il ) requirements. for device emulation, ensure that the ?communication channel select? (i.e., pgcx/pgdx pins), programmed into the device, matches the physical connections for the icsp to the microchip debugger/emulator tool. for more information on available microchip development tools connection requirements, refer to section 28.0 ?development support? . 2.6 external oscillator pins many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to section 3.0 ?oscillator module (with fail-safe clock monitor)? for details). the oscillator circuit should be placed on the same side of the board as the device. place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins. the load capacitors should be placed next to the oscillator itself, on the same side of the board. use a grounded copper pour around the oscillator cir- cuit to isolate it from surrounding circuits. the grounded copper pour should be routed directly to the mcu ground. do not run any signal traces or power traces inside the ground pour. also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. layout suggestions are shown in figure 2-4. in-line packages may be handled with a single-sided layout that completely encompasses the oscillator pins. with fine-pitch packages, it is not always possible to com- pletely surround the pins and components. a suitable solution is to tie the broken guard sections to a mirrored ground layer. in all cases, the guard trace(s) must be returned to ground. in planning the application?s routing and i/o assign- ments, ensure that adjacent port pins, and other signals in close proximity to the oscillator, are benign (i.e., free of high frequencies, short rise and fall times, and other similar noise). for additional information and design guidance on oscillator circuits, please refer to these microchip application notes, available at the corporate web site (www.microchip.com): ? an826, ? crystal oscillator basics and crystal selection for rfpic? and picmicro ? devices? ? an849, ?basic picmicro ? oscillator design? ? an943, ?practical picmicro ? oscillator analysis and design? ? an949, ?making your oscillator work? 2.7 unused i/os unused i/o pins should be configured as outputs and driven to a logic low state. alternatively, connect a 1 k ? to 10 k ? resistor to v ss on unused pins and drive the output to logic low. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 29 pic18(l)f2x/45k50 figure 2-4: suggested placement of the oscillator circuit gnd ` ` ` osc1 osc2 sosco sosci copper pour primary oscillator crystal timer1 oscillator crystal device pins primary oscillator c1 c2 t1 oscillator: c1 t1 oscillator: c2 (tied to ground) single-sided and in-line layouts: fine-pitch (dual-sided) layouts: gnd osco osci bottom layer copper pour oscillator crystal top layer copper pour c2 c1 device pins (tied to ground) (tied to ground) www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 30 ? 2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 31 pic18(l)f2x/45k50 3.0 oscillator module (with fail-safe clock monitor) 3.1 overview the oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing perfor- mance and minimizing power consumption. figure 3-1 illustrates a block diagram of the oscillator module. clock sources can be configured from external oscillators, quartz crystal resonators, ceramic resonators and resistor-capacitor (rc) circuits. in addition, the system clock source can be configured from one of three internal oscillators, with a choice of speeds selectable via software. additional clock features include: ? selectable system clock source between external or internal sources via software. ? two-speed start-up mode, which minimizes latency between external oscillator start-up and code execution. ? fail-safe clock monitor (fscm) designed to detect a failure of the external clock source (lp, xt, hs, ec or rc modes) and switch automatically to the internal oscillator. ? oscillator start-up timer (ost) ensures stability of crystal oscillator sources. the primary clock module can be configured to provide one of six clock sources as the primary clock. 1. rc external resistor/capacitor 2. lp low-power crystal 3. xt crystal/resonator 4. intosc internal oscillator 5. hs high-speed crystal/resonator 6. ec external clock the hs and ec oscillator circuits can be optimized for power consumption and oscillator speed using settings in fosc<3:0>. additional fosc<3:0> selections enable ra6 to be used as i/o or clko (f osc /4) for rc, ec and intosc oscillator modes. primary clock modes are selectable by the fosc<3:0> bits of the config1h configuration register. the primary clock operation is further defined by these configuration and register bits: 1. pclken (config1h<5>) 2. prisd (osccon2<2>) 3. cfgpllen (config1l<1>) 4. pllen (osccon2<4>) 5. ircf<2:0> (osccon<6:4>) 6. intsrc (osccon2<5>) the hfintosc and intrc are factory calibrated high and low-frequency oscillators, respectively, which are used as the internal clock sources. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 32 ? 2012 microchip technology inc. figure 3-1: simplified osci llator system block diagram note 1: details in figure 3-3 . 2: details in figure 3-2 . 3: details in ta b l e 3 - 1 . 4: the primary oscillator mux uses the intosc branch when fosc<3:0> = 100x . sosco sosci secondary oscillator (sosc) secondary oscillator (1) osc2 osc1 primary oscillator (2) (osc) primary oscillator 0 1 fosc<3:0> (4) pll_select (3) 0 1 4xpll intosc primary clock module low-power mode event switch (scs<1:0>) 01 00 1x secondary oscillator 2 primary clock intosc clock switch mux intosc ircf<2:0> intsrc hf-16 mh z hf-8 mh z hf-4 mh z hf-2 mh z hf-1 mh z hf-31.25 kh z hf-250 kh z hf-500 kh z hfintosc intrc (16 mhz) (31.25 khz) intosc divide circuit internal oscillator mux (3) lf-31.25 khz 3 3 internal oscillator soscout pclken prisd en 3x or cpu peripherals idle ? 4 ra6 clko enabled modes usb module 1 0 fsen ? 8 1 0 ? 4 ls48mhz clock needs 48 mhz for fs needs 6 mhz for ls pll postscaler ? 2 ? 3 ? 4 ? 6 11 10 01 00 cpudiv www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 33 pic18(l)f2x/45k50 3.2 oscillator control the osccon, osccon2 and osctune registers ( register 3-1 to register 3-3 ) control several aspects of the device clock?s operation, both in full-power operation and in power-managed modes. ? main system clock selection (scs) ? primary oscillator circuit shutdown (prisd) ? secondary oscillator enable (soscgo) ? primary clock frequency multiplier (pllen) ? internal frequency selection bits (ircf, intsrc) ? clock status bits (osts, hfiofs, lfiofs, soscrun, pllrdy) ? power management selection (idlen) 3.2.1 main system clock selection the system clock select bits, scs<1:0>, select the main clock source. the available clock sources are: ? primary clock defined by the fosc<3:0> bits of config1h. the primary clock can be the primary oscillator, an external clock, or the internal oscillator block. ? secondary clock (secondary oscillator) ? internal oscillator block (hfintosc and intrc). the clock source changes immediately after one or more of the bits is written to, following a brief clock transition interval. the scs bits are cleared to select the primary clock on all forms of reset. 3.2.2 internal frequency selection the internal oscillator frequency select bits (ircf<2:0>) select the frequency output of the internal oscillator block. the choices are the intrc source (31.25 khz) and the hfintosc source (16 mhz) or one of the frequencies derived from the hfintosc postscaler (31.25 khz to 16 mhz). if the internal oscil- lator block is supplying the main clock, changing the states of these bits will have an immediate change on the internal oscillator?s output. on device resets, the output frequency of the internal oscillator is set to the default frequency of 1 mhz. 3.2.3 low-frequency selection when a nominal output frequency of 31.25 khz is selected (ircf<2:0> = 000 ), users may choose which internal oscillator acts as the source. this is done with the intsrc bit of the osccon2<5> register. see figure 3-2 and register 3-1 for specific 31.25 khz selection. this option allows users to select a 31.25 khz clock (based on hfintosc) that can be tuned using the tun<6:0> bits in the osctune register, while maintaining power savings with a very low clock speed. intrc always remains the clock source for features such as the watchdog timer and the fail-safe clock monitor, regardless of the setting of the intsrc bit. this option allows users to select the tunable and more precise hfintosc as a clock source, while maintaining power savings with a very low clock speed. 3.2.4 power management the idlen bit of the osccon register determines whether the device goes into sleep mode or one of the idle modes when the sleep instruction is executed. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 34 ? 2012 microchip technology inc. figure 3-2: internal oscillator mux block diagram figure 3-3: secondary oscilla tor and external clock inputs 111 110 101 100 000 intosc 31.25 khz 1 0 ircf<2:0> intsrc hf-16 mhz hf-8 mhz hf-4 mhz hf-2 mhz hf-1 mhz lf-31.25 khz hf-31.25 khz 3 011 hf-500 khz 010 hf-250 khz 001 table 3-1: pll_select truth table primary clock mux source fosc<3:0> cfgpllen pllsel pllen spllmult pll_select external clock (echio/echclko) 010x 1 1x x 3xpll (1) 0x x 4xpll (2) hs crystal (hsh) 0010 0 x 1 1 3xpll (1) 0 4xpll (2) intosc (intoscio, intoscclko) 100x 0 x off f osc (all other modes) xxxx x x x x off note 1: the input clock source must be 16 mhz when 3xpll is used. 2: the input clock source must be 8 mhz to 12 mhz when 4xpll is used. 0 1 1 0 en soscen soscgo t1con<3> t3con<3> to clock switch module soscout secondary oscillator sosci sosco t1cki t3g t3cki soscen soscen soscen t3g t3cmx t1g t3cki t1g 1 0 t1con<3> t1clk_ext_src t3clk_ext_src t3con<3> www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 35 pic18(l)f2x/45k50 3.3 register definitions: oscillator control register 3-1: osccon: os cillator control register r/w-0 r/w-0 r/w-1 r/w-1 r-q r-0 r/w-0 r/w-0 idlen ircf<2:0> osts (1) hfiofs scs<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? q = depends on condition -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 idlen: idle enable bit 1 = device enters idle mode on sleep instruction 0 = device enters sleep mode on sleep instruction bit 6-4 ircf<2:0>: internal rc oscillator frequency select bits 111 = hfintosc ? (16 mhz) 110 = hfintosc/2 ? (8 mhz) 101 = hfintosc/4 ? (4 mhz) 100 = hfintosc/8 ? (2 mhz) 011 = hfintosc/16 ? (1 mhz) (2) 010 = hfintosc/32 ? (500 khz) 001 = hfintosc/64 ? (250 khz) if intsrc = 1 : 000 = hfintosc/512 ? (31.25 khz) if intsrc = 0 : 000 = intrc ? (31.25 khz) bit 3 osts: oscillator start-up time-out status bit 1 = device is running from the clock defined by fosc<3:0> of the config1h register 0 = device is running from the internal oscillator (hfintosc or intrc) bit 2 hfiofs: hfintosc frequency stable bit 1 = hfintosc frequency is stable 0 = hfintosc frequency is not stable bit 1-0 scs<1:0>: system clock select bit 1x = internal oscillator block 01 = secondary (sosc) oscillator 00 = primary clock (determined by fosc<3:0> in config1h). note 1: reset state depends on state of the ieso configuration bit. 2: default output frequency of hfintosc on reset. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 36 ? 2012 microchip technology inc. register 3-2: osccon2: osci llator control register 2 r-0/0 r-0/q r/w-0 r/w-0/0 r/w-0/u r/w-1/1 r-0/0 r-0/0 pllrdy soscrun intsrc pllen soscgo (1) prisd hfiofr lfiofs bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? q = depends on condition ?1? = bit is set ?0? = bit is cleared x = bit is unknown -n/n = value at por and bor/value at all other resets bit 7 pllrdy: pll run status bit 1 = system clock comes from pll 0 = system clock comes from an oscillator, other than pll bit 6 soscrun: sosc run status bit 1 = system clock comes from secondary sosc 0 = system clock comes from an oscillator, other than sosc bit 5 intsrc: hfintosc divided by 512 enable bit 1 = hfintosc used as the 31.25 khz system clock reference ? high accuracy 0 = intrc used as the 31.25 khz system clock reference ? low power. bit 4 pllen: software pll enable bit if fosc<3:0> = 100x, 010x or 001x 1 = pll enabled 0 = pll disabled else, no effect on pll operation. bit 3 soscgo (1) : secondary oscillator start control bit 1 = secondary oscillator is enabled. 0 = secondary oscillator is shut off if no other sources are requesting it. bit 2 prisd: primary oscillator drive circuit shutdown bit 1 = oscillator drive circuit on 0 = oscillator drive circuit off (zero power) bit 1 hfiofr: hfintosc status bit 1 = hfintosc is running 0 = hfintosc is not running bit 0 lfiofs: intrc frequency stable bit 1 = intrc is stable 0 = intrc is not stable note 1: the soscgo bit is only reset on a por reset. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 37 pic18(l)f2x/45k50 3.4 clock source modes clock source modes can be classified as external or internal. ? external clock modes rely on external circuitry for the clock source. examples are: clock modules (ec mode), quartz crystal resonators or ceramic resonators (lp, xt and hs modes) and resistor- capacitor (rc mode) circuits. ? internal clock sources are contained internally within the oscillator block. the oscillator block has two internal oscillators: the 16 mhz high- frequency internal oscillator (hfintosc) and the 31.25 khz low-frequency internal oscillator (intrc). the system clock can be selected between external or internal clock sources via the system clock select (scs<1:0>) bits of the osccon register. see section 3.11 ?clock switching? for additional information. 3.5 external clock modes 3.5.1 oscillator start-up timer (ost) when the oscillator module is configured for lp, xt or hs modes, the oscillator start-up timer (ost) counts 1024 oscillations from osc1. this occurs following a power-on reset (por) and when the power-up timer (pwrt) has expired (if configured), or a wake-up from sleep. during this time, the program counter does not increment and program execution is suspended. the ost ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the oscillator module. when switching between clock sources, a delay is required to allow the new clock to stabilize. these oscillator delays are shown in table 3-2 . in order to minimize latency between external oscillator start-up and code execution, the two-speed clock start-up mode can be selected (see section 3.12 ?two-speed clock start-up mode? ). table 3-2: oscillator delay examples 3.5.2 ec mode the external clock (ec) mode allows an externally generated logic level as the system clock source. when operating in this mode, an external clock source is connected to the osc1 input and the osc2 is available for general purpose i/o. figure 3-4 shows the pin connections for ec mode. the external clock (ec) offers different power modes, low power (ecl), medium power (ecm) and high power (ech), selectable by the fosc<3:0> bits. each mode is best suited for a certain range of frequencies. the ranges are: ? ecl ? below 4 mhz ? ecm ? between 4 mhz and 16 mhz ? ech ? above 16 mhz the oscillator start-up timer (ost) is disabled when ec mode is selected. therefore, there is no delay in operation after a power-on reset (por) or wake-up from sleep. because the pic ? mcu design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. upon restarting the external clock, the device will resume operation as if no time had elapsed. figure 3-4: external clock (ec) mode operation switch from switch to frequency oscillator delay sleep/por intrc hfintosc 31.25 khz 31.25 khz to 16 mhz oscillator warm-up delay (t warm ) sleep/por ec, rc dc ? 48 mhz 2 instruction cycles intrc (31.25 khz) ec, rc dc ? 48 mhz 1 cycle of each sleep/por lp, xt, hs 32 khz to 25 mhz 1024 clock cycles (ost) sleep/por pll 32 mhz to 48 mhz 1024 clock cycles (ost) + 2 ms intrc (31.25 khz) intrc hfintosc 31.25 khz to 16 mhz 1 ? s (approx.) osc1/clkin osc2/clko i/o clock from ext. system pic ? mcu www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 38 ? 2012 microchip technology inc. 3.5.3 lp, xt, hs modes the lp, xt and hs modes support the use of quartz crystal resonators or ceramic resonators connected to osc1 and osc2 ( figure 3-5 ). the mode selects a low, medium or high gain setting of the internal inverter- amplifier to support various resonator types and speed. lp oscillator mode selects the lowest gain setting of the internal inverter-amplifier. lp mode current consumption is the least of the three modes. this mode is best suited to drive resonators with a low drive level specification, for example, tuning fork type crystals. xt oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. xt mode current consumption is the medium of the three modes. this mode is best suited to drive resonators with a medium drive level specification. hs oscillator mode offers a medium power (mp) and a high power (hp) option selectable by the fosc<3:0> bits. the mp selections are best suited for oscillator frequencies between 4 and 16 mhz. the hp selection has the highest gain setting of the internal inverter- amplifier and is best suited for frequencies above 16 mhz. hs mode is best suited for resonators that require a high drive setting. figure 3-5: quartz crystal operation (lp, xt or hs mode) figure 3-6: ceramic resonator operation (xt or hs mode) note 1: a series resistor (r s ) may be required for quartz crystals with low drive level. 2: the value of r f varies with the oscillator mode selected (typically between 2 m ? to 10 m ?? . c1 c2 quartz r s (1) osc1/clkin r f (2) sleep to internal logic pic ? mcu crystal osc2/clko note 1: quartz crystal characteristics vary according to type, package and manufacturer. the user should consult the manufacturer data sheets for specifications and recommended application. 2: always verify oscillator performance over the v dd and temperature range that is expected for the application. 3: for oscillator design assistance, refer to the following microchip application notes: ? an826, ? crystal oscillator basics and crystal selection for rfpic ? and pic ? devices ? (ds00826) ? an849, ? basic pic ? oscillator design ? (ds00849) ? an943, ? practical pic ? oscillator analysis and design ? (ds00943) ? an949, ? making your oscillator work ? (ds00949) note 1: a series resistor (r s ) may be required for ceramic resonators with low drive level. 2: the value of r f varies with the oscillator mode selected (typically between 2 m ? to 10 m ?? . 3: an additional parallel feedback resistor (r p ) may be required for proper ceramic resonator operation. c1 c2 ceramic r s (1) osc1/clkin r f (2) sleep to internal logic pic ? mcu r p (3) resonator osc2/clko www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 39 pic18(l)f2x/45k50 3.5.4 external rc modes the external resistor-capacitor (rc) modes support the use of an external rc circuit. this allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. there are two modes: rc and rcio. 3.5.4.1 rc mode in rc mode, the rc circuit connects to osc1. osc2/ clko outputs the rc oscillator frequency divided by 4. this signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. figure 3-7 shows the external rc mode connections. figure 3-7: external rc modes 3.5.4.2 rcio mode in rcio mode, the rc circuit is connected to osc1. osc2 becomes a general purpose i/o pin. the rc oscillator frequency is a function of the supply voltage, the resistor (r ext ) and capacitor (c ext ) values and the operating temperature. other factors affecting the oscillator frequency are: ? input threshold voltage variation ? component tolerances ? packaging variations in capacitance the user also needs to take into account variation due to tolerance of external rc components used. 3.6 internal clock modes the oscillator module has two independent, internal oscillators that can be configured or selected as the system clock source. 1. the hfintosc (high-frequency internal oscillator) is factory calibrated and operates at 16 mhz. the frequency of the hfintosc can be user-adjusted via software using the osctune register ( register 3-3 ). 2. the intrc (low-frequency internal oscillator) is factory calibrated and operates at 31.25 khz. the intrc cannot be user-adjusted, but is designed to be stable over temperature and voltage. the system clock speed can be selected via software using the internal oscillator frequency select bits ircf<2:0> of the osccon register. the intsrc bit allows users to select which internal oscillator provides the clock source for the 31.25 khz frequency option. this is covered in greater detail in section 3.2.3 ?low- frequency selection? . the system clock can be selected between external or internal clock sources via the system clock selection (scs<1:0>) bits of the osccon register. see section 3.11 ?clock switching? for more information. 3.6.1 intosc with i/o or clockout two of the clock modes selectable with the fosc<3:0> bits of the config1h configuration register configure the internal oscillator block as the primary oscillator. mode selection determines whether osc2/clko/ra6 will be configured as general purpose i/o (ra6) or f osc /4 (clko). in both modes, osc1/clkin/ra6 is configured as general purpose i/o. see section 26.0 ?special features of the cpu? for more information. the clko signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. osc2/clko (1) c ext r ext pic ? mcu osc1/clkin f osc /4 or internal clock v dd v ss recommended values: 10 k ? ? r ext ? 100 k ? c ext > 20 pf note 1: alternate pin functions are listed in section 1.0 ?device overview? . 2: output depends upon rc or rcio clock mode. i/o (2) www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 40 ? 2012 microchip technology inc. 3.6.1.1 osctune register the hfintosc oscillator circuits are factory calibrated but can be adjusted in software by writing to the tun<6:0> bits of the osctune register ( register 3- 3 ). the default value of the tun<6:0> is ? 0 ?. the value is a 7-bit two?s complement number. when the osctune register is modified, the hfintosc frequency will begin shifting to the new frequency. code execution continues during this shift. there is no indication that the shift has occurred. the tun<6:0> bits in osctune do not affect the intrc frequency. operation of features that depend on the intrc clock source frequency, such as the power- up timer (pwrt), watchdog timer (wdt), fail-safe clock monitor (fscm) and peripherals, are not affected by the change in frequency. the osctune register also implements the spllmult bit, which controls whether 3x or 4xpll clock multiplication is used when the pll is enabled dynamically in software. for more details about the function of the spllmult bit see section 3.8.2 ?pll in hfintosc modes? . 3.7 register definitions: oscillator tuning register 3-3: osctune: osci llator tuning register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 spllmult tun<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 spllmult: software pll multiplier select bit if pll enabled, spllmult changes are ignored. else, selects which pll multiplier will be used: 1 = 3xpll is selected 0 = 4xpll is selected bit 6-0 tun<6:0>: frequency tuning bits ? affects hfintosc (1) 0111111 = maximum frequency 0111110 = ? ? ? 0000001 = 0000000 = center frequency. oscillator module is running at the factory calibrated frequency. 1111111 = ? ? ? 1000000 = minimum frequency note 1: the tun<6:0> bits may be supplied and controlled by the active clock tuning module (see section 3.15 ?active clock tuning (act) module? ) when the active clock tuning is enabled, the tun<6:0> bits are read-only. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 41 pic18(l)f2x/45k50 3.7.1 intrc the low-frequency internal oscillator (intrc) is a 31.25 khz internal clock source. the intrc is not tunable, but is designed to be stable across temperature and voltage. see section 29.0 ?electrical characteristics? for the intrc accuracy specifications. the output of the intrc can be a clock source to the primary clock or the intosc clock (see figure 3-1 ). the intrc is also the clock source for the power-up timer (pwrt), watchdog timer (wdt) and fail-safe clock monitor (fscm). 3.7.2 frequency select bits (ircf) the hfintosc (16 mhz) outputs to a divide circuit that provides frequencies of 16 mhz to 31.25 khz. these divide circuit frequencies, along with the 31.25 khz intrc output, are multiplexed to provide a single intosc clock output (see figure 3-1 ). the ircf<2:0> bits of the osccon register and the intsrc bit of the osccon2 register select the output frequency of the internal oscillators. one of eight frequencies can be selected via software: ?16 mhz ?8 mhz ?4 mhz ?2 mhz ? 1 mhz (default after reset) ? 500 khz ? 250 khz ? 31 khz (intrc or hfintosc) 3.7.3 intosc frequency drift the factory calibrates the internal oscillator block outputs (hfintosc) for 16 mhz. however, this frequency may drift as v dd or temperature changes. it is possible to automatically tune the hfintosc frequency using usb or secondary oscillator sources using the active clock tuning module (see section 3.15 ?active clock tuning (act) module? ). the hfintosc frequency may be manually adjusted using the tun<6:0> bits in the osctune register. this has no effect on the intrc clock source frequency. manually tuning the hfintosc source requires knowing when to make the adjustment, in which direction it should be made and, in some cases, how large a change is needed. three possible compensation techniques are discussed in the following sections. however, other techniques may be used. 3.7.3.1 compensating with the eusart an adjustment may be required when the eusart begins to generate framing errors or receives data with errors while in asynchronous mode. framing errors indicate that the device clock frequency is too high; to adjust for this, decrement the value in osctune to reduce the clock frequency. on the other hand, errors in data may suggest that the clock speed is too low; to compensate, increment osctune to increase the clock frequency. 3.7.3.2 compensating with the timers this technique compares device clock speed to some reference clock. two timers may be used; one timer is clocked by the peripheral clock, while the other is clocked by a fixed reference source, such as the timer1 oscillator. both timers are cleared, but the timer clocked by the reference generates interrupts. when an interrupt occurs, the internally clocked timer is read and both timers are cleared. if the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast. to adjust for this, decrement the osctune register. 3.7.3.3 compensating with the ccp module in capture mode a ccp module can use free running timer1 or timer3 clocked by the internal oscillator block and an external event with a known period (i.e., ac power frequency). the time of the first event is captured in the ccprxh:ccprxl registers and is recorded for use later. when the second event causes a capture, the time of the first event is subtracted from the time of the second event. since the period of the external event is known, the time difference between events can be calculated. if the measured time is much greater than the calculated time, the internal oscillator block is running too fast; to compensate, decrement the osctune register. if the measured time is much less than the calculated time, the internal oscillator block is running too slow; to compensate, increment the osctune register. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 42 ? 2012 microchip technology inc. 3.8 pll frequency multiplier a phase-locked loop (pll) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from the crystal oscillator. this may be useful for customers who are concerned with emi due to high-frequency crystals or users who require higher clock speeds from an internal oscillator. 3.8.1 pll in external oscillator modes the pll can be enabled for any of the external oscillator modes using the osc1/osc2 pins. medium- power and low-power oscillator mode selections in config1h<3:0> (fosc) should not be used with the pll. the pll can be enabled using the cfgpllen/ pllsel configuration bits in the config1l register, or by software using the pllen/spllmult special function register bits in osccon2 and osctune, respectively. a selectable 3x or 4x frequency multiplier circuit is provided. this gives greater flexibility in source clock frequencies that can be used. source clock frequencies between 8 and 12 mhz may use the 4x frequency multiplier to achieve operating speeds of 32 through 48 mhz. a source clock frequency of 16 mhz may use the 3x frequency multiplier to achieve 48 mhz operating speed. 3.8.2 pll in hfintosc modes the pll can be enabled using the hfintosc internal oscillator block. the frequency select bits (ircf<2:0> in the osccon register) should be configured for 16 mhz when using the hfintosc with 3x frequency multiplier. the ircf bits should be configured for 8 mhz when using hfintosc with 4x frequency multiplier. 3.9 effects of power-managed modes on the various clock sources for more information about the modes discussed in this section see section 4.0 ?power-managed modes? . a quick reference list is also available in ta b l e 4 - 1 . when pri_idle mode is selected, the designated primary oscillator continues to run without interruption. for all other power-managed modes, the oscillator using the osc1 pin is disabled. the osc1 pin (and osc2 pin, if used by the oscillator) will stop oscillating. in secondary clock modes (sec_run and sec_idle), the secondary oscillator (sosc) is operating and providing the device clock. the secondary oscillator may also run in all power- managed modes if required to clock timer1 or timer3. in internal oscillator modes (intosc_run and intosc_idle), the internal oscillator block provides the device clock source. the 31.25 khz intrc output can be used directly to provide the clock and may be enabled to support various special features, regardless of the power-managed mode (see section 26.3 ?watchdog timer (wdt)? , section 3.12 ?two- speed clock start-up mode? and section 3.13 ?fail- safe clock monitor? for more information on wdt, fail-safe clock monitor and two-speed start-up). the hfintosc output may be used directly to clock the device or may be divided down by the postscaler. the hfintosc output is disabled when the clock is provided directly from the intrc output. when the sleep mode is selected, all clock sources are stopped. since all the transistor switching currents have been stopped, sleep mode achieves the lowest current consumption of the device (only leakage currents). enabling any on-chip feature that will operate during sleep will increase the current consumed during sleep. the intrc is required to support wdt operation. other features may be operating that do not require a device clock source (i.e., ssp slave, intn pins and others). peripherals that may add significant current consumption are listed in section 29.8 ?dc characteristics: input/output characteristics, pic18(l)f2x/45k50? . www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 43 pic18(l)f2x/45k50 3.10 power-up delays power-up delays are controlled by two timers, so that no external reset circuitry is required for most applications. the delays ensure that the device is kept in reset until the device power supply is stable under normal circumstances and the primary clock is operating and stable. for additional information on power-up delays, see section 5.7 ?device reset timers? . the first timer is the power-up timer (pwrt), which provides a fixed delay on power-up. it is enabled by clearing (= 0 ) the pwrten configuration bit. the second timer is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable (lp, xt and hs modes). the ost does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device. when the pll is enabled with external oscillator modes, the device runs off of the base external oscilla- tor for 2 ms, following the ost delay, so the pll can lock to the incoming clock frequency. there is a delay of interval t csd , following por, while the controller becomes ready to execute instructions. this delay runs concurrently with any other delays. this may be the only delay that occurs when any of the ec, rc or intiosc modes are used as the primary clock source. when the hfintosc is selected as the primary clock, the main system clock can be delayed until the hfintosc is stable. this is user selectable by the hfofst bit of the config3h configuration register. when the hfofst bit is cleared, the main system clock is delayed until the hfintosc is stable. when the hfofst bit is set, the main system clock starts immediately. in either case, the hfiofs bit of the osccon register can be read to determine whether the hfintosc is operating and stable. table 3-3: osc1 and osc2 pin states in sleep mode osc mode osc1 pin osc2 pin rc, intosc with clko floating, external resistor should pull high at logic low (clock/4 output) rc with io floating, external resistor should pull high configured as porta, bit 6 intosc with io configured as porta, bit 7 configured as porta, bit 6 ec with io floating, pulled by external clock configured as porta, bit 6 ec with clko floating, pulled by external clock at logic low (clock/4 output) lp, xt, hs feedback inverter disabled at quiescent voltage level feedback inverter disabled at quiescent voltage level note: see table 5-2 in section 5.0 ?reset? for time-outs due to sleep and mclr reset. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 44 ? 2012 microchip technology inc. 3.11 clock switching the system clock source can be switched between external and internal clock sources via software using the system clock select (scs<1:0>) bits of the osccon register. pic18(l)f2x/45k50 devices contain circuitry to prevent clock ?glitches? when switching between clock sources. a short pause in the device clock occurs during the clock switch. the length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source. this formula assumes that the new clock source is stable. clock transitions are discussed in greater detail in section 4.1.2 ?entering power-managed modes? . 3.11.1 system clock select (scs<1:0>) bits the system clock select (scs<1:0>) bits of the osccon register select the system clock source that is used for the cpu and peripherals. ? when scs<1:0> = 00 , the system clock source is determined by configuration of the fosc<3:0> bits in the config1h configuration register. ? when scs<1:0> = 10 , the system clock source is chosen by the internal oscillator frequency selected by the intsrc bit of the osccon2<5> register and the ircf<2:0> bits of the osccon register. ? when scs<1:0> = 01 , the system clock source is the 32.768 khz secondary oscillator shared with timer1 and timer3. after a reset, the scs<1:0> bits of the osccon register are always cleared. 3.11.2 oscillator start-up time-out status (osts) bit the oscillator start-up time-out status (osts) bit of the osccon register indicates whether the system clock is running from the external clock source, as defined by the fosc<3:0> bits in the config1h configuration register, or from the internal clock source. in particular, when the primary oscillator is the source of the primary clock, osts indicates that the oscillator start-up timer (ost) has timed out for lp, xt or hs modes. 3.11.3 clock switch timing when switching between one oscillator and another, the new oscillator may not be operating which saves power (see figure 3-8 ). if this is the case, there is a delay after the scs<1:0> bits of the osccon register are modified before the frequency change takes place. the osts and hfiofr, lfiofs bits of the osccon and osccon2 registers will reflect the current active status of the external and hfintosc oscillators. the timing of a frequency selection is as follows: 1. scs<1:0> bits of the osccon register are modified. 2. the old clock continues to operate until the new clock is ready. 3. clock switch circuitry waits for two consecutive rising edges of the old clock after the new clock ready signal goes true. 4. the system clock is held low starting at the next falling edge of the old clock. 5. clock switch circuitry waits for an additional two rising edges of the new clock. 6. on the next falling edge of the new clock the low hold on the system clock is released and new clock is switched in as the system clock. 7. clock switch is complete. see figure 3-1 for more details. if the hfintosc is the source of both the old and new frequency, there is no start-up delay before the new frequency is active. this is because the old and new frequencies are derived from the hfintosc via the postscaler and multiplexer. start-up delay specifications are located in section 29.0 ?electrical characteristics? , under ac specifications (oscillator module). note: any automatic clock switch, which may occur from two-speed start-up or fail- safe clock monitor, does not update the scs<1:0> bits of the osccon register. the user can monitor the soscrun and lfiofs bits of the osccon2 register, and the hfiofs and osts bits of the osccon register to determine the current system clock source. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 45 pic18(l)f2x/45k50 3.12 two-speed clock start-up mode two-speed start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. in applications that make heavy use of the sleep mode, two-speed start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. this mode allows the application to wake-up from sleep, perform a few instructions using the hfintosc as the clock source and go back to sleep without waiting for the primary oscillator to become stable. when the oscillator module is configured for lp, xt or hs modes, the oscillator start-up timer (ost) is enabled (see section 3.5.1 ?oscillator start-up timer (ost)? ). the ost will suspend program execution until 1024 oscillations are counted. two-speed start-up mode minimizes the delay in code execution by operating from the internal oscillator as the ost is counting. when the ost count reaches 1024 and the osts bit of the osccon register is set, program execution switches to the external oscillator. 3.12.1 two-speed start-up mode configuration two-speed start-up mode is enabled when all of the following settings are configured as noted: ? two-speed start-up mode is enabled when the ieso of the config1h configuration register is set. ? scs<1:0> (of the osccon register) = 00 . ? fosc<2:0> bits of the config1h configuration register are configured for lp, xt or hs mode. two-speed start-up mode becomes active after: ? power-on reset (por) and, if enabled, after power-up timer (pwrt) has expired, or ? wake-up from sleep. note: executing a sleep instruction will abort the oscillator start-up time and will cause the osts bit of the osccon register to remain clear. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 46 ? 2012 microchip technology inc. 3.12.2 two-speed start-up sequence 1. wake-up from power-on reset or sleep. 2. instructions begin executing by the internal oscillator at the frequency set in the ircf<2:0> bits of the osccon register. 3. ost enabled to count 1024 external clock cycles. 4. ost timed out. external clock is ready. 5. osts is set. 6. clock switch finishes according to figure 3-8 3.12.3 checking two-speed clock status checking the state of the osts bit of the osccon register will confirm if the microcontroller is running from the external clock source, as defined by the fosc<2:0> bits in config1h configuration register, or the internal oscillator. osts = 0 when the external oscillator is not ready, which indicates that the system is running from the internal oscillator. figure 3-8: clock switch timing old clock new clock ircf <2:0> system clock start-up time (1) clock sync running high speed low speed select old select new new clk ready low speed high speed old clock new clock ircf <2:0> system clock start-up time (1) clock sync running select old select new new clk ready note 1: start-up time includes t ost (1024 t osc ) for external clocks, plus t pll (approx. 2 ms) for hspll mode. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 47 pic18(l)f2x/45k50 3.13 fail-safe clock monitor the fail-safe clock monitor (fscm) allows the device to continue operating should the external oscillator fail. the fscm can detect oscillator failure any time after the oscillator start-up timer (ost) has expired. the fscm is enabled by setting the fcmen bit in the config1h configuration register. the fscm is applicable to all external oscillator modes (lp, xt, hs, ec, rc and rcio). figure 3-9: fscm block diagram 3.13.1 fail-safe detection the fscm module detects a failed oscillator by comparing the external oscillator to the fscm sample clock. the sample clock is generated by dividing the intrc by 64 (see figure 3-9 ). inside the fail detector block is a latch. the external clock sets the latch on each falling edge of the external clock. the sample clock clears the latch on each rising edge of the sample clock. a failure is detected when an entire half-cycle of the sample clock elapses before the primary clock goes low. 3.13.2 fail-safe operation when the external clock fails, the fscm switches the device clock to an internal clock source and sets the bit flag oscfif of the pir2 register. the oscfif flag will generate an interrupt if the oscfie bit of the pie2 register is also set. the device firmware can then take steps to mitigate the problems that may arise from a failed clock. the system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. an automatic transition back to the failed clock source will not occur. the internal clock source chosen by the fscm is determined by the ircf<2:0> bits of the osccon register. this allows the internal oscillator to be configured before a failure occurs. 3.13.3 fail-safe condition clearing the fail-safe condition is cleared by either one of the following: ?any reset ? by toggling the scs1 bit of the osccon register both of these conditions restart the ost. while the ost is running, the device continues to operate from the intosc selected in osccon. when the ost times out, the fail-safe condition is cleared and the device automatically switches over to the external clock source. the fail-safe condition need not be cleared before the oscfif flag is cleared. 3.13.4 reset or wake-up from sleep the fscm is designed to detect an oscillator failure after the oscillator start-up timer (ost) has expired. the ost is used after waking up from sleep and after any type of reset. the ost is not used with the ec or rc clock modes so that the fscm will be active as soon as the reset or wake-up has completed. external intrc 64 s r q 31 khz (~32 ? s) 488 hz (~2 ms) clock monitor latch clock failure detected oscillator clock q sample clock note: due to the wide range of oscillator start-up times, the fail-safe circuit is not active during oscillator start-up (i.e., after exiting reset or sleep). after an appropriate amount of time, the user should check the osts bit of the osccon register to verify the oscillator start-up and that the system clock switchover has successfully completed. note: when the device is configured for fail- safe clock monitoring in either hs, xt, or ls oscillator modes then the ieso config- uration bit should also be set so that the clock will automatically switch from the internal clock to the external oscillator when the ost times out. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 48 ? 2012 microchip technology inc. figure 3-10: fscm timing diagram oscfif system clock output sample clock failure detected oscillator failure note: the system clock is normally at a much higher frequency than the sample clock. the relative frequencies in this example have been chosen for clarity. (q) te s t test test clock monitor output table 3-4: registers associated with clock sources name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie/gieh peie/giel tmr0ie int0ie iocie tmr0if int0if iocif 120 ipr2 oscfip c1ip c2ip eeip bclip hlvdip tmr3ip ccp2ip 130 osccon idlen ircf<2:0> osts hfiofs scs<1:0> 35 osccon2 pllrdy soscrun intsrc pllen soscgo prisd hfiofr lfiofs 36 osctune spllmult tun<6:0> 40 pie2 oscfie c1ie c2ie eeie bclie hlvdie tmr3ie ccp2ie 127 pir2 oscfif c1if c2if eeif bclif hlvdif tmr3if ccp2if 124 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used by clock sources. table 3-5: configuration registers associated with clock sources name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page config1h ieso fcmen pclken ?fosc<3:0> 388 config2l ? lpbor ? borv<1:0> boren<1:0> pwrten 389 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used for clock sources. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 49 pic18(l)f2x/45k50 3.14 oscillator settings for usb when the pic18(l)f2x/45k50 family devices are used for usb connectivity, a 6 mhz or 48 mhz clock must be provided to the usb module for operation in either low-speed or full-speed modes, respectively. this may require some forethought in selecting an oscillator frequency and programming the device. the full range of possible oscillator configurations compatible with usb operation is shown in table 3-7 . 3.14.1 low-speed operation the usb clock for low-speed mode is derived from the primary oscillator or from the pll. in order to operate the usb module in low-speed mode, a 6 mhz clock must be provided to the usb module. see ta bl e 3 - 6 and tab l e 3 - 7 for possible combinations which can be used for low-speed usb operation. table 3-6: clock fo r low-speed usb system clock cpudiv<1:0> microcontroller clock ls48mhz usb clock 48 11 48 mhz 1 48/8 = 6 mhz 48 10 48/2 = 24 mhz 1 48/8 = 6 mhz 48 01 48/3 = 16 mhz 1 48/8 = 6 mhz 48 00 48/6 = 8 mhz 1 48/8 = 6 mhz 24 11 24 mhz 0 24/4 = 6 mhz 24 10 24/2 = 12 mhz 0 24/4 = 6 mhz 24 01 24/3 = 8 mhz 0 24/4 = 6 mhz 24 00 24/6 = 4 mhz 0 24/4 = 6 mhz table 3-7: oscillator configurat ion options for usb operation input oscillator frequency clock mode (fosc<3:0>) mcu clock division (cpudiv<1:0>) microcontroller clock frequency 48 mhz ec none ( 11 ) 48 mhz ? 2 ( 10 )24mhz ? 3 ( 01 )16mhz ? 6 ( 00 )8mhz 16 mhz ec, hs or intosc with 3xpll none ( 11 )48mhz ? 2 ( 10 )24mhz ? 3 ( 01 )16mhz ? 6 ( 00 )8mhz 12 mhz ec or hs with 4xpll none ( 11 )48mhz ? 2 ( 10 )24mhz ? 3 ( 01 )16mhz ? 6 ( 00 )8mhz 24 mhz ec or hs (1) none ( 11 )24mhz ? 2 ( 10 )12mhz ? 3 ( 01 )8mhz ? 6 ( 00 )4mhz note 1: the 24 mhz mode (without pll) is only compatible with low-speed usb. full-speed usb requires a 48 mhz system clock. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 50 ? 2012 microchip technology inc. 3.15 active clock tuning (act) module the active clock tuning (act) module continuously adjusts the 16 mhz internal oscillator, using an available external reference, to achieve 0.20% accuracy. this eliminates the need for a high-speed, high-accuracy external crystal when the system has an available lower speed, lower power, high-accuracy clock source available. systems implementing a real-time clock calendar (rtcc) or a full-speed usb application can take full advantage of the act module. 3.16 active clock tuning operation the act module defaults to the disabled state after any reset. when the act module is disabled, the user can write to the tun<6:0> bits in the osctune register to manually adjust the 16 mhz internal oscillator. the module is enabled by setting the acten bit of the actcon register. when enabled, the act module takes control of the osctune register. the act module uses the selected act reference clock to tune the 16 mhz internal oscillator to an accuracy of 16 mhz 0.2%. the tuning automatically adjusts the osctune register every reference clock cycle. 3.17 active clock tuning source selection the act reference clock is selected with the actsrc bit of the actcon register. the reference clock sources are provided by the: ? usb module in full-speed operation (act_clk) ? secondary clock at 32.768 khz (sosc_clk) 3.18 act lock status the actlock bit will be set to ? 1 ?, when the 16 mhz internal oscillator is successfully tuned. the bit will be cleared by the following conditions: ? out of lock condition ? device reset ? module is disabled 3.19 act out-of-range status if the act module requires an osctune value outside the range to achieve 0.20% accuracy, then the act out-of-range (actors) status bit will be set to ? 1 ?. an out-of-range status can occur: ? when the 16 mhz internal oscillator is tuned to its lowest frequency and the next act_clk event requests a lower frequency. ? when the 16 mhz internal oscillator is tuned to its highest frequency and the next act_clk event requests a higher frequency. when the act out-of-range event occurs, the 16 mhz internal oscillator will continue to use the last written osctune value. when the osctune value moves back within the tunable range and actlock is established, the actors bit is cleared to ? 0 ?. figure 3-11: active clo ck tuning block diagram note 1: when the act module is enabled, the osctune register is only updated by the module. writes to the osctune register by the user are inhibited, but reading the register is permitted. 2: after disabling the act module, the user should wait three instructions before writing to the osctune register. actsrc fsusb_clk sosc_clk acten active clock tuning module act_clk enable acten write osctune acten actud 16 mhz internal osc 1 0 osctune<6:0> 7 7 act data sfr data www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 51 pic18(l)f2x/45k50 3.20 active clock tuning update disable when the act module is enabled, the osctune register is continuously updated every act_clk period. setting the act update disable bit can be used to suspend updates to the osctune register, without disabling the module. if the 16 mhz internal oscillator drifts out of the accuracy range, the act status bits will change and an interrupt can be generated to notify the application. clearing the actud bit will engage the act updates to osctune and an interrupt can be generated to notify the application. 3.21 interrupts the act module will set the act module interrupt flag, (actif) when either of the act module status bits (actlock or actors) change state, regardless if the interrupt is enabled, (actie = 1 ). the actif and actie bits are in the pir1 and pie1 registers, respec- tively. when actie = 1 , an interrupt will be generated whenever the act module status bits change. the actif bit must be cleared in software, regardless of the interrupt enable setting. 3.22 operation during sleep this act module does not run during sleep and will not generate interrupts during sleep. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 52 ? 2012 microchip technology inc. 3.23 register definitions: active clock tuning control register 3-4: actcon: active clock tuning ( act) control register r/w-0/0 r/w-0/0 u-0 r/w-0/0 r-0/0 u-0 r-0/0 u-0 acten actud ?actsrc (1) actlock ?actors ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 acten: active clock tuning selection bit 1 = act module is enabled, updates to osctune are exclusive to the act module. 0 = act module is disabled bit 6 actud: active clock tuning update disable bit 1 = updates to the osctune register from act module are disabled. 0 = updates to the osctune register from act module are enabled. bit 5 unimplemented: read as ? 0 ? bit 4 actsrc: active clock tuning source selection bit 1 = the hfintosc oscillator is tuned to approximately match the usb host clock tolerance 0 = the hfintosc oscillator is tuned to approximately match the 32.768 khz sosc tolerance bit 3 actlock: active clock tuning lock status bit 1 = locked; 16 mhz internal oscillator is within 0.20%.locked 0 = not locked; 16 mhz internal oscillator tuning has not stabilized within 0.20% bit 2 unimplemented: read as ? 0 ? bit 1 actors: active clock tuning out-of-range status bit 1 = out-of-range; oscillator frequency is outside of the osctune range 0 = in-range; oscillator frequency is within the osctune range bit 0 unimplemented: read as ? 0 ? note 1: the actsrc bit should only be changed when acten = 0 . www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 53 pic18(l)f2x/45k50 table 3-8: summary of registers asso ciated with act sources table 3-9: summary of configurat ion word with act sources name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page actcon acten actud ? actsrc actlock ?actors ? 52 osccon idlen ircf<2:0> osts hfiofs scs<1:0> 35 osctune spllmult tun<6:0> 40 osccon2 pllrdy soscrun intsrc pllen soscgo prisd hfiofr lfiofs 36 pir1 actif adif rcif txif sspif ccp1if tmr2if tmr1if 123 ipr1 actip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 129 pie1 actie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 126 t1con tmr1cs<1:0> t1ckps<1:0> soscen t1sync rd16 tmr1on 174 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by clock sources. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page config1h ieso fcmen pclken ? fosc<3:0> 388 www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 54 ? 2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 55 pic18(l)f2x/45k50 4.0 power-managed modes pic18(l)f2x/45k50 devices offer a total of seven operating modes for more efficient power management. these modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices). there are three categories of power-managed modes: ? run modes ? idle modes ? sleep mode these categories define which portions of the device are clocked and sometimes, what speed. the run and idle modes may use any of the three available clock sources (primary, secondary or internal oscillator block). the sleep mode does not use a clock source. the power-managed modes include several power- saving features offered on previous pic ? microcontroller devices. one of the clock switching features allows the controller to use the secondary oscillator (sosc) in place of the primary oscillator. also included is the sleep mode, offered by all pic ? microcontroller devices, where all device clocks are stopped. 4.1 selecting power-managed modes selecting a power-managed mode requires two decisions: ? whether or not the cpu is to be clocked ? the selection of a clock source the idlen bit (osccon<7>) controls cpu clocking, while the scs<1:0> bits (osccon<1:0>) select the clock source. the individual modes, bit settings, clock sources and affected modules are summarized in table 4-1 . 4.1.1 clock sources the scs<1:0> bits allow the selection of one of three clock sources for power-managed modes. they are: ? the primary clock, as defined by the fosc<3:0> configuration bits ? the secondary clock (the sosc oscillator) ? the internal oscillator block 4.1.2 entering power-managed modes switching from one power-managed mode to another begins by loading the osccon register. the scs<1:0> bits select the clock source and determine which run or idle mode is to be used. changing these bits causes an immediate switch to the new clock source, assuming that it is running. the switch may also be subject to clock transition delays. refer to section 3.11 ?clock switching? for more information. entry to the power-managed idle or sleep modes is triggered by the execution of a sleep instruction. the actual mode that results depends on the status of the idlen bit. depending on the current mode and the mode being switched to, a change to a power-managed mode does not always require setting all of these bits. many transitions may be done by changing the oscillator select bits, or changing the idlen bit, prior to issuing a sleep instruction. if the idlen bit is already configured correctly, it may only be necessary to perform a sleep instruction to switch to the desired mode. table 4-1: power- managed modes mode osccon bits module clocking available clock and oscillator source idlen (1) scs<1:0> cpu peripherals sleep 0 n/a off off none ? all clocks are disabled pri_run n/a 00 clocked clocked primary ? lp, xt, hs, rc, ec and internal oscillator block (2) . this is the normal full-power execution mode. sec_run n/a 01 clocked clocked secondary ? sosc oscillator rc_run n/a 1x clocked clocked internal oscillator block (2) pri_idle 100 off clocked primary ? lp, xt, hs, hspll, rc, ec sec_idle 101 off clocked secondary ? sosc oscillator rc_idle 11x off clocked internal oscillator block (2) note 1: idlen reflects its value when the sleep instruction is executed. 2: includes hfintosc and hfintosc postsc aler, as well as the intrc source. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 56 ? 2012 microchip technology inc. 4.1.3 multiple functions of the sleep command the power-managed mode that is invoked with the sleep instruction is determined by the value of the idlen bit at the time the instruction is executed. if idlen = 0 , when sleep is executed, the device enters the sleep mode and all clocks stop and minimum power is consumed. if idlen = 1 , when sleep is executed, the device enters the idle mode and the system clock continues to supply a clock to the peripherals but is disconnected from the cpu. 4.2 run modes in the run modes, clocks to both the core and peripherals are active. the difference between these modes is the clock source. 4.2.1 pri_run mode the pri_run mode is the normal, full-power execution mode of the microcontroller. this is also the default mode upon a device reset, unless two-speed start-up is enabled (see section 3.12 ?two-speed clock start-up mode? for details). in this mode, the device is operated off the oscillator defined by the fosc<3:0> bits of the config1h configuration register. 4.2.2 sec_run mode in sec_run mode, the cpu and peripherals are clocked from the secondary external oscillator. this gives users the option of lower power consumption while still using a high accuracy clock source. sec_run mode is entered by setting the scs<1:0> bits to ? 01 ?. when sec_run mode is active, all of the following are true: ? the device clock source is switched to the sosc oscillator (see figure 4-1 ) ? the primary oscillator is shut down ? the soscrun bit (osccon2<6>) is set ? the osts bit (osccon<3>) is cleared on transitions from sec_run mode to pri_run mode, the peripherals and cpu continue to be clocked from the sosc oscillator, while the primary clock is started. when the primary clock becomes ready, a clock switch back to the primary clock occurs (see figure 4-2 ). when the clock switch is complete, the soscrun bit is cleared, the osts bit is set and the primary clock is providing the clock. the idlen and scs bits are not affected by the wake-up and the sosc oscillator continues to run. 4.2.3 rc_run mode in rc_run mode, the cpu and peripherals are clocked from the internal oscillator block using the intosc multiplexer. in this mode, the primary clock is shut down. when using the intrc source, this mode provides the best power conservation of all the run modes, while still executing code. it works well for user applications which are not highly timing-sensitive or do not require high-speed clocks at all times. if the primary clock source is the internal oscillator block ? either intrc or hfintosc ? there are no distinguishable differences between the pri_run and rc_run modes during execution. entering or exiting rc_run mode, however, causes a clock switch delay. therefore, if the primary clock source is the internal oscillator block, using rc_run mode is not recommended. this mode is entered by setting the scs1 bit to ? 1 ?. to maintain software compatibility with future devices, it is recommended that the scs0 bit also be cleared, even though the bit is ignored. when the clock source is switched to the intosc multiplexer (see figure 4-1 ), the primary oscillator is shut down and the osts bit is cleared. the ircf<2:0> bits (osccon<6:4>) may be modified at any time to immediately change the clock speed. when the ircf bits and the intsrc bit are all clear, the intosc output (hfintosc) is not enabled and the hfiofs bit will remain clear. there will be no indi- cation of the current clock source. the intrc source is providing the device clocks. if the ircf bits are changed from all clear (thus, enabling the intosc output) or if intsrc is set, then the hfiofs bit is set after the intosc output becomes stable. for details, see table 4-2 . clocks to the device continue while the intosc source stabilizes after an interval of t iobst . if the ircf bits were previously at a non-zero value, or if intsrc was set before setting scs1 and the intosc source was already stable, then the hfiofs bit will remain set. note: the secondary external oscillator should already be running prior to entering sec_run mode. if the soscgo bit or any of the soscen bits are not set when the scs<1:0> bits are set to ? 01 ?, entry to sec_run mode will not occur until the soscgo bit is set and secondary external oscillator is ready. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 57 pic18(l)f2x/45k50 on transitions from rc_run mode to pri_run mode, the device continues to be clocked from the intosc multiplexer while the primary clock is started. when the primary clock becomes ready, a clock switch to the pri- mary clock occurs (see figure 4-3 ). when the clock switch is complete, the hfiofs bit is cleared, the osts bit is set and the primary clock is providing the device clock. the idlen and scs bits are not affected by the switch. the intrc source will continue to run if either the wdt or the fail-safe clock monitor is enabled. figure 4-1: transition timing for entry to sec_run mode figure 4-2: transition timing from sec_run mode to pri_run mode (hspll) q4 q3 q2 osc1 peripheral program q1 sosci q1 counter clock cpu clock pc + 2 pc 123 n-1n clock transition (1) q4 q3 q2 q1 q3 q2 pc + 4 note 1: clock transition typically occurs within 2-4 t osc . q1 q3 q4 osc1 peripheral program pc sosc pll clock q1 pc + 4 q2 output q3 q4 q1 cpu clock pc + 2 clock counter q2 q2 q3 note1: t ost = 1024 t osc ; t pll = 2 ms (approx). these intervals are not shown to scale. 2: clock transition typically occurs within 2-4 t osc . scs<1:0> bits changed t pll (1) 12 n-1n clock osts bit set transition (2) t ost (1) www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 58 ? 2012 microchip technology inc. figure 4-3: transition timing from rc_run mode to pri_run mode table 4-2: internal oscillator frequency stability bits ircf<2:0> intsrc selected oscillator selected oscillator stable when: 000 0 intrc lfiofs = 1 000 1 hfintosc hfiofs = 1 001 - 111 x hfintosc hfiofs = 1 q1 q3 q4 osc1 peripheral program pc intosc pll clock q1 pc + 4 q2 output q3 q4 q1 cpu clock pc + 2 clock counter q2 q2 q3 note1: t ost = 1024 t osc ; t pll = 2 ms (approx). these intervals are not shown to scale. 2: clock transition typically occurs within 2-4 t osc . scs<1:0> bits changed t pll (1) 12 n-1n clock osts bit set transition (2) multiplexer t ost (1) www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 59 pic18(l)f2x/45k50 4.3 sleep mode the power-managed sleep mode in the pic18(l)f2x/ 45k50 devices is identical to the legacy sleep mode offered in all other pic ? microcontroller devices. it is entered by clearing the idlen bit of the osccon register and executing the sleep instruction. this shuts down the selected oscillator ( figure 4-4 ) and all clock source status bits are cleared. entering the sleep mode from either run or idle mode does not require a clock switch. this is because no clocks are needed once the controller has entered sleep. if the wdt is selected, the intrc source will continue to operate. if the sosc oscillator is enabled, it will also continue to run. when a wake event occurs in sleep mode (by interrupt, reset or wdt time-out), the device will not be clocked until the clock source selected by the scs<1:0> bits becomes ready (see figure 4-5 ), or it will be clocked from the internal oscillator block if either the two-speed start-up or the fail-safe clock monitor are enabled (see section 26.0 ?special features of the cpu? ). in either case, the osts bit is set when the primary clock is providing the device clocks. the idlen and scs bits are not affected by the wake-up. 4.3.1 voltage regulator power mode on f devices, an internal voltage regulator provides power to the internal core logic of the chip. during sleep mode, the internal voltage regulator can be put into a lower-power mode, in exchange for longer wake-up time. similarly, the internal band gap voltage reference may be turned off during sleep for lower- power consumption. see register 4-1 . on lf devices, the internal core logic operates from v dd and the internal voltage regulator is bypassed. the vregcon register is, thus, not implemented on lf devices. register 4-1: vregcon ? voltage regulator power control register (1) u-0 u-0 u-0 u-0 u-0 r-0 r/w-0/0 r/w-0/0 ? ? ? ? ? ? vregpm<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit x = bit is unknown -n/n = value at por and bor/value at all other resets ? 0 ? = bit is cleared ? 1 ? = bit is set u = unimplemented bit, read as ?0? bit 7-2 unimplemented: read as ? 0 ? bit 1-0 vregpm<1:0>: voltage regulator power mode bits 11 = band gap not forced in sleep; ldo off in sleep; ulp regulator active 10 = band gap forced in sleep; ldo off in sleep; ulp regulator active 01 = ldo in low-power mode in sleep, if no peripherals require high-power mode. 00 = ldo in high-power mode ? always note 1: reset state depends on state of the ieso configuration bit. 2: default output frequency of hfintosc on reset. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 60 ? 2012 microchip technology inc. 4.4 idle modes the idle modes allow the controller?s cpu to be selectively shut down while the peripherals continue to operate. selecting a particular idle mode allows users to further manage power consumption. if the idlen bit is set to a ? 1 ? when a sleep instruction is executed, the peripherals will be clocked from the clock source selected by the scs<1:0> bits; however, the cpu will not be clocked. the clock source status bits are not affected. setting idlen and executing a sleep instruc- tion provides a quick method of switching from a given run mode to its corresponding idle mode. if the wdt is selected, the intrc source will continue to operate. if the sosc oscillator is enabled, it will also continue to run. since the cpu is not executing instructions, the only exits from any of the idle modes are by interrupt, wdt time-out, or a reset. when a wake event occurs, cpu execution is delayed by an interval of t csd while it becomes ready to execute code. when the cpu begins executing code, it resumes with the same clock source for the current idle mode. for example, when waking from rc_idle mode, the internal oscillator block will clock the cpu and peripherals (in other words, rc_run mode). the idlen and scs bits are not affected by the wake-up. while in any idle mode or the sleep mode, a wdt time-out will result in a wdt wake-up to the run mode currently specified by the scs<1:0> bits. figure 4-4: transition timi ng for entry to sleep mode figure 4-5: transition timing for wake from sleep (hspll) 4.4.1 pri_idle mode this mode is unique among the three low-power idle modes, in that it does not disable the primary device clock. for timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to ?warm-up? or transition from another oscillator. pri_idle mode is entered from pri_run mode by setting the idlen bit and executing a sleep instruc- tion. if the device is in another run mode, set idlen first, then clear the scs bits and execute sleep . although the cpu is disabled, the peripherals continue to be clocked from the primary clock source specified by the fosc<3:0> configuration bits. the osts bit remains set (see figure 4-6 ). when a wake event occurs, the cpu is clocked from the primary clock source. a delay of interval t csd is required between the wake event and when code execution starts. this is required to allow the cpu to become ready to execute instructions. after the wake- up, the osts bit remains set. the idlen and scs bits are not affected by the wake-up (see figure 4-7 ). q4 q3 q2 osc1 peripheral sleep program q1 q1 counter clock cpu clock pc + 2 pc q3 q4 q1 q2 osc1 peripheral program pc pll clock q3 q4 output cpu clock q1 q2 q3 q4 q1 q2 clock counter pc + 6 pc + 4 q1 q2 q3 q4 wake event note1: t ost = 1024 t osc ; t pll = 2 ms (approx). these intervals are not shown to scale. t ost (1) t pll (1) osts bit set pc + 2 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 61 pic18(l)f2x/45k50 4.4.2 sec_idle mode in sec_idle mode, the cpu is disabled but the peripherals continue to be clocked from the sosc oscillator. this mode is entered from sec_run by set- ting the idlen bit and executing a sleep instruction. if the device is in another run mode, set the idlen bit first, then set the scs<1:0> bits to ? 01 ? and execute sleep . when the clock source is switched to the sosc oscillator, the primary oscillator is shut down, the osts bit is cleared and the soscrun bit is set. when a wake event occurs, the peripherals continue to be clocked from the sosc oscillator. after an interval of t csd following the wake event, the cpu begins exe- cuting code being clocked by the sosc oscillator. the idlen and scs bits are not affected by the wake-up; the sosc oscillator continues to run (see figure 4-7 ). figure 4-6: transition timing for entry to idle mode figure 4-7: transition timing for wake from idle to run mode note: the sosc oscillator should already be running prior to entering sec_idle mode. at least one of the secondary oscil- lator enable bits (soscen, t1con<3> or t3con<3>) must be set when the sleep instruction is executed. otherwise, the main system clock will continue to operate in the previously selected mode and the corresponding idle mode will be entered (i.e., pri_idle or rc_idle). q1 peripheral program pc pc + 2 osc1 q3 q4 q1 cpu clock clock counter q2 osc1 peripheral program pc cpu clock q1 q3 q4 clock counter q2 wake event t csd www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 62 ? 2012 microchip technology inc. 4.4.3 rc_idle mode in rc_idle mode, the cpu is disabled but the periph- erals continue to be clocked from the internal oscillator block from the hfintosc multiplexer output. this mode allows for controllable power conservation during idle periods. from rc_run, this mode is entered by setting the idlen bit and executing a sleep instruction. if the device is in another run mode, first set idlen, then set the scs1 bit and execute sleep . it is recommended that scs0 also be cleared, although its value is ignored, to maintain software compatibility with future devices. the hfintosc multiplexer may be used to select a higher clock frequency by modifying the ircf bits before executing the sleep instruction. when the clock source is switched to the hfintosc multiplexer, the primary oscillator is shut down and the osts bit is cleared. if the ircf bits are set to any non-zero value, or the intsrc bits are set, the hfintosc output is enabled. the hfiofs bit becomes set after the hfintosc output stabilizes after an interval of t iobst . for information on the hfiofs bit, see table 4-2 . clocks to the peripherals continue while the hfintosc source stabilizes. the hfiofs bit will remain set if the ircf bits were previously set at a non- zero value or if intsrc was set before the sleep instruction was executed and the hfintosc source was already stable. if the ircf bits and intsrc are all clear, the hfintosc output will not be enabled, the hfiofs bit will remain clear and there will be no indication of the current clock source. when a wake event occurs, the peripherals continue to be clocked from the hfintosc multiplexer output. after a delay of t csd following the wake event, the cpu begins executing code being clocked by the hfintosc multiplexer. the idlen and scs bits are not affected by the wake-up. the intrc source will continue to run if either the wdt or the fail-safe clock monitor is enabled. 4.5 exiting idle and sleep modes an exit from sleep mode or any of the idle modes is triggered by any one of the following: ? an interrupt ?a reset ? a watchdog time-out this section discusses the triggers that cause exits from power-managed modes. the clocking subsystem actions are discussed in each of the power-managed modes (see section 4.2 ?run modes? , section 4.3 ?sleep mode? and section 4.4 ?idle modes? ). 4.5.1 exit by interrupt any of the available interrupt sources can cause the device to exit from an idle mode or the sleep mode to a run mode. to enable this functionality, an interrupt source must be enabled by setting its enable bit in one of the intcon or pie registers. the exit sequence is initiated when the corresponding interrupt flag bit is set. the instruction immediately following the sleep instruction is executed on all exits by interrupt from idle or sleep modes. code execution then branches to the interrupt vector if the gie/gieh bit of the intcon register is set, otherwise code execution continues without branching (see section 10.0 ?interrupts? ). a fixed delay of interval t csd following the wake event is required when leaving sleep and idle modes. this delay is required for the cpu to prepare for execution. instruction execution resumes on the first clock cycle following this delay. 4.5.2 exit by wdt time-out a wdt time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs. if the device is not executing code (all idle modes and sleep mode), the time-out will result in an exit from the power-managed mode (see section 4.2 ?run modes? and section 4.3 ?sleep mode? ). if the device is executing code (all run modes), the time-out will result in a wdt reset (see section 26.3 ?watchdog timer (wdt)? ). the wdt timer and postscaler are cleared by any one of the following: ? executing a sleep instruction ? executing a clrwdt instruction ? the loss of the currently selected clock source when the fail-safe clock monitor is enabled ? modifying the ircf bits in the osccon register when the internal oscillator block is the device clock source www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 63 pic18(l)f2x/45k50 4.5.3 exit by reset exiting sleep and idle modes by reset causes code execution to restart at address 0. see section 5.0 ?reset? for more details. the exit delay time from reset to the start of code execution depends on both the clock sources before and after the wake-up and the type of oscillator. 4.5.4 exit without an oscillator start-up delay certain exits from power-managed modes do not invoke the ost at all. there are two cases: ? pri_idle mode, where the primary clock source is not stopped and ? the primary clock source is not any of the lp, xt, hs or hspll modes. in these instances, the primary clock source either does not require an oscillator start-up delay since it is already running (pri_idle), or normally does not require an oscillator start-up delay (rc, ec, intosc, and intoscio modes). however, a fixed delay of interval t csd following the wake event is still required when leaving sleep and idle modes to allow the cpu to prepare for execution. instruction execution resumes on the first clock cycle following this delay. 4.6 selective peripheral module control idle mode allows users to substantially reduce power consumption by stopping the cpu clock. even so, peripheral modules still remain clocked, and thus, con- sume power. there may be cases where the applica- tion needs what idle mode does not provide: the allocation of power resources to the cpu processing with minimal power consumption from the peripherals. pic18(l)f2x/45k50 family devices address this requirement by allowing peripheral modules to be selectively disabled, reducing or eliminating their power consumption. this can be done with control bits in the peripheral module disable (pmd) registers. these bits generically named xxxmd are located in control registers pmd0 or pmd1. setting the pmd bit for a module disables all clock sources to that module, reducing its power consumption to an absolute minimum. in this state, power to the control and status registers associated with the peripheral is removed. writes to these registers have no effect and read values are invalid. clearing a set pmd bit restores power to the associated control and status registers, thereby setting those registers to their default values. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 64 ? 2012 microchip technology inc. 4.7 register definitions: peripheral module disable register 4-2: pmd0: peripheral module disable register 0 u-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 ? uartmd usbmd actmd ? tmr3md tmr2md tmr1md bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ? 0 ?. bit 6 uartmd: uart peripheral module disable control bit 1 = module is disabled, clock source is disconnected, module does not draw digital power 0 = module is enabled, clock source is connected, module draws digital power bit 5 usbmd: usb peripheral module disable control bit 1 = module is disabled, clock source is disconnected, module does not draw digital power 0 = module is enabled, clock source is connected, module draws digital power bit 4 actmd: active clock tuning peripheral module disable control bit 1 = module is disabled and does not draw any digital power 0 = module is enabled and available for use; will draw digital power bit 3 unimplemented: read as ? 0 ?. bit 2 tmr3md: timer3 peripheral module disable control bit 1 = module is disabled, clock source is disconnected, module does not draw digital power 0 = module is enabled, clock source is connected, module draws digital power bit 1 tmr2md: timer2 peripheral module disable control bit 1 = module is disabled, clock source is disconnected, module does not draw digital power 0 = module is enabled, clock source is connected, module draws digital power bit 0 tmr1md: timer1 peripheral module disable control bit 1 = module is disabled, clock source is disconnected, module does not draw digital power 0 = module is enabled, clock source is connected, module draws digital power www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 65 pic18(l)f2x/45k50 register 4-3: pmd1: peripheral module disable register 1 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? msspmd ctmumd cmp2md cmp1md adcmd ccp2md ccp1md bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6 msspmd: mssp peripheral module disable control bit 1 = module is disabled, clock source is disconnected, module does not draw digital power 0 = module is enabled, clock source is connected, module draws digital power bit 5 ctmumd: ctmu peripheral module disable control bit 1 = module is disabled, clock source is disconnected, module does not draw digital power 0 = module is enabled, clock source is connected, module draws digital power bit 4 cmp2md: comparator 2 peripheral module disable control bit 1 = module is disabled, clock source is disconnected, module does not draw digital power 0 = module is enabled, clock source is connected, module draws digital power bit 3 cmp1md: comparator 1 peripheral module disable control bit 1 = module is disabled, clock source is disconnected, module does not draw digital power 0 = module is enabled, clock source is connected, module draws digital power bit 2 adcmd: analog-to-digital converter peripheral module disable control bit 1 = module is disabled, clock source is disconnected, module does not draw digital power 0 = module is enabled, clock source is connected, module draws digital power bit 1 ccp2md: ccp2 peripheral module disable control bit 1 = module is disabled, clock source is disconnected, module does not draw digital power 0 = module is enabled, clock source is connected, module draws digital power bit 0 ccp1md: ccp1 peripheral module disable control bit 1 = module is disabled, clock source is disconnected, module does not draw digital power 0 = module is enabled, clock source is connected, module draws digital power www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 66 ? 2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 67 pic18(l)f2x/45k50 5.0 reset the pic18(l)f2x/45k50 devices differentiate between various kinds of reset: a) power-on reset (por) b) mclr reset during normal operation c) mclr reset during power-managed modes d) watchdog timer (wdt) reset (during execution) e) programmable brown-out reset (bor) f) reset instruction g) stack full reset h) stack underflow reset this section discusses resets generated by mclr , por and bor and covers the operation of the various start-up timers. stack reset events are covered in section 6.2.1 ?stack full and underflow resets? . wdt resets are covered in section 26.3 ?watchdog timer (wdt)? . a simplified block diagram of the on-chip reset circuit is shown in figure 5-1 . 5.1 rcon register device reset events are tracked through the rcon register ( register 5-1 ). the lower five bits of the register indicate that a specific reset event has occurred. in most cases, these bits can only be cleared by the event and must be set by the application after the event. the state of these flag bits, taken together, can be read to indicate the type of reset that just occurred. this is described in more detail in section 5.8 ?reset state of registers? . the rcon register also has control bits for setting interrupt priority (ipen) and software control of the bor (sboren). interrupt priority is discussed in section 10.0 ?interrupts? . bor is covered in section 5.5 ?brown-out reset (bor)? . figure 5-1: simplified block di agram of on-chip reset circuit external reset mclr v dd osc1 wdt time-out v dd detect ost/pwrt intrc por ost (2) 10-bit ripple counter pwrt (2) 11-bit ripple counter enable ost (1) enable pwrt note 1: see table 5-2 for time-out situations. 2: pwrt and ost counters are reset by por and bor. see sections 5.4 and 5.5 . brown-out reset boren reset instruction stack pointer stack full/underflow reset sleep idle 1024 cycles 65.5 ms 32 ? s mclre s r q chip_reset www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 68 ? 2012 microchip technology inc. 5.2 register definitions: reset control register 5-1: rcon: re set control register r/w-0/0 r/w-q/u u-0 r/w-1/q r-1/q r-1/q r/w-q/u r/w-0/q ipen sboren (1) ?ri to pd por (2) bor bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? ?1? = bit is set ?0? = bit is cleared -n/n = value at por and bor/value at all other resets x = bit is unknown u = unchanged q = depends on condition bit 7 ipen: interrupt priority enable bit 1 = enable priority levels on interrupts 0 = disable priority levels on interrupts (pic16cxxx compatibility mode) bit 6 sboren: bor software enable bit (1) if boren<1:0> = 01 : 1 = bor is enabled 0 = bor is disabled if boren<1:0> = 00 , 10 or 11 : bit is disabled and read as ? 0 ?. bit 5 unimplemented: read as ? 0 ? bit 4 ri : reset instruction flag bit 1 = the reset instruction was not executed (set by firmware or power-on reset) 0 = the reset instruction was executed causing a device reset (must be set in firmware after a code-executed reset occurs) bit 3 to : watchdog time-out flag bit 1 = set by power-up, clrwdt instruction or sleep instruction 0 = a wdt time-out occurred bit 2 pd : power-down detection flag bit 1 = set by power-up or by the clrwdt instruction 0 = set by execution of the sleep instruction bit 1 por : power-on reset status bit (2) 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit (3) 1 = a brown-out reset has not occurred (set by firmware only) 0 = a brown-out reset occurred (must be set by firmware after a por or brown-out reset occurs) note 1: when config2l[2:1] = 01 , then the sboren reset state is ? 1 ?; otherwise, it is ? 0 ?. 2: the actual reset value of por is determined by the type of device reset. see the notes following this register and section 5.8 ?reset state of registers? for additional information. 3: see table 5-1 . note 1: brown-out reset is indicated when bor is ? 0 ? and por is ? 1 ? (assuming that both por and bor were set to ? 1 ? by firmware immediately after por). 2: it is recommended that the por bit be set after a power-on reset has been detected so that subsequent power-on resets may be detected. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 69 pic18(l)f2x/45k50 5.3 master clear (mclr ) the mclr pin provides a method for triggering an external reset of the device. a reset is generated by holding the pin low. these devices have a noise filter in the mclr reset path which detects and ignores small pulses. an internal weak pull-up is enabled when the pin is configured as the mclr input. the mclr pin is not driven low by any internal resets, including the wdt. in pic18(l)f2x/45k50 devices, the mclr input can be disabled with the mclre configuration bit. when mclr is disabled, the pin becomes a digital input. see section 11.6 ?porte registers? for more information. 5.4 power-on reset (por) a power-on reset pulse is generated on-chip whenever v dd rises above a certain threshold. this allows the device to start in the initialized state when v dd is adequate for operation. to take advantage of the por circuitry either leave the pin floating, or tie the mclr pin through a resistor to v dd . this will eliminate external rc components usually needed to create a power-on reset delay. a minimum rise rate for v dd is specified. for a slow rise time, see figure 5-2 . when the device starts normal operation (i.e., exits the reset condition), device operating parameters (volt- age, frequency, temperature, etc.) must be met to ensure proper operation. if these conditions are not met, the device must be held in reset until the operat- ing conditions are met. por events are captured by the por bit of the rcon register. the state of the bit is set to ? 0 ? whenever a por occurs; it does not change for any other reset event. por is not reset to ? 1 ? by any hardware event. to capture multiple events, the user must manually set the bit to ? 1 ? by software following any por. figure 5-2: external power-on reset circuit (for slow v dd power-up) note 1: external power-on reset circuit is required only if the v dd power-up slope is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: 15 k ? < r < 40 k ? is recommended to make sure that the voltage drop across r does not violate the device?s electrical specification. 3: r1 ? 1 k ? will limit any current flowing into mclr from external capacitor c, in the event of mclr /v pp pin breakdown, due to electrostatic discharge (esd) or electrical overstress (eos). c r1 r d v dd mclr v dd pic ? mcu www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 70 ? 2012 microchip technology inc. 5.5 brown-out reset (bor) pic18(l)f2x/45k50 devices implement a bor circuit that provides the user with a number of configuration and power-saving options. the bor is controlled by the borv<1:0> and boren<1:0> bits of the config2l configuration register. there are a total of four bor configurations which are summarized in ta b l e 5 - 1 . the bor threshold is set by the borv<1:0> bits. if bor is enabled (any values of boren<1:0>, except ? 00 ?), any drop of v dd below v bor for greater than t bor will reset the device. a reset may or may not occur if v dd falls below v bor for less than t bor . the chip will remain in brown-out reset until v dd rises above v bor . if the power-up timer is enabled, it will be invoked after v dd rises above v bor ; it then will keep the chip in reset for an additional time delay, t pwrt . if v dd drops below v bor while the power-up timer is running, the chip will go back into a brown-out reset and the power-up timer will be initialized. once v dd rises above v bor , the power-up timer will execute the additional time delay. bor and the power-on timer (pwrt) are independently configured. enabling bor reset does not automatically enable the pwrt. the bor circuit has an output that feeds into the por circuit and rearms the por within the operating range of the bor. this early rearming of the por ensures that the device will remain in reset in the event that v dd falls below the operating range of the bor circuitry. 5.5.1 detecting bor when bor is enabled, the bor bit always resets to ? 0 ? on any bor or por event. this makes it difficult to determine if a bor event has occurred just by reading the state of bor alone. a more reliable method is to simultaneously check the state of both por and bor. this assumes that the por and bor bits are reset to ? 1 ? by software immediately after any por event. if bor is ? 0 ? while por is ? 1 ?, it can be reliably assumed that a bor event has occurred. 5.5.2 software enabled bor when boren<1:0> = 01 , the bor can be enabled or disabled by the user in software. this is done with the sboren control bit of the rcon register. setting sboren enables the bor to function as previously described. clearing sboren disables the bor entirely. the sboren bit operates only in this mode; otherwise it is read as ? 0 ?. placing the bor under software control gives the user the additional flexibility of tailoring the application to the environment without having to reprogram the device to change bor configuration. it also allows the user to tailor device power consumption in software by eliminating the incremental current that the bor consumes. while the bor current is typically very small, it may have some impact in low-power applications. 5.5.3 disabling bor in sleep mode when boren<1:0> = 10 , the bor remains under hardware control and operates as previously described. whenever the device enters sleep mode, however, the bor is automatically disabled. when the device returns to any other operating mode, bor is automatically re-enabled. this mode allows for applications to recover from brown-out situations, while actively executing code, when the device requires bor protection the most. at the same time, it saves additional power in sleep mode by eliminating the small incremental bor current. 5.5.4 minimum bor enable time enabling the bor also enables the fixed voltage reference (fvr) when no other peripheral requiring the fvr is active. the bor becomes active only after the fvr stabilizes. therefore, to ensure bor protection, the fvr settling time must be considered when enabling the bor in software or when the bor is automatically enabled after waking from sleep. if the bor is disabled, in software or by reentering sleep before the fvr stabilizes, the bor circuit will not sense a bor condition. the fvrst bit of the vrefcon0 register can be used to determine fvr stability. note: even when bor is under software control, the bor reset voltage level is still set by the borv<1:0> configuration bits. it cannot be changed by software. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 71 pic18(l)f2x/45k50 5.6 low-power bor (lpbor ) pic18(l)f2x/45k50 devices implement a low-power brown-out reset circuit (lpbor ). the lpbor is used to monitor the external v dd pin. when low voltage is detected, the device is held in reset. when this occurs, the rcon<0> (bor ) bit is changed to indicate that a bor reset has occurred. this is the same bit in the rcon register that is set for the traditional bor. lpbor provides the user with a lower power bor option. in exchange for the lower power, the lpbor circuit trips at a loose voltage range compared to the traditional bor voltage trip point options. lpbor is enabled by the configuration bit config2l<6> (l pbor ). the threshold of the lpbor is not configurable and its range is specified as parameter d006. 5.7 device reset timers pic18(l)f2x/45k50 devices incorporate three separate on-chip timers that help regulate the power- on reset process. their main function is to ensure that the device clock is stable before code is executed. these timers are: ? power-up timer (pwrt) ? oscillator start-up timer (ost) ? pll lock time-out 5.7.1 power-up timer (pwrt) the power-up timer (pwrt) of pic18(l)f2x/45k50 devices is an 11-bit counter which uses the intrc source as the clock input. this yields an approximate time interval of 2048 x 32 ? s = 65.6 ms. while the pwrt is counting, the device is held in reset. the power-up time delay depends on the intrc clock and will vary from chip-to-chip due to temperature and process variation. the pwrt is enabled by clearing the pwrten configuration bit. 5.7.2 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides a 1024 oscillator cycle (from osc1 input) delay after the pwrt delay is over. this ensures that the crystal oscillator or resonator has started and stabilized. the ost time-out is invoked only for xt, lp and hs modes and only on power-on reset, or on exit from all power-managed modes that stop the external oscillator. 5.7.3 pll lock time-out with the pll enabled, the time-out sequence following a power-on reset is slightly different from other oscillator modes. a separate timer is used to provide a fixed time- out that is sufficient for the pll to lock to the main oscillator frequency. this pll lock time-out (t pll ) is typically 2 ms and follows the oscillator start-up time-out. 5.7.4 time-out sequence on power-up, the time-out sequence is as follows: 1. after the por pulse has cleared, pwrt time-out is invoked (if enabled). 2. then, the ost is activated. the total time-out will vary based on oscillator configuration and the status of the pwrt. figure 5-3 , figure 5-4 , figure 5-5 , figure 5-6 and figure 5-7 all depict time-out sequences on power-up, with the power-up timer enabled and the device operating in hs oscillator mode. figures 5-3 through 5-6 also apply to devices operating in xt or lp modes. for devices in rc mode and with the pwrt disabled, on the other hand, there will be no time-out at all. since the time-outs occur from the por pulse, if mclr is kept low long enough, all time-outs will expire, after which, bringing mclr high will allow program execution to begin immediately ( figure 5-5 ). this is useful for testing purposes or to synchronize more than one pic ? mcu device operating in parallel. table 5-1: bor configurations bor configuration status of sboren (rcon<6>) bor operation boren1 boren0 00 unavailable bor disabled; must be enabled by reprogramming the configuration bits. 01 available bor enabled by software; operation controlled by sboren. 10 unavailable bor enabled by hardware in run and idle modes, disabled during sleep mode. 11 unavailable bor enabled by hardware; must be di sabled by reprogramming the configuration bits. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 72 ? 2012 microchip technology inc. figure 5-3: time-out sequ ence on power-up (mclr tied to v dd , v dd rise < t pwrt ) figure 5-4: time-out sequ ence on power-up (mclr not tied to v dd ): case 1 table 5-2: time-out in various situations oscillator configuration power-up (2) and brown-out exit from power-managed mode pwrten = 0 pwrten = 1 hspll 66 ms (1) + 1024 t osc + 2 ms (2) 1024 t osc + 2 ms (2) 1024 t osc + 2 ms (2) hs, xt, lp 66 ms (1) + 1024 t osc 1024 t osc 1024 t osc ec, ecio 66 ms (1) ?? rc, rcio 66 ms (1) ?? intosc, intoscio 66 ms (1) ?? note 1: 66 ms (65.5 ms) is the nominal power-up timer (pwrt) delay. 2: 2 ms is the nominal time required for the pll to lock. t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 73 pic18(l)f2x/45k50 figure 5-5: time-out sequ ence on power-up (mclr not tied to v dd ): case 2 figure 5-6: slow rise time (mclr tied to v dd , v dd rise > t pwrt ) v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset 0v 5v t pwrt t ost www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 74 ? 2012 microchip technology inc. figure 5-7: time-out sequence on por w/pll enabled (mclr tied to v dd ) t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset pll time-out t pll note: t ost = 1024 clock cycles. t pll ? 2 ms max. first three stages of the pwrt timer. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 75 pic18(l)f2x/45k50 5.8 reset state of registers some registers are unaffected by a reset. their status is unknown on por and unchanged by all other resets. all other registers are forced to a ?reset state? depending on the type of reset that occurred. most registers are not affected by a wdt wake-up, since this is viewed as the resumption of normal operation. status bits from the rcon register, ri , to , pd , por and bor , are set or cleared differently in different reset situations, as indicated in table 5-3 . these bits are used by software to determine the nature of the reset. table 6-2 describes the reset states for all of the special function registers. the table identifies differences between power-on reset (por)/brown- out reset (bor) and all other resets, (i.e., master clear, wdt resets, stkful, stkunf, etc.). additionally, the table identifies register bits that are changed when the device receives a wake-up from wdt or other interrupts. table 5-3: status bits, their signifi cance and the initialization condition for rcon register condition program counter rcon register stkptr register sboren ri to pd por bor stkful stkunf power-on reset 0000h 1 11100 0 0 reset instruction 0000h u (2) 0uuuu u u brown-out reset 0000h u (2) 111u0 u u mclr during power-managed run modes 0000h u (2) u1uuu u u mclr during power-managed idle modes and sleep mode 0000h u (2) u10uu u u wdt time-out during full power or power-managed run mode 0000h u (2) u0uuu u u mclr during full power execution 0000h u (2) uuuuu u u stack full reset (stvren = 1 ) 0000h u (2) uuuuu 1 u stack underflow reset (stvren = 1 ) 0000h u (2) uuuuu u 1 stack underflow error (not an actual reset, stvren = 0 ) 0000h u (2) uuuuu u 1 wdt time-out during power- managed idle or sleep modes pc + 2 u (2) u00uu u u interrupt exit from power- managed modes pc + 2 (1) u (2) uu0uu u u legend: u = unchanged note 1: when the wake-up is due to an interrupt and the gieh or giel bits are set, the pc is loaded with the interrupt vector (008h or 0018h). 2: reset state is ? 1 ? for sboren and unchanged for all other resets when software bor is enabled (boren<1:0> configuration bits = 01 ). otherwise, the reset state is ? 0 ?. table 5-4: registers associated with resets name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page rcon ipen sboren ?ri to pd por bor 68 stkptr stkful stkunf ? stkptr<4:0> 80 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used for resets. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 76 ? 2012 microchip technology inc. table 5-5: configuratio n registers associated with resets name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page config2l ? lpbor ? borv<1:0> boren<1:0> pwrten 389 config2h ? ? wdtps<3:0> wdten<1:0> 390 config3h mclre sdomx ? t3cmx ? ? pbaden ccp2mx 391 config4l debug xinst icprt ? ? lvp ? strven 392 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used for resets. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 77 pic18(l)f2x/45k50 6.0 memory organization there are three types of memory in pic18 enhanced microcontroller devices: ? program memory ? data ram ? data eeprom as harvard architecture devices, the data and program memories use separate buses; this allows for concurrent access of the two memory spaces. the data eeprom, for practical purposes, can be regarded as a peripheral device, since it is addressed and accessed through a set of control registers. additional detailed information on the operation of the flash program memory is provided in section 7.0 ?flash program memory? . data eeprom is discussed separately in section 8.0 ?data eeprom memory? . 6.1 program memory organization pic18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2-mbyte program memory space. accessing a location between the upper boundary of the physically implemented memory and the 2-mbyte address will return all ? 0 ?s (a nop instruction). this family of devices contain the following: ? pic18(l)f24k50: 16 kbytes of flash memory, up to 8,192 single-word instructions ? pic18(l)f25k50, pic18(l)f45k50: 32 kbytes of flash memory, up to 16,384 single-word instructions pic18 devices have two interrupt vectors. the reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. the program memory map for pic18(l)f2x/45k50 devices is shown in figure 6-1 . memory block details are shown in figure 21-2 . figure 6-1: program memory map and stack for pic18(l)f2x/45k50 devices pc<20:0> stack level 1 ? stack level 31 reset vector low priority interrupt vector ? ? call,rcall,return retfie,retlw 21 0000h 0018h on-chip program memory high priority interrupt vector 0008h user memory space 1fffffh 4000h 3fffh read ? 0 ? 200000h 8000h 7fffh on-chip program memory read ? 0 ? pic18(l)f25k50 pic18(l)f45k50 pic18(l)f24k50 www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 78 ? 2012 microchip technology inc. 6.1.1 program counter the program counter (pc) specifies the address of the instruction to fetch for execution. the pc is 21 bits wide and is contained in three separate 8-bit registers. the low byte, known as the pcl register, is both readable and writable. the high byte, or pch register, contains the pc<15:8> bits; it is not directly readable or writable. updates to the pch register are performed through the pclath register. the upper byte is called pcu. this register contains the pc<20:16> bits; it is also not directly readable or writable. updates to the pcu register are performed through the pclatu register. the contents of pclath and pclatu are transferred to the program counter by any operation that writes pcl. similarly, the upper two bytes of the program counter are transferred to pclath and pclatu by an operation that reads pcl. this is useful for computed offsets to the pc (see section 6.2.3.1 ?computed goto? ). the pc addresses bytes in the program memory. to prevent the pc from becoming misaligned with word instructions, the least significant bit of pcl is fixed to a value of ? 0 ?. the pc increments by two to address sequential instructions in the program memory. the call , rcall , goto and program branch instructions write to the program counter directly. for these instructions, the contents of pclath and pclatu are not transferred to the program counter. 6.1.2 return address stack the return address stack allows any combination of up to 31 program calls and interrupts to occur. the pc is pushed onto the stack when a call or rcall instruction is executed or an interrupt is acknowledged. the pc value is pulled off the stack on a return, retlw or a retfie instruction. pclatu and pclath are not affected by any of the return or call instructions. the stack operates as a 31-word by 21-bit ram and a 5-bit stack pointer, stkptr. the stack space is not part of either program or data space. the stack pointer is readable and writable and the address on the top of the stack is readable and writable through the top-of- stack (tos) special file registers. data can also be pushed to, or popped from the stack, using these registers. a call type instruction causes a push onto the stack; the stack pointer is first incremented and the location pointed to by the stack pointer is written with the contents of the pc (already pointing to the instruction following the call ). a return type instruction causes a pop from the stack; the contents of the location pointed to by the stkptr are transferred to the pc and then the stack pointer is decremented. the stack pointer is initialized to ? 00000 ? after all resets. there is no ram associated with the location corresponding to a stack pointer value of ? 00000 ?; this is only a reset value. status bits indicate if the stack is full or has overflowed or has underflowed. 6.1.2.1 top-of-stack access only the top of the return address stack (tos) is readable and writable. a set of three registers, tosu:tosh:tosl, hold the contents of the stack location pointed to by the stkptr register ( figure 6-2 ). this allows users to implement a software stack if necessary. after a call, rcall or interrupt, the software can read the pushed value by reading the tosu:tosh:tosl registers. these values can be placed on a user defined software stack. at return time, the software can return these values to tosu:tosh:tosl and do a return. the user must disable the global interrupt enable (gie) bits while accessing the stack to prevent inadvertent stack corruption. figure 6-2: return address stack and associated registers 00011 001a34h 11111 11110 11101 00010 00001 00000 00010 return address stack <20:0> to p - o f - st a c k 000d58h tosl tosh tosu 34h 1ah 00h stkptr<4:0> top-of-stack registers stack pointer www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 79 pic18(l)f2x/45k50 6.1.2.2 return stack pointer (stkptr) the stkptr register ( register 6-1 ) contains the stack pointer value, the stkful (stack full) status bit and the stkunf (stack underflow) status bits. the value of the stack pointer can be 0 through 31. the stack pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. on reset, the stack pointer value will be zero. the user may read and write the stack pointer value. this feature can be used by a real-time operating system (rtos) for return stack maintenance. after the pc is pushed onto the stack 31 times (without popping any values off the stack), the stkful bit is set. the stkful bit is cleared by software or by a por. the action that takes place when the stack becomes full depends on the state of the stvren (stack over- flow reset enable) configuration bit. (refer to section 26.1 ?configuration bits? for a description of the device configuration bits.) if stvren is set (default), the 31st push will push the (pc + 2) value onto the stack, set the stkful bit and reset the device. the stkful bit will remain set and the stack pointer will be set to zero. if stvren is cleared, the stkful bit will be set on the 31st push and the stack pointer will increment to 31. any additional pushes will not overwrite the 31 st push and stkptr will remain at 31. when the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the pc and sets the stkunf bit, while the stack pointer remains at zero. the stkunf bit will remain set until cleared by software or until a por occurs. note: returning a value of zero to the pc on an underflow has the effect of vectoring the program to the reset vector, where the stack conditions can be verified and appropriate actions can be taken. this is not the same as a reset, as the contents of the sfrs are not affected. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 80 ? 2012 microchip technology inc. 6.1.2.3 push and pop instructions since the top-of-stack is readable and writable, the ability to push values onto the stack and pull values off the stack without disturbing normal program execution is a desirable feature. the pic18 instruction set includes two instructions, push and pop , that permit the tos to be manipulated under software control. tosu, tosh and tosl can be modified to place data or a return address on the stack. the push instruction places the current pc value onto the stack. this increments the stack pointer and loads the current pc value onto the stack. the pop instruction discards the current tos by decre- menting the stack pointer. the previous value pushed onto the stack then becomes the tos value. 6.2 register definitions: stack pointer 6.2.1 stack full and underflow resets device resets on stack overflow and stack underflow conditions are enabled by setting the stvren bit in configuration register 4l. when stvren is set, a full or underflow will set the appropriate stkful or stkunf bit and then cause a device reset. when stvren is cleared, a full or underflow condition will set the appropriate stkful or stkunf bit but not cause a device reset. the stkful or stkunf bits are cleared by the user software or a power-on reset. 6.2.2 fast register stack a fast register stack is provided for the status, wreg and bsr registers, to provide a ?fast return? option for interrupts. the stack for each register is only one level deep and is neither readable nor writable. it is loaded with the current value of the corresponding register when the processor vectors for an interrupt. all inter- rupt sources will push values into the stack registers. the values in the registers are then loaded back into their associated registers if the retfie, fast instruction is used to return from the interrupt. if both low and high priority interrupts are enabled, the stack registers cannot be used reliably to return from low priority interrupts. if a high priority interrupt occurs while servicing a low priority interrupt, the stack register values stored by the low priority interrupt will be overwritten. in these cases, users must save the key registers by software during a low priority interrupt. if interrupt priority is not used, all interrupts may use the fast register stack for returns from interrupt. if no interrupts are used, the fast register stack can be used to restore the status, wreg and bsr registers at the end of a subroutine call. to use the fast register stack for a subroutine call, a call label , fast instruction must be executed to save the status, wreg and bsr registers to the fast register stack. a return , fast instruction is then executed to restore these registers from the fast register stack. example 6-1 shows a source code example that uses the fast register stack during a subroutine call and return. register 6-1: stkptr: stack pointer register r/c-0 r/c-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 stkful (1) stkunf (1) ? stkptr<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented c = clearable only bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 stkful: stack full flag bit (1) 1 = stack became full or overflowed 0 = stack has not become full or overflowed bit 6 stkunf: stack underflow flag bit (1) 1 = stack underflow occurred 0 = stack underflow did not occur bit 5 unimplemented: read as ? 0 ? bit 4-0 stkptr<4:0>: stack pointer location bits note 1: bit 7 and bit 6 are cleared by user software or by a por. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 81 pic18(l)f2x/45k50 example 6-1: fast register stack code example 6.2.3 look-up tables in program memory there may be programming situations that require the creation of data structures, or look-up tables, in program memory. for pic18 devices, look-up tables can be implemented in two ways: ? computed goto ? table reads 6.2.3.1 computed goto a computed goto is accomplished by adding an offset to the program counter. an example is shown in example 6-2 . a look-up table can be formed with an addwf pcl instruction and a group of retlw nn instructions. the w register is loaded with an offset into the table before executing a call to that table. the first instruction of the called routine is the addwf pcl instruction. the next instruction executed will be one of the retlw nn instructions that returns the value ? nn ? to the calling function. the offset value (in wreg) specifies the number of bytes that the program counter should advance and should be multiples of 2 (lsb = 0 ). in this method, only one data byte may be stored in each instruction location and room on the return address stack is required. example 6-2: computed goto using an offset value 6.2.3.2 table reads and table writes a better method of storing data in program memory allows two bytes of data to be stored in each instruction location. look-up table data may be stored two bytes per program word by using table reads and writes. the table pointer (tblptr) register specifies the byte address and the table latch (tablat) register contains the data that is read from or written to program memory. data is transferred to or from program memory one byte at a time. table read and table write operations are discussed further in section 7.1 ?table reads and table writes? . call sub1, fast ;status, wreg, bsr ;saved in fast register ;stack ? ? sub1 ? ? return, fast ;restore values saved ;in fast register stack movf offset, w call table org nn00h table addwf pcl retlw nnh retlw nnh retlw nnh . . . www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 82 ? 2012 microchip technology inc. 6.3 pic18 instruction cycle 6.3.1 clocking scheme the microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four non-overlapping quadrature clocks (q1, q2, q3 and q4). internally, the program counter is incremented on every q1; the instruction is fetched from the program memory and latched into the instruction register during q4. the instruction is decoded and executed during the following q1 through q4. the clocks and instruction execution flow are shown in figure 6-3 . 6.3.2 instruction flow/pipelining an ?instruction cycle? consists of four q cycles: q1 through q4. the instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the program counter to change (e.g., goto ), then two cycles are required to complete the instruction ( example 6-3 ). a fetch cycle begins with the program counter (pc) incrementing in q1. in the execution cycle, the fetched instruction is latched into the instruction register (ir) in cycle q1. this instruction is then decoded and executed during the q2, q3 and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). figure 6-3: clock/ instruction cycle example 6-3: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc osc2/clko (rc mode) pc pc + 2 pc + 4 fetch inst (pc) execute inst (pc ? 2) fetch inst (pc + 2) execute inst (pc) fetch inst (pc + 4) execute inst (pc + 2) internal phase clock all instructions are single cycle, except for any program branches. these take two cycles since the fetch instruction is ?flushed? from the pipeline while the new instruction is being fetched and then executed. t cy 0t cy 1t cy 2t cy 3t cy 4t cy 5 1. movlw 55h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. bra sub_1 fetch 3 execute 3 4. bsf porta, bit3 (forced nop) fetch 4 flush ( nop ) 5. instruction @ address sub_1 fetch sub_1 execute sub_1 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 83 pic18(l)f2x/45k50 6.3.3 instructions in program memory the program memory is addressed in bytes. instructions are stored as either two bytes or four bytes in program memory. the least significant byte of an instruction word is always stored in a program memory location with an even address (lsb = 0 ). to maintain alignment with instruction boundaries, the pc increments in steps of two and the lsb will always read ? 0 ? (see section 6.1.1 ?program counter? ). figure 6-4 shows an example of how instruction words are stored in the program memory. the call and goto instructions have the absolute program memory address embedded into the instruction. since instructions are always stored on word boundaries, the data contained in the instruction is a word address. the word address is written to pc<20:1>, which accesses the desired byte address in program memory. instruction #2 in figure 6-4 shows how the instruction goto 0006h is encoded in the program memory. program branch instructions, which encode a relative address offset, operate in the same manner. the offset value stored in a branch instruction represents the number of single-word instructions that the pc will be offset by. section 27.0 ?instruction set summary? provides further details of the instruction set. figure 6-4: instructions in program memory 6.3.4 two-word instructions the standard pic18 instruction set has four two-word instructions: call , movff , goto and lsfr . in all cases, the second word of the instruction always has ? 1111 ? as its four most significant bits; the other 12 bits are literal data, usually a data memory address. the use of ? 1111 ? in the four msbs of an instruction specifies a special form of nop . if the instruction is executed in proper sequence ? immediately after the first word ? the data in the second word is accessed and used by the instruction sequence. if the first word is skipped for some reason and the second word is executed by itself, a nop is executed instead. this is necessary for cases when the two-word instruction is preceded by a conditional instruction that changes the pc. example 6-4 shows how this works. example 6-4: two- word instructions word address lsb = 1 lsb = 0 ? program memory byte locations ? ? 000000h 000002h 000004h 000006h instruction 1: movlw 055h 0fh 55h 000008h instruction 2: goto 0006h efh 03h 00000ah f0h 00h 00000ch instruction 3: movff 123h, 456h c1h 23h 00000eh f4h 56h 000010h 000012h 000014h note: see section 6.8 ?pic18 instruction execution and the extended instruc- tion set? for information on two-word instructions in the extended instruction set. case 1: object code source code 0110 0110 0000 0000 tstfsz reg1 ; is ram location 0? 1100 0001 0010 0011 movff reg1, reg2 ; no, skip this word 1111 0100 0101 0110 ; execute this word as a nop 0010 0100 0000 0000 addwf reg3 ; continue code case 2: object code source code 0110 0110 0000 0000 tstfsz reg1 ; is ram location 0? 1100 0001 0010 0011 movff reg1, reg2 ; yes, execute this word 1111 0100 0101 0110 ; 2nd word of instruction 0010 0100 0000 0000 addwf reg3 ; continue code www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 84 ? 2012 microchip technology inc. 6.4 data memory organization the data memory in pic18 devices is implemented as static ram. each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. the memory space is divided into as many as 16 banks that contain 256 bytes each. figures 6-5 through 6-7 show the data memory organization for the pic18(l)f2x/45k50 devices. the data memory contains special function registers (sfrs) and general purpose registers (gprs). the sfrs are used for control and status of the controller and peripheral functions, while gprs are used for data storage and scratchpad operations in the user?s application. any read of an unimplemented location will read as ? 0 ?s. the instruction set and architecture allow operations across all banks. the entire data memory may be accessed by direct, indirect or indexed addressing modes. addressing modes are discussed later in this subsection. to ensure that commonly used registers (sfrs and select gprs) can be accessed in a single cycle, pic18 devices implement an access bank. this is a 256-byte memory space that provides fast access to sfrs and the lower portion of gpr bank 0 without using the bank select register (bsr). section 6.4.3 ?access bank? provides a detailed description of the access ram. 6.4.1 usb ram banks 4 through 7 of the data memory are actually mapped to special dual port ram. when the usb module is disabled, the gprs in these banks are used like any other gpr in the data memory space. when the usb module is enabled, the memory in these banks is allocated as buffer ram for usb operation. this area is shared between the microcontroller core and the usb serial interface engine (sie) and is used to transfer data directly between the two. it is theoretically possible to use the areas of usb ram that are not allocated as usb buffers for normal scratchpad memory or other variable storage. in practice, the dynamic nature of buffer allocation makes this risky, at best. additionally, bank 4 is used for usb buffer descriptor tables when the module is enabled and should not be used for any other purposes during that time. additional information on usb ram and buffer operation is provided in section 24.0 ?universal serial bus (usb)? . 6.4.2 bank select register (bsr) large areas of data memory require an efficient addressing scheme to make rapid access to any address possible. ideally, this means that an entire address does not need to be provided for each read or write operation. for pic18 devices, this is accom- plished with a ram banking scheme. this divides the memory space into 16 contiguous banks of 256 bytes. depending on the instruction, each location can be addressed directly by its full 12-bit address, or an 8-bit low-order address and a 4-bit bank pointer. most instructions in the pic18 instruction set make use of the bank pointer, known as the bank select register (bsr). this sfr holds the four most significant bits of a location?s address; the instruction itself includes the eight least significant bits. only the four lower bits of the bsr are implemented (bsr<3:0>). the upper four bits are unused; they will always read ? 0 ? and cannot be written to. the bsr can be loaded directly by using the movlb instruction. the value of the bsr indicates the bank in data memory; the eight bits in the instruction show the location in the bank and can be thought of as an offset from the bank?s lower boundary. the relationship between the bsr?s value and the bank division in data memory is shown in figures 6-5 through 6-7 . since up to 16 registers may share the same low-order address, the user must always be careful to ensure that the proper bank is selected before performing a data read or write. for example, writing what should be program data to an 8-bit address of f9h while the bsr is 0fh will end up resetting the program counter. while any bank can be selected, only those banks that are actually implemented can be read or written to. writes to unimplemented banks are ignored, while reads from unimplemented banks will return ? 0 ?s. even so, the status register will still be affected as if the operation was successful. the data memory maps in figures 6-5 through 6-7 indicate which banks are implemented. in the core pic18 instruction set, only the movff instruction fully specifies the 12-bit address of the source and target registers. this instruction ignores the bsr completely when it executes. all other instructions include only the low-order address as an operand and must use either the bsr or the access bank to locate their target registers. note: the operation of some aspects of data memory are changed when the pic18 extended instruction set is enabled. see section 6.7 ?data memory and the extended instruction set? for more information. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 85 pic18(l)f2x/45k50 figure 6-5: data memory map for pic18(l)f2x/45k50 devices bank 0 bank 1 bank 14 bank 15 data memory map bsr<3:0> = 0000 = 0001 = 1111 060h 05fh 00h 5fh 60h ffh access bank when ?a? = 0 : the bsr is ignored and the access bank is used. the first 96 bytes are general purpose ram (from bank 0). the second 160 bytes are special function registers (from bank 15). when ?a? = 1 : the bsr specifies the bank used by the instruction. 1ffh 100h 0ffh 000h access ram ffh 00h ffh 00h gpr gpr access ram high access ram low bank 2 = 0110 = 0010 (sfrs) 2ffh 200h 3ffh 300h 4ffh 400h 5ffh 500h 6ffh 600h 7ffh 700h 8ffh 800h 9ffh 900h affh a00h bffh b00h cffh c00h dffh d00h e00h bank 3 bank 4 bank 5 bank 6 bank 7 bank 8 bank 9 bank 10 bank 11 bank 12 bank 13 ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h gpr ffh 00h = 0011 = 0100 = 0101 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 gpr gpr (2) gpr (2) gpr (2) gpr (2) note 1: addresses f53h through f5fh are also used by sfrs, but are not part of the access ram. users must always use the complete address or load the proper bsr value to access these registers. 2: these banks also serve as ram buffer for usb operation. see section 6.4.1 ?usb ram? for more information. f60h fffh f5fh f00h ffh 00h sfr (1) unimplemented sfr f53h f52h unimplemented. read as 00h. unimplemented. read as 00h. unimplemented. read as 00h. unimplemented. read as 00h. unimplemented. read as 00h. unimplemented. read as 00h. unimplemented. read as 00h. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 86 ? 2012 microchip technology inc. figure 6-6: use of the bank select register (direct addressing) note 1: the access ram bit of the instruction can be used to force an override of the selected bank (bsr<3:0>) to the registers of the access bank. 2: the movff instruction embeds the entire 12-bit address in the instruction. data memory bank select (2) 7 0 from opcode (2) 0000 000h 100h 200h 300h f00h e00h fffh bank 0 bank 1 bank 2 bank 14 bank 15 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh bank 3 through bank 13 0011 11111111 7 0 bsr (1) www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 87 pic18(l)f2x/45k50 6.4.3 access bank while the use of the bsr with an embedded 8-bit address allows users to address the entire range of data memory, it also means that the user must always ensure that the correct bank is selected. otherwise, data may be read from or written to the wrong location. this can be disastrous if a gpr is the intended target of an operation, but an sfr is written to instead. verifying and/or changing the bsr for each read or write to data memory can become very inefficient. to streamline access for the most commonly used data memory locations, the data memory is configured with an access bank, which allows users to access a mapped block of memory without specifying a bsr. the access bank consists of the first 96 bytes of mem- ory (00h-5fh) in bank 0 and the last 160 bytes of mem- ory (60h-ffh) in block 15. the lower half is known as the ?access ram? and is composed of gprs. this upper half is also where the device?s sfrs are mapped. these two areas are mapped contiguously in the access bank and can be addressed in a linear fashion by an 8-bit address (figures 6-5 through 6-7 ). the access bank is used by core pic18 instructions that include the access ram bit (the ?a? parameter in the instruction). when ?a? is equal to ? 1 ?, the instruction uses the bsr and the 8-bit address included in the opcode for the data memory address. when ?a? is ? 0 ?, however, the instruction is forced to use the access bank address map; the current value of the bsr is ignored entirely. using this ?forced? addressing allows the instruction to operate on a data address in a single cycle, without updating the bsr first. for 8-bit addresses of 60h and above, this means that users can evaluate and operate on sfrs more efficiently. the access ram below 60h is a good place for data values that the user might need to access rapidly, such as immediate computational results or common program variables. access ram also allows for faster and more code efficient context saving and switching of variables. the mapping of the access bank is slightly different when the extended instruction set is enabled (xinst configuration bit = 1 ). this is discussed in more detail in section 6.7.3 ?mapping the access bank in indexed literal offset mode? . 6.4.4 general purpose register file pic18 devices may have banked memory in the gpr area. this is data ram, which is available for use by all instructions. gprs start at the bottom of bank 0 (address 000h) and grow upwards towards the bottom of the sfr area. gprs are not initialized by a power-on reset and are unchanged on all other resets. 6.4.5 special function registers the special function registers (sfrs) are registers used by the cpu and peripheral modules for controlling the desired operation of the device. these registers are implemented as static ram. sfrs start at the top of data memory (fffh) and extend downward to occupy the top portion of bank 15 (f53h to fffh). a list of these registers is given in ta b l e 6 - 1 and tab l e 6 - 2 . the sfrs can be classified into two sets: those associated with the ?core? device functionality (alu, resets and interrupts) and those related to the peripheral functions. the reset and interrupt registers are described in their respective chapters, while the alu?s status register is described later in this section. registers related to the operation of a peripheral feature are described in the chapter for that peripheral. the sfrs are typically distributed among the peripherals whose functions they control. unused sfr locations are unimplemented and read as ? 0 ?s. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 88 ? 2012 microchip technology inc. table 6-1: special function register map for pic18(l)f2x/45k50 devices address name address name address name address name address name fffh tosu fd7h tmr0h fafh spbrg1 f87h iocc f5fh ansele (3) ffeh tosh fd6h tmr0l faeh rcreg1 f86h iocb f5eh anseld (3) ffdh tosl fd5h t0con fadh txreg1 f85h wpub f5dh anselc ffch stkptr fd4h ? (2) fach txsta1 f84h porte f5ch anselb ffbh pclatu fd3h osccon fabh rcsta1 f83h portd (3) f5bh ansela ffah pclath fd2h osccon2 faah ? f82h portc f5ah vregcon (4) ff9h pcl fd1h wdtcon fa9h eeadr f81h portb f59h ccptmrs ff8h tblptru fd0h rcon fa8h eedata f80h porta f58h srcon0 ff7h tblptrh fcfh tmr1h fa7h eecon2 (1) f7fh pmd1 f57h srcon1 ff6h tblptrl fceh tmr1l fa6h eecon1 f7eh pmd0 f56h ? ff5h tablat fcdh t1con fa5h ipr3 f7dh vrefcon0 f55h ? ff4h prodh fcch t1gcon fa4h pir3 f7ch vrefcon1 f54h ? ff3h prodl fcbh ssp1con3 fa3h pie3 f7bh vrefcon2 f53h ? ff2h intcon fcah ssp1msk fa2h ipr2 f7ah slrcon f52h general purpose ram ff1h intcon2 fc9h ssp1buf fa1h pir2 f79h uep15 f51h ff0h intcon3 fc8h ssp1add fa0h pie2 f78h uep14 f50h fefh indf0 (1) fc7h ssp1stat f9fh ipr1 f77h uep13 f4fh feeh postinc0 (1) fc6h ssp1con1 f9eh pir1 f76h uep12 f4eh fedh postdec0 (1) fc5h ssp1con2 f9dh pie1 f75h uep11 f4dh fech preinc0 (1) fc4h adresh f9ch hlvdcon f74h uep10 f4ch febh plusw0 (1) fc3h adresl f9bh osctune f73h uep9 f4bh feah fsr0h fc2h adcon0 f9ah cm2con1 f72h uep8 f4ah fe9h fsr0l fc1h adcon1 f99h cm2con0 f71h uep7 f49h fe8h wreg fc0h adcon2 f98h cm1con0 f70h uep6 f48h fe7h indf1 (1) fbfh ccpr1h f97h ccp2con f6fh uep5 f47h fe6h postinc1 (1) fbeh ccpr1l f96h trise (3) f6eh uep4 f46h fe5h postdec1 (1) fbdh ccp1con f95h trisd (3) f6dh uep3 f45h fe4h preinc1 (1) fbch tmr2 f94h trisc f6ch uep2 f44h fe3h plusw1 (1) fbbh pr2 f93h trisb f6bh uep1 f43h fe2h fsr1h fbah t2con f92h trisa f6ah uep0 f42h fe1h fsr1l fb9h pstr1con f91h ccpr2h f69h ufrmh f41h fe0h bsr fb8h baudcon1 f90h ccpr2l f68h ufrml f40h fdfh indf2 (1) fb7h pwm1con f8fh ctmuconh f67h ueir f3fh fdeh postinc2 (1) fb6h eccp1as f8eh ctmuconl f66h ueie f3eh fddh postdec2 (1) fb5h stcon f8dh late (3) f65h uir f3dh fdch preinc2 (1) fb4h t3gcon f8ch latd (3) f64h uie f3ch fdbh plusw2 (1) fb3h tmr3h f8bh latc f63h uaddr f3bh fdah fsr2h fb2h tmr3l f8ah latb f62h ucnfg f3ah fd9h fsr2l fb1h t3con f89h lata f61h ustat f39h fd8h status fb0h spbrgh1 f88h ctmuiconh f60h uctrl f38h note 1: this is not a physical register. 2: unimplemented registers are read as ? 0 ?. 3: pic18(l)f45k50 device only. 4: f devices only. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 89 pic18(l)f2x/45k50 table 6-2: register file summary for pic18(l)f2x/45k50 devices address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor fffh tosu ? ? ? top-of-stack, upper byte (tos<20:16>) ---0 0000 ffeh tosh top-of-stack, high byte (tos<15:8>) 0000 0000 ffdh tosl top-of-stack, low byte (tos<7:0>) 0000 0000 ffch stkptr stkful stkunf ?stkptr<4:0> 00-0 0000 ffbh pclatu ? ? ? holding register for pc<20:16> ---0 0000 ffah pclath holding register for pc<15:8> 0000 0000 ff9h pcl holding register for pc<7:0> 0000 0000 ff8h tblptru ? ? program memory table pointer upper byte (tblptr<21:16>) --00 0000 ff7h tblptrh program memory table pointer high byte (tblptr<15:8>) 0000 0000 ff6h tblptrl program memory table pointer low byte (tblptr<7:0>) 0000 0000 ff5h tablat program memory table latch 0000 0000 ff4h prodh product register, high byte xxxx xxxx ff3h prodl product register, low byte xxxx xxxx ff2h intcon gie/gieh peie/giel tmr0ie int0ie iocie tmr0if int0if iocif 0000 000x ff1h intcon2 rbpu intedg0 intedg1 intedg2 ?tmr0ip ?iocip 1111 -1-1 ff0h intcon3 int2ip int1ip ? int2ie int1ie ?int2ifint1if 11-0 0-00 fefh indf0 uses contents of fsr0 to address data memory ? value of fsr0 not changed (not a physical register) ---- ---- feeh postinc0 uses contents of fsr0 to address data memory ? value of fsr0 post-incremented (not a physical register) ---- ---- fedh postdec0 uses contents of fsr0 to address data memory ? value of fsr0 post-decremented (not a physical register) ---- ---- fech preinc0 uses contents of fsr0 to address data memory ? value of fsr0 pre-incremented (not a physical register) ---- ---- febh plusw0 uses contents of fsr0 to address data memory ? value of fsr0 pre-incremented (not a physical register) ? value of fsr0 offset by w ---- ---- feah fsr0h ? ? ? ? indirect data memory address pointer 0, high byte ---- 0000 fe9h fsr0l indirect data memory address pointer 0, low byte xxxx xxxx fe8h wreg working register xxxx xxxx fe7h indf1 uses contents of fsr1 to address data memory ? value of fsr1 not changed (not a physical register) ---- ---- fe6h postinc1 uses contents of fsr1 to address data memory ? value of fsr1 post-incremented (not a physical register) ---- ---- fe5h postdec1 uses contents of fsr1 to address data memory ? value of fsr1 post-incremented (not a physical register) ---- ---- fe4h preinc1 uses contents of fsr1 to address data memory ? value of fsr1 pre-incremented (not a physical register) ---- ---- fe3h plusw1 uses contents of fsr1 to address data memory ? value of fsr1 pre-incremented (not a physical register) ? value of fsr1 offset by w ---- ---- fe2h fsr1h ? ? ? ? indirect data memory address pointer 1, high byte ---- 0000 fe1h fsr1l indirect data memory address pointer 1, low byte xxxx xxxx fe0h bsr ? ? ? ? bank select register ---- 0000 fdfh indf2 uses contents of fsr2 to address data memory ? value of fsr2 not changed (not a physical register) ---- ---- fdeh postinc2 uses contents of fsr2 to address data memory ? value of fsr2 post-incremented (not a physical register) ---- ---- fddh postdec2 uses contents of fsr2 to address data memory ? value of fsr2 post-decremented (not a physical register) ---- ---- fdch preinc2 uses contents of fsr2 to address data memory ? value of fsr2 pre-incremented (not a physical register) ---- ---- fdbh plusw2 uses contents of fsr2 to address data memory ? value of fsr2 pre-incremented (not a physical register) ? value of fsr2 offset by w ---- ---- fdah fsr2h ? ? ? ? indirect data memory address pointer 2, high byte ---- 0000 fd9h fsr2l indirect data memory address pointer 2, low byte xxxx xxxx fd8h status ? ? ?novzdcc ---x xxxx fd7h tmr0h timer0 register, high byte 0000 0000 fd6h tmr0l timer0 register, low byte xxxx xxxx fd5h t0con tmr0on t08bit t0cs t0se psa t0ps<2:0> 1111 1111 fd3h osccon idlen ircf<2:0> osts hfiofs scs<1:0> 0011 q000 fd2h osccon2 pllrdy soscrun intsrc pllen soscgo prisd hfiofr lfiofs 0000 0100 fd1h wdtcon ? ? ? ? ? ? ?swdten ---- ---0 fd0h rcon ipen sboren ? ri to pd por bor 01-1 1100 legend: x = unknown, u = unchanged, ? = unimplemented, q = value depends on condition note 1: pic18(l)f45k50 devices only. 2: pic18(l)f2xk50 devices only. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 90 ? 2012 microchip technology inc. fcfh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx fceh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx fcdh t1con tmr1cs<1:0> t1ckps<1:0> soscen t1sync rd16 tmr1on 0000 0000 fcch t1gcon tmr1ge t1gpol t1gtm t1gspm t1ggo/ done t1gval t1gss<1:0> 0000 0x00 fcbh ssp1con3 acktim pcie scie boen sdaht sbcde ahen dhen 0000 0000 fcah ssp1msk ssp1 mask register bits 1111 1111 fc9h ssp1buf ssp1 receive buffer/transmit register xxxx xxxx fc8h ssp1add ssp1 address register in i 2 c slave mode. ssp1 baud rate reload register in i 2 c master mode 0000 0000 fc7h ssp1stat smp cke d/a psr/w ua bf 0000 0000 fc6h ssp1con1 wcol sspov sspen ckp sspm<3:0> 0000 0000 fc5h ssp1con2 gcen ackstat ackdt acken rcen pen rsen sen 0000 0000 fc4h adresh a/d result, high byte xxxx xxxx fc3h adresl a/d result, low byt xxxx xxxx fc2h adcon0 ? chs<4:0> go/done adon -000 0000 fc1h adcon1 trigsel ? ? ? pvcfg<1:0> nvcfg<1:0> 0--- 0000 fc0h adcon2 adfm ? acqt<2:0> adcs<2:0> 0-00 0000 fbfh ccpr1h capture/compare/pwm register 1, high byte xxxx xxxx fbeh ccpr1l capture/compare/pwm register 1, low byte xxxx xxxx fbdh ccp1con p1m<1:0> dc1b<1:0> ccp1m<3:0> 0000 0000 fbch tmr2 timer2 register 0000 0000 fbbh pr2 timer2 period register 1111 1111 fbah t2con ? t2outps<3:0> tmr2on t2ckps<1:0> -000 0000 fb9h pstr1con ? ? ? str1sync str1d str1c str1b str1a ---0 0001 fb8h baudcon1 abdovf rcidl rxdtp txckp brg16 ? wue abden 0100 0-00 fb7h pwm1con p1rsen p1dc<6:0> 0000 0000 fb6h eccp1as eccp1ase eccp1as<2:0> pss1ac<1:0> pss1bd<1:0> 0000 0000 fb5h actcon acten actud ? actsrc actlock ?actors ? 00-0 0-0- fb4h t3gcon tmr3ge t3gpol t3gtm t3gspm t3ggo/ done t3gval t3gss<1:0> 0000 0x00 fb3h tmr3h holding register for the most significant byte of the 16-bit tmr3 register xxxx xxxx fb2h tmr3l holding register for the least significant byte of the 16-bit tmr3 register xxxx xxxx fb1h t3con tmr3cs<1:0> t3ckps<1:0> soscen t3sync rd16 tmr3on 0000 0000 fb0h spbrgh1 eusart baud rate generator, high byte 0000 0000 fafh spbrg1 eusart baud rate generator, low byte 0000 0000 faeh rcreg1 eusart receive register 0000 0000 fadh txreg1 eusart transmit register 0000 0000 fach txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 0000 0010 fabh rcsta1 spen rx9 sren cren adden ferr oerr rx9d 0000 000x fa9h eeadr eeadr<7:0> 0000 0000 fa8h eedata eeprom data register 0000 0000 fa7h eecon2 eeprom control register 2 (not a physical register) ---- ---- fa6h eecon1 eepgd cfgs ? free wrerr wren wr rd xx-0 x000 fa5h ipr3 ? ? ? ? ctmuip usbip tmr3gip tmr1gip 0000 1111 fa4h pir3 ? ? ? ? ctmuif usbif tmr3gif tmr1gif 0000 0000 fa3h pie3 ? ? ? ? ctmuie usbie tmr3gie tmr1gie 0000 0000 fa2h ipr2 oscfip c1ip c2ip eeip bclip hlvdip tmr3ip ccp2ip 1111 1111 fa1h pir2 oscfif c1if c2if eeif bclif hlvdif tmr3if ccp2if 0000 0000 fa0h pie2 oscfie c1ie c2ie eeie bclie hlvdie tmr3ie ccp2ie 0000 0000 table 6-2: register file summary for pic18(l)f2x/45k50 devices (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor legend: x = unknown, u = unchanged, ? = unimplemented, q = value depends on condition note 1: pic18(l)f45k50 devices only. 2: pic18(l)f2xk50 devices only. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 91 pic18(l)f2x/45k50 f9fh ipr1 actip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 f9eh pir1 actif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 f9dh pie1 actie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 f9ch hlvdcon vdirmag bgvst irvst hlvden hlvdl<3:0> 0000 0000 f9bh osctune spllmult tun<6:0> 0000 0000 f9ah cm2con1 mc1out mc2out c1rsel c2rsel c1hys c2hys c1sync c2sync 0000 0000 f99h cm2con0 c2on c2out c2oe c2pol c2sp c2r c2ch<1:0> 0000 1000 f98h cm1con0 c1on c1out c1oe c1pol c1sp c1r c1ch<1:0> 0000 1000 f97h ccp2con ? ? dc2b<1:0> ccp2m<3:0> --00 0000 f96h trise wpue3 ? ? ? ?trise2 (1) trise1 (1) trise0 (1) 1--- -111 f95h trisd (1) trisd7 trisd6 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 1111 1111 f94h trisc trisc7 trisc6 ? ? ? trisc2 trisc1 trisc0 1111 -111 f93h trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 1111 1111 f92h trisa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 1111 1111 f91h ccpr2h capture/compare/pwm register 2, high byte xxxx xxxx f90h ccpr2l capture/compare/pwm register 2, low byte xxxx xxxx f8fh ctmuconh ctmuen ? ctmusidl tgen edgen edgseqen idissen cttrig 0-00 0000 f8eh ctmuconl edg2pol edg2sel<1:0> edg1pol edg1sel<1:0> edg2stat edg1stat 0000 00xx f8dh late (1) ? ? ? ? ? late2 late1 late0 ---- -xxx f8ch latd (1) latd7 latd6 latd5 latd4 latd3 latd2 latd1 latd0 xxxx xxxx f8bh latc latc7 latc6 ? ? ? latc2 latc1 latc0 xxxx -xxx f8ah latb latb7 latb6 latb5 latb4 latb3 latb2 latb1 latb0 xxxx xxxx f89h lata lata7 lata6 lata5 lata4 lata3 lata2 lata1 lata0 xxxx xxxx f88h ctmuicon itrim<5:0> irng<1:0> 0000 0000 f87h iocc iocc7 iocc6 iocc5 iocc4 ? iocc2 iocc1 iocc0 0000 -000 f86h iocb iocb7 iocb6 iocb5 iocb4 ? ? ? ? 0000 ---- f85h wpub wpub7 wpub6 wpub5 wpub4 wpub3 wpub2 wpub1 wpub0 1111 1111 f84h porte (2) ? ? ? ?re3 ? ? ? ---- x--- porte (1) ? ? ? ?re3re2re1re0 ---- xxxx f83h portd (1) rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx xxxx f82h portc rc7 rc6 ? ? ? rc2 rc1 rc0 xx-- -xxx f81h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx f80h porta ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 xxxx xxxx f7fh pmd1 ? msspmd ctmumd cmp2md cmp1md adcmd ccp2md ccp1md -000 0000 f7eh pmd0 ? uartmd usbmd actmd ? tmr3md tmr2md tmr1md -000 -000 f7dh vrefcon0 fvren fvrst fvrs<1:0> ? ? ? ? 0001 00-- f7ch vrefcon1 dacen daclps dacoe ? dacpss<1:0> ? dacnss 000- 00-0 f7bh vrefcon2 ? ? ? dacr<4:0> ---0 0000 f7ah slrcon ? ? ? slre slrd slrc slrb slra ---1 1111 f79h uep15 ? ? ? ephshk epcondis epouten epinen epstall ---0 0000 f78h uep14 ? ? ? ephshk epcondis epouten epinen epstall ---0 0000 f77h uep13 ? ? ? ephshk epcondis epouten epinen epstall ---0 0000 f76h uep12 ? ? ? ephshk epcondis epouten epinen epstall ---0 0000 f75h uep11 ? ? ? ephshk epcondis epouten epinen epstall ---0 0000 f74h uep10 ? ? ? ephshk epcondis epouten epinen epstall ---0 0000 f73h uep9 ? ? ? ephshk epcondis epouten epinen epstall ---0 0000 f72h uep8 ? ? ? ephshk epcondis epouten epinen epstall ---0 0000 f71h uep7 ? ? ? ephshk epcondis epouten epinen epstall ---0 0000 f70h uep6 ? ? ? ephshk epcondis epouten epinen epstall ---0 0000 table 6-2: register file summary for pic18(l)f2x/45k50 devices (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor legend: x = unknown, u = unchanged, ? = unimplemented, q = value depends on condition note 1: pic18(l)f45k50 devices only. 2: pic18(l)f2xk50 devices only. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 92 ? 2012 microchip technology inc. f6fh uep5 ? ? ? ephshk epcondis epouten epinen epstall ---0 0000 f6eh uep4 ? ? ? ephshk epcondis epouten epinen epstall ---0 0000 f6dh uep3 ? ? ? ephshk epcondis epouten epinen epstall ---0 0000 f6ch uep2 ? ? ? ephshk epcondis epouten epinen epstall ---0 0000 f6bh uep1 ? ? ? ephshk epcondis epouten epinen epstall ---0 0000 f6ah uep0 ? ? ? ephshk epcondis epouten epinen epstall ---0 0000 f69h ufrmh ? ? ? ? ? frm<10:8> ---- -xxx f68h ufrml frm<7:0> xxxx xxxx f67h ueir btsef ? ? btoef dfn8ef crc16ef crc5ef pidef 0--0 0000 f66h ueie btsee ? ? btoee dfn8ee crc16ee crc5ee pidee 0--0 0000 f65h uir ? sofif stallif idleif trnif actvif uerrif urstif -000 0000 f64h uie ? sofie stallie idleie trnie actvie uerrie urstie -000 0000 f63h uaddr ? addr<6:0> -000 0000 f62h ucfg uteye uoemon ? upuen utrdis fsen ppb<1:0> 00-0 0000 f61h ustat ? endp<3:0> dir ppbi ? -xxx xxx- f60h ucon ? ppbrst se0 pktdis usben resume suspnd ? -0x0 000- f5fh ansele ? ? ? ? ? anse2 anse1 anse0 ---- -111 f5eh anseld ansd7 ansd6 ansd5 ansd4 ansd3 ansd2 ansd1 ansd0 1111 1111 f5dh anselc ansc7 ansc6 ? ? ? ansc2 ? ? 11-- -1-- f5ch anselb ? ? ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 --11 1111 f5bh ansela ? ? ansa5 ? ansa3 ansa2 ansa1 ansa0 --1- 1111 f5ah vregcon ? ? ? ? ? ? vregpm<1:0> ---- --01 f59h ccptmrs ? ? ? ? c2tsel ? ? c1tsel ---- 0--0 f58h srcon0 srlen srclk<2:0> srqen srnqen srps srpr 0000 0000 f57h srcon1 srspe srscke srsc2e srsc1e srrpe srrcke srrc2e srrc1e 0000 0000 f56h ? ? ? ? ? ? ? ? ? ---- ---- f55h ? ? ? ? ? ? ? ? ? ---- ---- f54h ? ? ? ? ? ? ? ? ? ---- ---- f53h ? ? ? ? ? ? ? ? ? ---- ---- table 6-2: register file summary for pic18(l)f2x/45k50 devices (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor legend: x = unknown, u = unchanged, ? = unimplemented, q = value depends on condition note 1: pic18(l)f45k50 devices only. 2: pic18(l)f2xk50 devices only. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 93 pic18(l)f2x/45k50 6.4.6 status register the status register, shown in register 6-2 , contains the arithmetic status of the alu. as with any other sfr, it can be the operand for any instruction. if the status register is the destination for an instruc- tion that affects the z, dc, c, ov or n bits, the results of the instruction are not written; instead, the status register is updated according to the instruction per- formed. therefore, the result of an instruction with the status register as its destination may be different than intended. as an example, clrf status will set the z bit and leave the remaining status bits unchanged (? 000u u1uu ?). it is recommended that only bcf , bsf , swapf , movff and movwf instructions are used to alter the status register, because these instructions do not affect the z, c, dc, ov or n bits in the status register. for other instructions that do not affect status bits, see the instruction set summaries in section 27.2 ?extended instruction set? and table 27-3 . 6.5 register definitions: status note: the c and dc bits operate as the b orrow and digit borrow bits, respectively, in subtraction. register 6-2: status: status register u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x ? ? ? nov z dc (1) c (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-5 unimplemented: read as ? 0 ? bit 4 n: negative bit this bit is used for signed arithmetic (two?s complement). it indicates whether the result was negative (alu msb = 1 ). 1 = result was negative 0 = result was positive bit 3 ov: overflow bit this bit is used for signed arithmetic (two?s complement). it indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7 of the result) to change state. 1 = overflow occurred for signed arithmetic (in this arithmetic operation) 0 = no overflow occurred bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc: digit carry/digit b orrow bit ( addwf , addlw,sublw,subwf instructions) (1) 1 = a carry-out from the 4th low-order bit of the result occurred 0 = no carry-out from the 4th low-order bit of the result bit 0 c: carry/borrow bit ( addwf , addlw, sublw, subwf instructions) (2) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note 1: for digit borrow , the polarity is reversed. a subtraction is executed by adding the two?s complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. 2: for borrow , the polarity is reversed. a subtraction is executed by adding the two?s complement of the second operand. for rotate (rrf, rlf) instructions, this bit is loaded with either the high-order or low-order bit of the source register. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 94 ? 2012 microchip technology inc. 6.6 data addressing modes while the program memory can be addressed in only one way ? through the program counter ? information in the data memory space can be addressed in several ways. for most instructions, the addressing mode is fixed. other instructions may use up to three modes, depending on which operands are used and whether or not the extended instruction set is enabled. the addressing modes are: ? inherent ? literal ?direct ?indirect an additional addressing mode, indexed literal offset, is available when the extended instruction set is enabled (xinst configuration bit = 1 ). its operation is discussed in greater detail in section 6.7.1 ?indexed addressing with literal offset? . 6.6.1 inherent and literal addressing many pic18 control instructions do not need any argu- ment at all; they either perform an operation that glob- ally affects the device or they operate implicitly on one register. this addressing mode is known as inherent addressing. examples include sleep , reset and daw . other instructions work in a similar way but require an additional explicit argument in the opcode. this is known as literal addressing mode because they require some literal value as an argument. examples include addlw and movlw , which respectively, add or move a literal value to the w register. other examples include call and goto , which include a 20-bit program memory address. 6.6.2 direct addressing direct addressing specifies all or part of the source and/or destination address of the operation within the opcode itself. the options are specified by the arguments accompanying the instruction. in the core pic18 instruction set, bit-oriented and byte- oriented instructions use some version of direct addressing by default. all of these instructions include some 8-bit literal address as their least significant byte. this address specifies either a register address in one of the banks of data ram ( section 6.4.4 ?general purpose register file? ) or a location in the access bank ( section 6.4.3 ?access bank? ) as the data source for the instruction. the access ram bit ?a? determines how the address is interpreted. when ?a? is ? 1 ?, the contents of the bsr ( section 6.4.2 ?bank select register (bsr)? ) are used with the address to determine the complete 12-bit address of the register. when ?a? is ? 0 ?, the address is interpreted as being a register in the access bank. addressing that uses the access ram is sometimes also known as direct forced addressing mode. a few instructions, such as movff , include the entire 12-bit address (either source or destination) in their opcodes. in these cases, the bsr is ignored entirely. the destination of the operation?s results is determined by the destination bit ?d?. when ?d? is ? 1 ?, the results are stored back in the source register, overwriting its origi- nal contents. when ?d? is ? 0 ?, the results are stored in the w register. instructions without the ?d? argument have a destination that is implicit in the instruction; their destination is either the target register being operated on or the w register. 6.6.3 indirect addressing indirect addressing allows the user to access a location in data memory without giving a fixed address in the instruction. this is done by using file select registers (fsrs) as pointers to the locations which are to be read or written. since the fsrs are themselves located in ram as special file registers, they can also be directly manipulated under program control. this makes fsrs very useful in implementing data struc- tures, such as tables and arrays in data memory. the registers for indirect addressing are also implemented with indirect file operands (indfs) that permit automatic manipulation of the pointer value with auto-incrementing, auto-decrementing or offsetting with another value. this allows for efficient code, using loops, such as the example of clearing an entire ram bank in example 6-5 . example 6-5: how to clear ram (bank 1) using indirect addressing note: the execution of some instructions in the core pic18 instruction set are changed when the pic18 extended instruction set is enabled. see section 6.7 ?data memory and the extended instruction set? for more information. lfsr fsr0, 100h ; next clrf postinc0 ; clear indf ; register then ; inc pointer btfss fsr0h, 1 ; all done with ; bank1? bra next ; no, clear next continue ; yes, continue www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 95 pic18(l)f2x/45k50 6.6.3.1 fsr registers and the indf operand at the core of indirect addressing are three sets of reg- isters: fsr0, fsr1 and fsr2. each represents a pair of 8-bit registers, fsrnh and fsrnl. each fsr pair holds a 12-bit value, therefore, the four upper bits of the fsrnh register are not used. the 12-bit fsr value can address the entire range of the data memory in a linear fashion. the fsr register pairs, then, serve as pointers to data memory locations. indirect addressing is accomplished with a set of indirect file operands, indf0 through indf2. these can be thought of as ?virtual? registers: they are mapped in the sfr space but are not physically implemented. reading or writing to a particular indf register actually accesses its corresponding fsr register pair. a read from indf1, for example, reads the data at the address indicated by fsr1h:fsr1l. instructions that use the indf registers as operands actually use the contents of their corresponding fsr as a pointer to the instruction?s target. the indf operand is just a convenient way of using the pointer. because indirect addressing uses a full 12-bit address, data ram banking is not necessary. thus, the current contents of the bsr and the access ram bit have no effect on determining the target address. 6.6.3.2 fsr registers and postinc, postdec, preinc and plusw in addition to the indf operand, each fsr register pair also has four additional indirect operands. like indf, these are ?virtual? registers which cannot be directly read or written. accessing these registers actually accesses the location to which the associated fsr register pair points, and also performs a specific action on the fsr value. they are: ? postdec: accesses the location to which the fsr points, then automatically decrements the fsr by 1 afterwards ? postinc: accesses the location to which the fsr points, then automatically increments the fsr by 1 afterwards ? preinc: automatically increments the fsr by 1, then uses the location to which the fsr points in the operation ? plusw: adds the signed value of the w register (range of -128 to +127) to that of the fsr and uses the location to which the result points in the operation. in this context, accessing an indf register uses the value in the associated fsr register without changing it. similarly, accessing a plusw register gives the fsr value an offset by that in the w register; however, neither w nor the fsr is actually changed in the operation. accessing the other virtual registers changes the value of the fsr register. figure 6-7: indirect addressing fsr1h:fsr1l 0 7 data memory 000h 100h 200h 300h f00h e00h fffh bank 0 bank 1 bank 2 bank 14 bank 15 bank 3 through bank 13 addwf, indf1, 1 0 7 using an instruction with one of the indirect addressing registers as the operand.... ...uses the 12-bit address stored in the fsr pair associated with that register.... ...to determine the data memory location to be used in that operation. in this case, the fsr1 pair contains ecch. this means the contents of location ecch will be added to that of the w register and stored back in ecch. xxxx 1110 11001100 www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 96 ? 2012 microchip technology inc. operations on the fsrs with postdec, postinc and preinc affect the entire register pair; that is, roll- overs of the fsrnl register from ffh to 00h carry over to the fsrnh register. on the other hand, results of these operations do not change the value of any flags in the status register (e.g., z, n, ov, etc.). the plusw register can be used to implement a form of indexed addressing in the data memory space. by manipulating the value in the w register, users can reach addresses that are fixed offsets from pointer addresses. in some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. 6.6.3.3 operations by fsrs on fsrs indirect addressing operations that target other fsrs or virtual registers represent special cases. for example, using an fsr to point to one of the virtual registers will not result in successful operations. as a specific case, assume that fsr0h:fsr0l contains fe7h, the address of indf1. attempts to read the value of the indf1 using indf0 as an operand will return 00h. attempts to write to indf1 using indf0 as the operand will result in a nop . on the other hand, using the virtual registers to write to an fsr pair may not occur as planned. in these cases, the value will be written to the fsr pair but without any incrementing or decrementing. thus, writing to either the indf2 or postdec2 register will write the same value to the fsr2h:fsr2l. since the fsrs are physical registers mapped in the sfr space, they can be manipulated through all direct operations. users should proceed cautiously when working on these registers, particularly if their code uses indirect addressing. similarly, operations by indirect addressing are generally permitted on all other sfrs. users should exercise the appropriate caution that they do not inadvertently change settings that might affect the operation of the device. 6.7 data memory and the extended instruction set enabling the pic18 extended instruction set (xinst configuration bit = 1 ) significantly changes certain aspects of data memory and its addressing. specifi- cally, the use of the access bank for many of the core pic18 instructions is different; this is due to the intro- duction of a new addressing mode for the data memory space. what does not change is just as important. the size of the data memory space is unchanged, as well as its linear addressing. the sfr map remains the same. core pic18 instructions can still operate in both direct and indirect addressing mode; inherent and literal instructions do not change at all. indirect addressing with fsr0 and fsr1 also remain unchanged. 6.7.1 indexed addressing with literal offset enabling the pic18 extended instruction set changes the behavior of indirect addressing using the fsr2 register pair within access ram. under the proper conditions, instructions that use the access bank ? that is, most bit-oriented and byte-oriented instructions ? can invoke a form of indexed addressing using an offset specified in the instruction. this special addressing mode is known as indexed addressing with literal offset, or indexed literal offset mode. when using the extended instruction set, this addressing mode requires the following: ? the use of the access bank is forced (?a? = 0 ) and ? the file address argument is less than or equal to 5fh. under these conditions, the file address of the instruction is not interpreted as the lower byte of an address (used with the bsr in direct addressing), or as an 8-bit address in the access bank. instead, the value is interpreted as an offset value to an address pointer, specified by fsr2. the offset and the contents of fsr2 are added to obtain the target address of the operation. 6.7.2 instructions affected by indexed literal offset mode any of the core pic18 instructions that can use direct addressing are potentially affected by the indexed literal offset addressing mode. this includes all byte-oriented and bit-oriented instructions, or almost one-half of the standard pic18 instruction set. instructions that only use inherent or literal addressing modes are unaffected. additionally, byte-oriented and bit-oriented instructions are not affected if they do not use the access bank (access ram bit is ? 1 ?), or include a file address of 60h or above. instructions meeting these criteria will continue to execute as before. a comparison of the different possible addressing modes when the extended instruction set is enabled is shown in figure 6-8 . those who desire to use byte-oriented or bit-oriented instructions in the indexed literal offset mode should note the changes to assembler syntax for this mode. this is described in more detail in section 27.2.1 ?extended instruction syntax? . www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 97 pic18(l)f2x/45k50 figure 6-8: comparing addressing options for bit-oriented and byte-oriented instructions (extended instruction set enabled) example instruction: addwf, f, d, a (opcode: 0010 01da ffff ffff ) when ?a? = 0 and f ? 60h: the instruction executes in direct forced mode. ?f? is inter- preted as a location in the access ram between 060h and 0ffh. this is the same as locations f60h to fffh (bank 15) of data memory. locations below 60h are not available in this addressing mode. when ?a? = 0 and f ??? 5fh: the instruction executes in indexed literal offset mode. ?f? is interpreted as an offset to the address value in fsr2. the two are added together to obtain the address of the target register for the instruction. the address can be anywhere in the data memory space. note that in this mode, the correct syntax is now: addwf [k], d where ?k? is the same as ?f?. when ?a? = 1 (all values of f): the instruction executes in direct mode (also known as direct long mode). ?f? is inter- preted as a location in one of the 16 banks of the data memory space. the bank is designated by the bank select register (bsr). the address can be in any implemented bank in the data memory space. 000h 060h 100h f00h f60h fffh valid range 00h 60h ffh data memory access ram bank 0 bank 1 through bank 14 bank 15 sfrs 000h 060h 100h f00h f60h fffh data memory bank 0 bank 1 through bank 14 bank 15 sfrs fsr2h fsr2l ffffffff 001001da ffffffff 001001da 000h 060h 100h f00h f60h fffh data memory bank 0 bank 1 through bank 14 bank 15 sfrs for ?f? bsr 00000000 www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 98 ? 2012 microchip technology inc. 6.7.3 mapping the access bank in indexed literal offset mode the use of indexed literal offset addressing mode effectively changes how the first 96 locations of access ram (00h to 5fh) are mapped. rather than containing just the contents of the bottom section of bank 0, this mode maps the contents from a user defined ?window? that can be located anywhere in the data memory space. the value of fsr2 establishes the lower bound- ary of the addresses mapped into the window, while the upper boundary is defined by fsr2 plus 95 (5fh). addresses in the access ram above 5fh are mapped as previously described (see section 6.4.3 ?access bank? ). an example of access bank remapping in this addressing mode is shown in figure 6-9 . remapping of the access bank applies only to opera- tions using the indexed literal offset mode. operations that use the bsr (access ram bit is ? 1 ?) will continue to use direct addressing as before. 6.8 pic18 instruction execution and the extended instruction set enabling the extended instruction set adds eight additional commands to the existing pic18 instruction set. these instructions are executed as described in section 27.2 ?extended instruction set? . figure 6-9: remapping the access bank with indexed literal offset addressing data memory 000h 100h 200h f60h f00h fffh bank 1 bank 15 bank 2 through bank 14 sfrs addwf f, d, a fsr2h:fsr2l = 120h locations in the region from the fsr2 pointer (120h) to the pointer plus 05fh (17fh) are mapped to the bottom of the access ram (000h-05fh). special file registers at f60h through fffh are mapped to 60h through ffh, as usual. bank 0 addresses below 5fh can still be addressed by using the bsr. access bank 00h 60h ffh sfrs bank 1 ?window? bank 0 window example situation: 120h 17fh 5fh bank 1 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 99 pic18(l)f2x/45k50 7.0 flash program memory the flash program memory is readable, writable and erasable during normal operation over the specified v dd ranges. a read from program memory is executed one byte at a time. a write to program memory is executed on blocks of 64 bytes at a time. program memory is erased in blocks of 64 bytes at a time. a bulk erase operation cannot be issued from user code. writing or erasing program memory will cease instruction fetches until the operation is complete. the program memory cannot be accessed during the write or erase, therefore, code cannot execute. an internal programming timer terminates program memory writes and erases. a value written to program memory does not need to be a valid instruction. executing a program memory location that forms an invalid instruction results in a nop . 7.1 table reads and table writes in order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data ram: ? table read ( tblrd ) ? table write ( tblwt ) the program memory space is 16 bits wide, while the data ram space is 8 bits wide. table reads and table writes move data between these two memory spaces through an 8-bit register (tablat). the table read operation retrieves one byte of data directly from program memory and places it into the tablat register. figure 7-1 shows the operation of a table read. the table write operation stores one byte of data from the tablat register into a write block holding register. the procedure to write the contents of the holding registers into program memory is detailed in section 7.6 ?writing to flash program memory? . figure 7-2 shows the operation of a table write with program memory and data ram. table operations work with byte entities. tables containing data, rather than program instructions, are not required to be word aligned. therefore, a table can start and end at any byte address. if a table write is being used to write executable code into program memory, program instructions will need to be word aligned. figure 7-1: table read operation table pointer (1) table latch (8-bit) program memory tblptrh tblptrl tablat tblptru instruction: tblrd * note 1: table pointer register points to a byte in program memory. program memory (tblptr) www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 100 ? 2012 microchip technology inc. figure 7-2: table write operation 7.2 control registers several control registers are used in conjunction with the tblrd and tblwt instructions. these include the: ? eecon1 register ? eecon2 register ? tablat register ? tblptr registers 7.2.1 eecon1 and eecon2 registers the eecon1 register ( register 7-1 ) is the control register for memory accesses. the eecon2 register is not a physical register; it is used exclusively in the memory write and erase sequences. reading eecon2 will read all ? 0 ?s. the eepgd control bit determines if the access will be a program or data eeprom memory access. when eepgd is clear, any subsequent operations will operate on the data eeprom memory. when eepgd is set, any subsequent operations will operate on the program memory. the cfgs control bit determines if the access will be to the configuration/calibration registers or to program memory/data eeprom memory. when cfgs is set, subsequent operations will operate on configuration registers regardless of eepgd (see section 26.0 ?special features of the cpu? ). when cfgs is clear, memory selection access is determined by eepgd. the free bit allows the program memory erase operation. when free is set, an erase operation is initiated on the next wr command. when free is clear, only writes are enabled. the wren bit, when set, will allow a write operation. the wren bit is clear on power-up. the wrerr bit is set by hardware when the wr bit is set and cleared when the internal programming timer expires and the write operation is complete. the wr control bit initiates write operations. the wr bit cannot be cleared, only set, by firmware. the wr bit is cleared by hardware at the completion of the write operation. table pointer (1) table latch (8-bit) tblptrh tblptrl tablat program memory (tblptr ? 2012 microchip technology inc. ds30684a-page 101 pic18(l)f2x/45k50 7.3 register definitions: memory control register 7-1: eecon1: data eeprom control 1 register r/w-x r/w-x u-0 r/w-0 r/w-x r/w-0 r/s-0 r/s-0 eepgd cfgs ? free wrerr wren wr rd bit 7 bit 0 legend: r = readable bit w = writable bit s = bit can be set by software, but not cleared u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 eepgd: flash program or data eeprom memory select bit 1 = access flash program memory 0 = access data eeprom memory bit 6 cfgs: flash program/data eeprom or configuration select bit 1 = access configuration registers 0 = access flash program or data eeprom memory bit 5 unimplemented: read as ? 0 ? bit 4 free: flash row (block) erase enable bit 1 = erase the program memory block addressed by tblptr on the next wr command (cleared by completion of erase operation) 0 = perform write-only bit 3 wrerr: flash program/data eeprom error flag bit (1) 1 = a write operation is prematurely terminated (any reset during self-timed programming in normal operation, or an improper write attempt) 0 = the write operation completed bit 2 wren: flash program/data eeprom write enable bit 1 = allows write cycles to flash program/data eeprom 0 = inhibits write cycles to flash program/data eeprom bit 1 wr: write control bit 1 = initiates a data eeprom erase/write cycle or a program memory erase cycle or write cycle. (the operation is self-timed and the bit is cleared by hardware once write is complete. the wr bit can only be set (not cleared) by software.) 0 = write cycle to the eeprom is complete bit 0 rd: read control bit 1 = initiates an eeprom read (read takes one cycle. rd is cleared by hardware. the rd bit can only be set (not cleared) by software. rd bit cannot be set when eepgd = 1 or cfgs = 1 .) 0 = does not initiate an eeprom read note 1: when a wrerr occurs, the eepgd and cfgs bits are not cleared. this allows tracing of the error condition. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 102 ? 2012 microchip technology inc. 7.3.1 tablat ? table latch register the table latch (tablat) is an 8-bit register mapped into the sfr space. the table latch register is used to hold 8-bit data during data transfers between program memory and data ram. 7.3.2 tblptr ? table pointer register the table pointer (tblptr) register addresses a byte within the program memory. the tblptr is comprised of three sfr registers: table pointer upper byte, table pointer high byte and table pointer low byte (tblptru:tblptrh:tblptrl). these three regis- ters join to form a 22-bit wide pointer. the low-order 21 bits allow the device to address up to 2 mbytes of program memory space. the 22nd bit allows access to the device id, the user id and the configuration bits. the table pointer register, tblptr, is used by the tblrd and tblwt instructions. these instructions can update the tblptr in one of four ways based on the table operation. these operations on the tblptr affect only the low-order 21 bits. 7.3.3 table pointer boundaries tblptr is used in reads, writes and erases of the flash program memory. when a tblrd is executed, all 22 bits of the tblptr determine which byte is read from program memory directly into the tablat register. when a tblwt is executed the byte in the tablat register is written, not to flash memory but, to a holding register in preparation for a program memory write. the holding registers constitute a write block which varies depending on the device (see tab l e 7 - 1 ).the six lsbs of the tblptrl register determine which specific address within the holding register block is written to. the msbs of the table pointer have no effect during tblwt operations. when a program memory write is executed (wr = 1 ), the entire holding register block is written to the flash memory at the address determined by the msbs of the tblptr. the six lsbs are ignored during flash mem- ory writes. for more detail, see section 7.6 ?writing to flash program memory? . when an erase of program memory is executed, the 16 msbs of the table pointer register (tblptr<21:6>) point to the 64-byte block that will be erased. the least significant bits (tblptr<5:0>) are ignored. figure 7-3 describes the relevant boundaries of tblptr based on flash program memory operations. table 7-1: table pointer operations wi th tblrd and tblwt instructions figure 7-3: table pointer bo undaries based on operation example operation on table pointer tblrd* tblwt* tblptr is not modified tblrd*+ tblwt*+ tblptr is incremented after the read/write tblrd*- tblwt*- tblptr is decremented after the read/write tblrd+* tblwt+* tblptr is incremented before the read/write 21 16 15 87 0 table erase/write table write table read ? tblptr<21:0> tblptrl tblptrh tblptru tblptr ? 2012 microchip technology inc. ds30684a-page 103 pic18(l)f2x/45k50 7.4 reading the flash program memory the tblrd instruction retrieves data from program memory and places it into data ram. table reads from program memory are performed one byte at a time. tblptr points to a byte address in program space. executing tblrd places the byte pointed to into tablat. in addition, tblptr can be modified automatically for the next table read operation. the internal program memory is typically organized by words. the least significant bit of the address selects between the high and low bytes of the word. figure 7-4 shows the interface between the internal program memory and the tablat. figure 7-4: reads from flash program memory example 7-1: reading a flash program memory word (even byte address) program memory (odd byte address) tblrd tablat tblptr = xxxxx1 fetch instruction register (ir) read register tblptr = xxxxx0 movlw code_addr_upper ; load tblptr with the base movwf tblptru ; address of the word movlw code_addr_high movwf tblptrh movlw code_addr_low movwf tblptrl read_word tblrd*+ ; read into tablat and increment movf tablat, w ; get data movwf word_even tblrd*+ ; read into tablat and increment movfw tablat, w ; get data movf word_odd www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 104 ? 2012 microchip technology inc. 7.5 erasing flash program memory the minimum erase block is 32 words or 64 bytes. only through the use of an external programmer, or through icsp? control, can larger blocks of program memory be bulk erased. word erase in the flash array is not supported. when initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased. the most significant 16 bits of the tblptr<21:6> point to the block being erased. the tblptr<5:0> bits are ignored. the eecon1 register commands the erase operation. the eepgd bit must be set to point to the flash program memory. the wren bit must be set to enable write operations. the free bit is set to select an erase operation. the write initiate sequence for eecon2, shown as steps 4 through 6 in section 7.5.1 ?flash program memory erase sequence? , is used to guard against accidental writes. this is sometimes referred to as a long write. a long write is necessary for erasing the internal flash. instruction execution is halted during the long write cycle. the long write is terminated by the internal programming timer. 7.5.1 flash program memory erase sequence the sequence of events for erasing a block of internal program memory is: 1. load table pointer register with address of block being erased. 2. set the eecon1 register for the erase operation: ? set eepgd bit to point to program memory; ? clear the cfgs bit to access program memory; ? set wren bit to enable writes; ? set free bit to enable the erase. 3. disable interrupts. 4. write 55h to eecon2. 5. write 0aah to eecon2. 6. set the wr bit. this will begin the block erase cycle. 7. the cpu will stall for duration of the erase (about 2 ms using internal timer). 8. re-enable interrupts. example 7-2: erasing a flash program memory block movlw code_addr_upper ; load tblptr with the base movwf tblptru ; address of the memory block movlw code_addr_high movwf tblptrh movlw code_addr_low movwf tblptrl erase_block bsf eecon1, eepgd ; point to flash program memory bcf eecon1, cfgs ; access flash program memory bsf eecon1, wren ; enable write to memory bsf eecon1, free ; enable block erase operation bcf intcon, gie ; disable interrupts required movlw 55h sequence movwf eecon2 ; write 55h movlw 0aah movwf eecon2 ; write 0aah bsf eecon1, wr ; start erase (cpu stall) bsf intcon, gie ; re-enable interrupts www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 105 pic18(l)f2x/45k50 7.6 writing to flash program memory the programming block size is 64 bytes. word or byte programming is not supported. table writes are used internally to load the holding registers needed to program the flash memory. there are only as many holding registers as there are bytes in a write block (64 bytes). since the table latch (tablat) is only a single byte, the tblwt instruction needs to be executed 64 times for each programming operation. all of the table write operations will essentially be short writes because only the holding registers are written. after all the holding registers have been written, the programming operation of that block of memory is started by configuring the eecon1 register for a program memory write and performing the long write sequence. the long write is necessary for programming the internal flash. instruction execution is halted during a long write cycle. the long write will be terminated by the internal programming timer. the eeprom on-chip timer controls the write time. the write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. figure 7-5: table writes to flash program memory 7.6.1 flash program memory write sequence the sequence of events for programming an internal program memory location should be: 1. read 64 bytes into ram. 2. update data values in ram as necessary. 3. load table pointer register with address being erased. 4. execute the block erase procedure. 5. load table pointer register with address of first byte being written. 6. write the 64-byte block into the holding registers with auto-increment (tblwt*+ or tblwt+*). 7. set the eecon1 register for the write operation: ? set eepgd bit to point to program memory; ? clear the cfgs bit to access program memory; ? set wren to enable writes. 8. disable interrupts. 9. write 55h to eecon2. 10. write 0aah to eecon2. 11. set the wr bit. this will begin the write cycle. 12. the cpu will stall for duration of the write (about 2 ms using internal timer). 13. re-enable interrupts. 14. verify the memory (table read). this procedure will require about 6 ms to update each write block of memory. an example of the required code is given in example 7-3 . note: the default value of the holding registers on device resets and after write operations is ffh. a write of ffh to a holding register does not modify that byte. this means that individual bytes of program memory may be modified, provided that the change does not attempt to change any bit from a ? 0 ? to a ? 1 ?. when modifying individual bytes, it is not necessary to load all holding registers before executing a long write operation. tablat tblptr = xxxxyy (1) tblptr = xxxx01 tblptr = xxxx00 write register tblptr = xxxx02 program memory holding register holding register holding register holding register 8 8 8 8 note 1: yy = 3fh for 64 byte write blocks. note: before setting the wr bit, the table pointer address needs to be within the intended address range of the bytes in the holding registers. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 106 ? 2012 microchip technology inc. example 7-3: writing to flash program memory movlw d'64? ; number of bytes in erase block movwf counter movlw buffer_addr_high ; point to buffer movwf fsr0h movlw buffer_addr_low movwf fsr0l movlw code_addr_upper ; load tblptr with the base movwf tblptru ; address of the memory block movlw code_addr_high movwf tblptrh movlw code_addr_low movwf tblptrl read_block tblrd*+ ; read into tablat, and inc movf tablat, w ; get data movwf postinc0 ; store data decfsz counter ; done? bra read_block ; repeat modify_word movlw buffer_addr_high ; point to buffer movwf fsr0h movlw buffer_addr_low movwf fsr0l movlw new_data_low ; update buffer word movwf postinc0 movlw new_data_high movwf indf0 erase_block movlw code_addr_upper ; load tblptr with the base movwf tblptru ; address of the memory block movlw code_addr_high movwf tblptrh movlw code_addr_low movwf tblptrl bsf eecon1, eepgd ; point to flash program memory bcf eecon1, cfgs ; access flash program memory bsf eecon1, wren ; enable write to memory bsf eecon1, free ; enable erase operation bcf intcon, gie ; disable interrupts movlw 55h required movwf eecon2 ; write 55h sequence movlw 0aah movwf eecon2 ; write 0aah bsf eecon1, wr ; start erase (cpu stall) bsf intcon, gie ; re-enable interrupts tblrd*- ; dummy read decrement movlw buffer_addr_high ; point to buffer movwf fsr0h movlw buffer_addr_low movwf fsr0l write_buffer_back movlw blocksize ; number of bytes in holding register movwf counter movlw d?64?/blocksize ; number of write blocks in 64 bytes movwf counter2 write_byte_to_hregs movf postinc0, w ; get low byte of buffer data movwf tablat ; present data to table latch tblwt+* ; write data, perform a short write ; to internal tblwt holding register. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 107 pic18(l)f2x/45k50 example 7-3: writing to flash program memory (continued) 7.6.2 write verify depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. this should be used in applications where excessive writes can stress bits near the specification limit. 7.6.3 unexpected termination of write operation if a write is terminated by an unplanned event, such as loss of power or an unexpected reset, the memory location just programmed should be verified and reprogrammed if needed. if the write operation is interrupted by a mclr reset or a wdt time-out reset during normal operation, the wrerr bit will be set which the user can check to decide whether a rewrite of the location(s) is needed. 7.6.4 protection against spurious writes to protect against spurious writes to flash program memory, the write initiate sequence must also be followed. see section 26.0 ?special features of the cpu? for more detail. 7.7 flash program operation during code protection see section 26.5 ?program verification and code protection? for details on code protection of flash program memory. decfsz counter ; loop until holding registers are full bra write_word_to_hregs program_memory bsf eecon1, eepgd ; point to flash program memory bcf eecon1, cfgs ; access flash program memory bsf eecon1, wren ; enable write to memory bcf intcon, gie ; disable interrupts movlw 55h required movwf eecon2 ; write 55h sequence movlw 0aah movwf eecon2 ; write 0aah bsf eecon1, wr ; start program (cpu stall) dcfsz counter2 ; repeat for remaining write blocks bra write_byte_to_hregs ; bsf intcon, gie ; re-enable interrupts bcf eecon1, wren ; disable write to memory table 7-2: registers associated with program flash memory name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page tblptru ? ? program memory table pointer upper byte (tblptr<21:16>) ? tbpltrh program memory table pointer high byte (tblptr<15:8>) ? tblptrl program memory table pointer low byte (tblptr<7:0>) ? tablat program memory table latch ? intcon gie/gieh peie/giel tmr0ie int0ie iocie tmr0if int0if iocif 120 eecon2 eeprom control register 2 (not a physical register) ? eecon1 eepgd cfgs ? free wrerr wren wr rd 101 ipr2 oscfip c1ip c2ip eeip bclip hlvdip tmr3ip ccp2ip 130 pir2 oscfif c1if c2if eeif bclif hlvdif tmr3if ccp2if 124 pie2 oscfie c1ie c2ie eeie bclie hlvdie tmr3ie ccp2ie 127 legend: ? = unimplemented, read as ? 0 ?. shaded bits are not used during flash/eeprom access. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 108 ? 2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 109 pic18(l)f2x/45k50 8.0 data eeprom memory the data eeprom is a nonvolatile memory array, separate from the data ram and program memory, which is used for long-term storage of program data. it is not directly mapped in either the register file or program memory space but is indirectly addressed through the special function registers (sfrs). the eeprom is readable and writable during normal operation over the specified v dd range. four sfrs are used to read and write to the data eeprom as well as the program memory. they are: ? eecon1 ? eecon2 ? eedata ? eeadr the data eeprom allows byte read and write. when interfacing to the data memory block, eedata holds the 8-bit data for read/write, and the eeadr register holds the address of the eeprom location being accessed. the eeprom data memory is rated for high erase/write cycle endurance. a byte write automatically erases the location and writes the new data (erase-before-write). the write time is controlled by an on-chip timer; it will vary with voltage and temperature as well as from chip- to-chip. please refer to the data eeprom memory parameters in section 29.0 ?electrical characteris- tics? for limits. 8.1 eeadr register the eeadr register is used to address the data eeprom for read and write operations. the 8-bit range of the register can address a memory range of 256 bytes (00h to ffh). 8.2 eecon1 and eecon2 registers access to the data eeprom is controlled by two registers: eecon1 and eecon2. these are the same registers which control access to the program memory and are used in a similar manner for the data eeprom. the eecon1 register ( register 8-1 ) is the control register for data and program memory access. control bit eepgd determines if the access will be to program or data eeprom memory. when the eepgd bit is clear, operations will access the data eeprom memory. when the eepgd bit is set, program memory is accessed. control bit, cfgs, determines if the access will be to the configuration registers or to program memory/data eeprom memory. when the cfgs bit is set, subsequent operations access configuration registers. when the cfgs bit is clear, the eepgd bit selects either program flash or data eeprom memory. the wren bit, when set, will allow a write operation. on power-up, the wren bit is clear. the wrerr bit is set by hardware when the wr bit is set and cleared when the internal programming timer expires and the write operation is complete. the wr control bit initiates write operations. the bit can be set but not cleared by software. it is cleared only by hardware at the completion of the write operation. control bits, rd and wr, start read and erase/write operations, respectively. these bits are set by firmware and cleared by hardware at the completion of the operation. the rd bit cannot be set when accessing program memory (eepgd = 1 ). program memory is read using table read instructions. see section 7.1 ?table reads and table writes? regarding table reads. the eecon2 register is not a physical register. it is used exclusively in the memory write and erase sequences. reading eecon2 will read all ? 0 ?s. note: during normal operation, the wrerr may read as ? 1 ?. this can indicate that a write operation was prematurely termi- nated by a reset, or a write operation was attempted improperly. note: the eeif interrupt flag bit of the pir2 register is set when the write is complete. it must be cleared by software. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 110 ? 2012 microchip technology inc. register 8-1: eecon1: data eeprom control 1 register r/w-x r/w-x u-0 r/w-0 r/w-x r/w-0 r/s-0 r/s-0 eepgd cfgs ? free wrerr wren wr rd bit 7 bit 0 legend: r = readable bit w = writable bit s = bit can be set by software, but not cleared u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 eepgd: flash program or data eeprom memory select bit 1 = access flash program memory 0 = access data eeprom memory bit 6 cfgs: flash program/data eeprom or configuration select bit 1 = access configuration registers 0 = access flash program or data eeprom memory bit 5 unimplemented: read as ? 0 ? bit 4 free: flash row (block) erase enable bit 1 = erase the program memory block addressed by tblptr on the next wr command (cleared by completion of erase operation) 0 = perform write-only bit 3 wrerr: flash program/data eeprom error flag bit (1) 1 = a write operation is prematurely terminated (any reset during self-timed programming in normal operation, or an improper write attempt) 0 = the write operation completed bit 2 wren: flash program/data eeprom write enable bit 1 = allows write cycles to flash program/data eeprom 0 = inhibits write cycles to flash program/data eeprom bit 1 wr: write control bit 1 = initiates a data eeprom erase/write cycle or a program memory erase cycle or write cycle. (the operation is self-timed and the bit is cleared by hardware once write is complete. the wr bit can only be set (not cleared) by software.) 0 = write cycle to the eeprom is complete bit 0 rd: read control bit 1 = initiates an eeprom read (read takes one cycle. rd is cleared by hardware. the rd bit can only be set (not cleared) by software. rd bit cannot be set when eepgd = 1 or cfgs = 1 .) 0 = does not initiate an eeprom read note 1: when a wrerr occurs, the eepgd and cfgs bits are not cleared. this allows tracing of the error condition. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 111 pic18(l)f2x/45k50 8.3 reading the data eeprom memory to read a data memory location, the user must write the address to the eeadr register, clear the eepgd con- trol bit of the eecon1 register and then set control bit, rd. the data is available on the very next instruction cycle; therefore, the eedata register can be read by the next instruction. eedata will hold this value until another read operation, or until it is written to by the user (during a write operation). the basic process is shown in example 8-1 . 8.4 writing to the data eeprom memory to write an eeprom data location, the address must first be written to the eeadr register and the data writ- ten to the eedata register. the sequence in example 8-2 must be followed to initiate the write cycle. the write will not begin if this sequence is not exactly followed (write 55h to eecon2, write 0aah to eecon2, then set wr bit) for each byte. it is strongly recommended that interrupts be disabled during this code segment. additionally, the wren bit in eecon1 must be set to enable writes. this mechanism prevents accidental writes to data eeprom due to unexpected code execution (i.e., runaway programs). the wren bit should be kept clear at all times, except when updating the eeprom. the wren bit is not cleared by hardware. after a write sequence has been initiated, eecon1, eeadr and eedata cannot be modified. the wr bit will be inhibited from being set unless the wren bit is set. both wr and wren cannot be set with the same instruction. at the completion of the write cycle, the wr bit is cleared by hardware and the eeprom interrupt flag bit, eeif, is set. the user may either enable this interrupt or poll this bit. eeif must be cleared by software. 8.5 write verify depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. this should be used in applications where excessive writes can stress bits near the specification limit. example 8-1: data eeprom read example 8-2: data eeprom write movlw data_ee_addr ; movwf eeadr ; data memory address to read bcf eecon1, eepgd ; point to data memory bcf eecon1, cfgs ; access eeprom bsf eecon1, rd ; eeprom read movf eedata, w ; w = eedata movlw data_ee_addr_low ; movwf eeadr ; data memory address to write movlw data_ee_addr_hi ; movwf eeadrh ; movlw data_ee_data ; movwf eedata ; data memory value to write bcf eecon1, eepgd ; point to data memory bcf eecon1, cfgs ; access eeprom bsf eecon1, wren ; enable writes bcf intcon, gie ; disable interrupts movlw 55h ; required movwf eecon2 ; write 55h sequence movlw 0aah ; movwf eecon2 ; write 0aah bsf eecon1, wr ; set wr bit to begin write bsf intcon, gie ; enable interrupts ; user code execution bcf eecon1, wren ; disable writes on write complete (eeif set) www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 112 ? 2012 microchip technology inc. 8.6 operation during code-protect data eeprom memory has its own code-protect bits in configuration words. external read and write operations are disabled if code protection is enabled. the microcontroller itself can both read and write to the internal data eeprom, regardless of the state of the code-protect configuration bit. refer to section 26.0 ?special features of the cpu? for additional information. 8.7 protection against spurious write there are conditions when the user may not want to write to the data eeprom memory. to protect against spurious eeprom writes, various mechanisms have been implemented. on power-up, the wren bit is cleared. in addition, writes to the eeprom are blocked during the power-up timer period (t pwrt ). the write initiate sequence and the wren bit together help prevent an accidental write during brown-out, power glitch or software malfunction. 8.8 using the data eeprom the data eeprom is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). when variables in one section change frequently, while variables in another section do not change, it is possible to exceed the total number of write cycles to the eeprom without exceeding the total number of write cycles to a single byte. refer to the data eeprom memory parameters in section 29.0 ?electrical characteristics? for write cycle limits. if this is the case, then an array refresh must be performed. for this reason, variables that change infrequently (such as constants, ids, calibration, etc.) should be stored in flash program memory. a simple data eeprom refresh routine is shown in example 8-3 . example 8-3: data eeprom refresh routine note: if data eeprom is only used to store constants and/or data that changes rarely, an array refresh is likely not required. see specification. clrf eeadr ; start at address 0 bcf eecon1, cfgs ; set for memory bcf eecon1, eepgd ; set for data eeprom bcf intcon, gie ; disable interrupts bsf eecon1, wren ; enable writes loop ; loop to refresh array bsf eecon1, rd ; read current address movlw 55h ; movwf eecon2 ; write 55h movlw 0aah ; movwf eecon2 ; write 0aah bsf eecon1, wr ; set wr bit to begin write btfsc eecon1, wr ; wait for write to complete bra $-2 incfsz eeadr, f ; increment address bra loop ; not zero, do it again bcf eecon1, wren ; disable writes bsf intcon, gie ; enable interrupts www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 113 pic18(l)f2x/45k50 table 8-1: registers associated with data eeprom memory name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie/gieh peie/giel tmr0ie int0ie iocie tmr0if int0if iocif 120 eeadr eeadr7 eeadr6 eeadr5 eeadr4 eeadr3 eeadr2 eeadr1 eeadr0 ? eedata eeprom data register ? eecon2 eeprom control register 2 (not a physical register) ? eecon1 eepgd cfgs ? free wrerr wren wr rd 110 ipr2 oscfip c1ip c2ip eeip bclip hlvdip tmr3ip ccp2ip 130 pir2 oscfif c1if c2if eeif bclif hlvdif tmr3if ccp2if 124 pie2 oscfie c1ie c2ie eeie bclie hlvdie tmr3ie ccp2ie 127 legend: ? = unimplemented, read as ? 0 ?. shaded bits are not used during eeprom access. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 114 ? 2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 115 pic18(l)f2x/45k50 9.0 8 x 8 hardware multiplier 9.1 introduction all pic18 devices include an 8 x 8 hardware multiplier as part of the alu. the multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, prodh:prodl. the multiplier?s operation does not affect any flags in the status register. making multiplication a hardware operation allows it to be completed in a single instruction cycle. this has the advantages of higher computational throughput and reduced code size for multiplication algorithms and allows the pic18 devices to be used in many applica- tions previously reserved for digital signal processors. a comparison of various hardware and software multiply operations, along with the savings in memory and execution time, is shown in tab l e 9 - 1 . 9.2 operation example 9-1 shows the instruction sequence for an 8 x 8 unsigned multiplication. only one instruction is required when one of the arguments is already loaded in the wreg register. example 9-2 shows the sequence to do an 8 x 8 signed multiplication. to account for the sign bits of the arguments, each argument?s most significant bit (msb) is tested and the appropriate subtractions are done. example 9-1: 8 x 8 unsigned multiply routine example 9-2: 8 x 8 signed multiply routine movf arg1, w ; mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl movf arg1, w mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl btfsc arg2, sb ; test sign bit subwf prodh, f ; prodh = prodh ; - arg1 movf arg2, w btfsc arg1, sb ; test sign bit subwf prodh, f ; prodh = prodh ; - arg2 table 9-1: performance comparison for various multiply operations routine multiply method program memory (words) cycles (max) time @ 48 mhz @ 40 mhz @ 10 mhz @ 4 mhz 8 x 8 unsigned without hardware multiply 13 69 5.7 ? s 6.9 ? s27.6 ? s69 ? s hardware multiply 1 1 83.3 ns 100 ns 400 ns 1 ? s 8 x 8 signed without hardware multiply 33 91 7.5 ? s9.1 ? s36.4 ? s91 ? s hardware multiply 6 6 500 ns 600 ns 2.4 ? s6 ? s 16 x 16 unsigned without hardware multiply 21 242 20.1 ? s24.2 ? s96.8 ? s242 ? s hardware multiply 28 28 2.3 ? s2.8 ? s11.2 ? s28 ? s 16 x 16 signed without hardware multiply 52 254 21.6 ? s25.4 ? s 102.6 ? s254 ? s hardware multiply 35 40 3.3 ? s4.0 ? s16.0 ? s40 ? s www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 116 ? 2012 microchip technology inc. example 9-3 shows the sequence to do a 16 x 16 unsigned multiplication. equation 9-1 shows the algorithm that is used. the 32-bit result is stored in four registers (res<3:0>). equation 9-1: 16 x 16 unsigned multiplication algorithm example 9-3: 16 x 16 unsigned multiply routine example 9-4 shows the sequence to do a 16 x 16 signed multiply. equation 9-2 shows the algorithm used. the 32-bit result is stored in four registers (res<3:0>). to account for the sign bits of the argu- ments, the msb for each argument pair is tested and the appropriate subtractions are done. equation 9-2: 16 x 16 signed multiplication algorithm example 9-4: 16 x 16 signed multiply routine res3:res0 = arg1h:arg1l ? arg2h:arg2l = (arg1h ? arg2h ? 2 16 ) + (arg1h ? arg2l ? 2 8 ) + (arg1l ? arg2h ? 2 8 ) + (arg1l ? arg2l) movf arg1l, w mulwf arg2l ; arg1l * arg2l-> ; prodh:prodl movff prodh, res1 ; movff prodl, res0 ; movf arg1h, w mulwf arg2h ; arg1h * arg2h-> ; prodh:prodl movff prodh, res3 ; movff prodl, res2 ; movf arg1l, w mulwf arg2h ; arg1l * arg2h-> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; movf arg1h, w ; mulwf arg2l ; arg1h * arg2l-> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; res3:res0 = arg1h:arg1l ? arg2h:arg2l = (arg1h ? arg2h ? 2 16 ) + (arg1h ? arg2l ? 2 8 ) + (arg1l ? arg2h ? 2 8 ) + (arg1l ? arg2l) + (-1 ? arg2h<7> ? arg1h:arg1l ? 2 16 ) + (-1 ? arg1h<7> ? arg2h:arg2l ? 2 16 ) movf arg1l, w mulwf arg2l ; arg1l * arg2l -> ; prodh:prodl movff prodh, res1 ; movff prodl, res0 ; movf arg1h, w mulwf arg2h ; arg1h * arg2h -> ; prodh:prodl movff prodh, res3 ; movff prodl, res2 ; movf arg1l, w mulwf arg2h ; arg1l * arg2h -> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; movf arg1h, w ; mulwf arg2l ; arg1h * arg2l -> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; btfss arg2h, 7 ; arg2h:arg2l neg? bra sign_arg1 ; no, check arg1 movf arg1l, w ; subwf res2 ; movf arg1h, w ; subwfb res3 sign_arg1 btfss arg1h, 7 ; arg1h:arg1l neg? bra cont_code ; no, done movf arg2l, w ; subwf res2 ; movf arg2h, w ; subwfb res3 cont_code : www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 117 pic18(l)f2x/45k50 10.0 interrupts the pic18(l)f2x/45k50 devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high or low priority level (int0 does not have a priority bit, it is always a high priority). the high priority interrupt vector is at 0008h and the low priority interrupt vector is at 0018h. a high priority interrupt event will interrupt a low priority interrupt that may be in progress. there are 13 registers used to control interrupt operation. these registers are: ? intcon, intcon2, intcon3 ? pir1, pir2, pir3 ? pie1, pie2, pie3 ? ipr1, ipr2, ipr3 ? rcon it is recommended that the microchip header files supplied with mplab ? ide be used for the symbolic bit names in these registers. this allows the assembler/ compiler to automatically take care of the placement of these bits within the specified register. in general, interrupt sources have three bits to control their operation. they are: ? flag bit to indicate that an interrupt event occurred ? enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set ? priority bit to select high priority or low priority 10.1 mid-range compatibility when the ipen bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with pic ? microcontroller mid-range devices. in compatibility mode, the interrupt priority bits of the iprx registers have no effect. the peie/giel bit of the intcon register is the global interrupt enable for the peripherals. the peie/giel bit disables only the peripheral interrupt sources and enables the peripheral interrupt sources when the gie/gieh bit is also set. the gie/gieh bit of the intcon register is the global interrupt enable which enables all non-peripheral interrupt sources and disables all interrupt sources, including the peripherals. all interrupts branch to address 0008h in compatibility mode. 10.2 interrupt priority the interrupt priority feature is enabled by setting the ipen bit of the rcon register. when interrupt priority is enabled the gie/gieh and peie/giel global inter- rupt enable bits of compatibility mode are replaced by the gieh high priority, and giel low priority, global interrupt enables. when set, the gieh bit of the intcon register enables all interrupts that have their associated iprx register or intconx register priority bit set (high priority). when clear, the gieh bit disables all interrupt sources including those selected as low pri- ority. when clear, the giel bit of the intcon register disables only the interrupts that have their associated priority bit cleared (low priority). when set, the giel bit enables the low priority sources when the gieh bit is also set. when the interrupt flag, enable bit and appropriate global interrupt enable (gie) bit are all set, the interrupt will vector immediately to address 0008h for high priority, or 0018h for low priority, depending on level of the interrupting source?s priority bit. individual interrupts can be disabled through their corresponding interrupt enable bits. 10.3 interrupt response when an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. the gie/gieh bit is the global interrupt enable when the ipen bit is cleared. when the ipen bit is set, enabling interrupt priority levels, the gieh bit is the high priority global interrupt enable and the giel bit is the low priority global interrupt enable. high priority interrupt sources can interrupt a low priority interrupt. low priority interrupts are not processed while high priority interrupts are in progress. the return address is pushed onto the stack and the pc is loaded with the interrupt vector address (0008h or 0018h). once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits in the intconx and pirx registers. the interrupt flag bits must be cleared by software before re-enabling interrupts to avoid repeating the same interrupt. the ?return from interrupt? instruction, retfie , exits the interrupt routine and sets the gie/gieh bit (gieh or giel if priority levels are used), which re-enables interrupts. for external interrupt events, such as the int pins or the portb interrupt-on-change, the interrupt latency will be three to four instruction cycles. the exact latency is the same for one-cycle or two-cycle instructions. individual interrupt flag bits are set, regardless of the status of their corresponding enable bits or the global interrupt enable bit. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 118 ? 2012 microchip technology inc. figure 10-1: pic18 interrupt logic note: do not use the movff instruction to modify any of the interrupt control registers while any interrupt is enabled. doing so may cause erratic microcontroller behavior. tmr0ie gieh/gie wake-up if in interrupt to cpu vector to location 0008h int2if int2ie int2ip int1if int1ie int1ip tmr0if tmr0ie tmr0ip iocif iocie iocip tmr0if tmr0ip int1if int1ie int1ip int2if int2ie int2ip iocif iocie iocip int0if int0ie giel/peie interrupt to cpu vector to location ipen ipen 0018h high priority interrupt generation low priority interrupt generation idle or sleep modes gieh/gie note 1: the iocif interrupt also requires the individual pin iocb enables. (1) (1) pir1<7:0> pie1<7:0> ipr1<7:0> pir2<7:0> pie2<7:0> ipr2<7:0> pir3<7:0> pie3<7:0> ipr3<7:0> pir1<7:0> pie1<7:0> ipr1<7:0> pir2<7:0> pie2<7:0> ipr2<7:0> pir3<7:0> pie3<7:0> ipr3<7:0> ipen giel/peie www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 119 pic18(l)f2x/45k50 10.4 intcon registers the intcon registers are readable and writable registers, which contain various enable, priority and flag bits. 10.5 pir registers the pir registers contain the individual flag bits for the peripheral interrupts. due to the number of peripheral interrupt sources, there are three peripheral interrupt request flag registers (pir1, pir2 and pir3). 10.6 pie registers the pie registers contain the individual enable bits for the peripheral interrupts. due to the number of peripheral interrupt sources, there are three peripheral interrupt enable registers (pie1, pie2 and pie3). when ipen = 0 , the peie/giel bit must be set to enable any of these peripheral interrupts. 10.7 ipr registers the ipr registers contain the individual priority bits for the peripheral interrupts. due to the number of peripheral interrupt sources, there are three peripheral interrupt priority registers (ipr1, ipr2 and ipr3). using the priority bits requires that the interrupt priority enable (ipen) bit be set. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 120 ? 2012 microchip technology inc. 10.8 register definitions: interrupt control register 10-1: intcon: interrupt control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie/gieh peie/giel tmr0ie int0ie iocie tmr0if int0if iocif bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 gie/gieh: global interrupt enable bit when ipen = 0 : 1 = enables all unmasked interrupts 0 = disables all interrupts including peripherals when ipen = 1 : 1 = enables all high priority interrupts 0 = disables all interrupts including low priority bit 6 peie/giel: peripheral interrupt enable bit when ipen = 0 : 1 = enables all unmask ed peripheral interrupts 0 = disables all peripheral interrupts when ipen = 1 : 1 = enables all low priority interrupts 0 = disables all low priority interrupts bit 5 tmr0ie: tmr0 overflow interrupt enable bit 1 = enables the tmr0 overflow interrupt 0 = disables the tmr0 overflow interrupt bit 4 int0ie: int0 external interrupt enable bit 1 = enables the int0 external interrupt 0 = disables the int0 external interrupt bit 3 iocie: interrupt-on-change (iocx) interrupt enable bit (2) 1 = enables the iocx port change interrupt 0 = disables the iocx port change interrupt bit 2 tmr0if: tmr0 overflow interrupt flag bit 1 = tmr0 register has overflowed (must be cleared by software) 0 = tmr0 register did not overflow bit 1 int0if: int0 external interrupt flag bit 1 = the int0 external interrupt oc curred (must be cleared by software) 0 = the int0 external interrupt did not occur bit 0 iocif: interrupt-on-change (iocx) interrupt flag bit (1) 1 = at least one of the ioc pins chang ed state (must be cleared by software) 0 = none of the ioc pins have changed state note 1: a mismatch condition will continue to set the iocif bit. reading portb/portc will end the mismatch condition and allow the bit to be cleared. 2: port change interrupts also require the individual pins iocbx/ioccx enables. note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 121 pic18(l)f2x/45k50 register 10-2: intcon2: in terrupt control 2 register r/w-1 r/w-1 r/w-1 r/w-1 u-0 r/w-1 u-0 r/w-1 rbpu intedg0 intedg1 intedg2 ?tmr0ip ?iocip bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 rbpu : portb pull-up enable bit 1 = all portb pull-ups are disabled 0 = portb pull-ups are enabled provided that the pin is an input and the corresponding wpub bit is set. bit 6 intedg0: external interrupt 0 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 5 intedg1: external interrupt 1 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 4 intedg2: external interrupt 2 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 3 unimplemented: read as ? 0 ? bit 2 tmr0ip: tmr0 overflow interrupt priority bit 1 =high priority 0 = low priority bit 1 unimplemented: read as ? 0 ? bit 0 iocip: port change interrupt priority bit 1 =high priority 0 = low priority note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 122 ? 2012 microchip technology inc. register 10-3: intcon3: in terrupt control 3 register r/w-1 r/w-1 u-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 int2ip int1ip ? int2ie int1ie ? int2if int1if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 int2ip: int2 external interrupt priority bit 1 = high priority 0 = low priority bit 6 int1ip: int1 external interrupt priority bit 1 = high priority 0 = low priority bit 5 unimplemented: read as ? 0 ? bit 4 int2ie: int2 external interrupt enable bit 1 = enables the int2 external interrupt 0 = disables the int2 external interrupt bit 3 int1ie: int1 external interrupt enable bit 1 = enables the int1 external interrupt 0 = disables the int1 external interrupt bit 2 unimplemented: read as ? 0 ? bit 1 int2if: int2 external interrupt flag bit 1 = the int2 external interrupt occurred (must be cleared by software) 0 = the int2 external interrupt did not occur bit 0 int1if: int1 external interrupt flag bit 1 = the int1 external interrupt occurred (must be cleared by software) 0 = the int1 external interrupt did not occur note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 123 pic18(l)f2x/45k50 register 10-4: pir1: peripheral interrupt request (flag) register 1 r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 actif adif rcif txif sspif ccp1if tmr2if tmr1if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 actif: active clock tuning interrupt flag bit 1 = an active clock tuning event generated an interrupt (must be cleared in software) 0 = no active clock tuning interrupt is pending bit 6 adif: a/d converter interrupt flag bit 1 = an a/d conversion completed (must be cleared by software) 0 = the a/d conversion is not complete or has not been started bit 5 rcif: eusart receive interrupt flag bit 1 = the eusart receive buffer, rcreg1, is full (cleared when rcreg1 is read) 0 = the eusart receive buffer is empty bit 4 txif: eusart transmit interrupt flag bit 1 = the eusart transmit buffer, txreg1, is empty (cleared when txreg1 is written) 0 = the eusart transmit buffer is full bit 3 sspif: master synchronous serial port interrupt flag bit 1 = the transmission/reception is complete (must be cleared by software) 0 = waiting to transmit/receive bit 2 ccp1if: ccp1 interrupt flag bit capture mode: 1 = a tmr1 register capture occurred (must be cleared by software) 0 = no tmr1 register capture occurred compare mode: 1 = a tmr1 register compare match occurred (must be cleared by software) 0 = no tmr1 register compare match occurred pwm mode: unused in this mode bit 1 tmr2if: tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared by software) 0 = no tmr2 to pr2 match occurred bit 0 tmr1if: tmr1 overflow interrupt flag bit 1 = tmr1 register overflowed (must be cleared by software) 0 = tmr1 register did not overflow note 1: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit, gie/ gieh of the intcon register. 2: user software should ensure the appro- priate interrupt flag bits are cleared prior to enabling an interrupt and after servic- ing that interrupt. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 124 ? 2012 microchip technology inc. register 10-5: pir2: peripheral interrupt request (flag) register 2 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 oscfif c1if c2if eeif bclif hlvdif tmr3if ccp2if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 oscfif: oscillator fail interrupt flag bit 1 = device oscillator failed, clock input has changed to hfintosc (must be cleared by software) 0 = device clock operating bit 6 c1if: comparator c1 interrupt flag bit 1 = comparator c1 output has changed (must be cleared by software) 0 = comparator c1 output has not changed bit 5 c2if: comparator c2 interrupt flag bit 1 = comparator c2 output has changed (must be cleared by software) 0 = comparator c2 output has not changed bit 4 eeif: data eeprom/flash write operation interrupt flag bit 1 = the write operation is complete (must be cleared by software) 0 = the write operation is not complete or has not been started bit 3 bclif: mssp bus collision interrupt flag bit 1 = a bus collision occurred (must be cleared by software) 0 = no bus collision occurred bit 2 hlvdif: low-voltage detect interrupt flag bit 1 = a low-voltage condition occurred (direction determined by the vdirmag bit of the hlvdcon register) 0 = a low-voltage condition has not occurred bit 1 tmr3if: tmr3 overflow interrupt flag bit 1 = tmr3 register overflowed (must be cleared by software) 0 = tmr3 register did not overflow bit 0 ccp2if: ccp2 interrupt flag bit capture mode: 1 = a tmr1 register capture occurred (must be cleared by software) 0 = no tmr1 register capture occurred compare mode: 1 = a tmr1 register compare match occurred (must be cleared by software) 0 = no tmr1 register compare match occurred pwm mode: unused in this mode. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 125 pic18(l)f2x/45k50 register 10-6: pir3: peripheral interrupt (flag) register 3 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ctmuif usbif tmr3gif tmr1gif bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 unimplemented: read as ? 0 ? bit 3 ctmuif: ctmu interrupt flag bit 1 = ctmu interrupt occurred (must be cleared in software) 0 = no ctmu interrupt occurred bit 2 usbif: usb interrupt flag bit 1 = usb requested an interrupt (must be cleared in software) 0 = no usb interrupt request bit 1 tmr3gif: tmr3 gate interrupt flag bit 1 = tmr gate interrupt occurred (must be cleared in software) 0 = no tmr gate occurred bit 0 tmr1gif: tmr1 gate interrupt flag bit 1 = tmr gate interrupt occurred (must be cleared in software) 0 = no tmr gate occurred www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 126 ? 2012 microchip technology inc. register 10-7: pie1: peripheral in terrupt enable (flag) register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 actie adie rcie txie sspie ccp1ie tmr2ie tmr1ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 actie: active clock tuning interrupt enable bit 1 = enables active clock tuning interrupt 0 = disables active clock tuning interrupt bit 6 adie: a/d converter interrupt enable bit 1 = enables the a/d interrupt 0 = disables the a/d interrupt bit 5 rcie: eusart receive interrupt enable bit 1 = enables the eusart receive interrupt 0 = disables the eusart receive interrupt bit 4 txie: eusart transmit interrupt enable bit 1 = enables the eusart transmit interrupt 0 = disables the eusart transmit interrupt bit 3 sspie: master synchronous serial port interrupt enable bit 1 = enables the mssp interrupt 0 = disables the mssp interrupt bit 2 ccp1ie: ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 1 tmr2ie: tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit 0 tmr1ie: tmr1 overflow interrupt enable bit 1 = enables the tmr1 overflow interrupt 0 = disables the tmr1 overflow interrupt www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 127 pic18(l)f2x/45k50 register 10-8: pie2: peripheral in terrupt enable (flag) register 2 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 oscfie c1ie c2ie eeie bclie hlvdie tmr3ie ccp2ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 oscfie: oscillator fail interrupt enable bit 1 = enabled 0 =disabled bit 6 c1ie: comparator c1 interrupt enable bit 1 = enabled 0 = disabled bit 5 c2ie: comparator c2 interrupt enable bit 1 = enabled 0 = disabled bit 4 eeie: data eeprom/flash write operation interrupt enable bit 1 = enabled 0 =disabled bit 3 bclie: mssp bus collision interrupt enable bit 1 = enabled 0 =disabled bit 2 hlvdie: low-voltage detect interrupt enable bit 1 = enabled 0 =disabled bit 1 tmr3ie: tmr3 overflow interrupt enable bit 1 = enabled 0 =disabled bit 0 ccp2ie: ccp2 interrupt enable bit 1 = enabled 0 =disabled www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 128 ? 2012 microchip technology inc. register 10-9: pie3: peripheral in terrupt enable (flag) register 3 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ctmuie usbie tmr3gie tmr1gie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 unimplemented: read as ? 0 ? bit 3 ctmuie: ctmu interrupt enable bit 1 = enabled 0 =disabled bit 2 usbie: usb interrupt enable bit 1 = enabled 0 =disabled bit 1 tmr3gie: tmr3 gate interrupt enable bit 1 = enabled 0 =disabled bit 0 tmr1gie: tmr1 gate interrupt enable bit 1 = enabled 0 =disabled www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 129 pic18(l)f2x/45k50 register 10-10: ipr1: peripheral interrupt priority register 1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 actip adip rcip txip sspip ccp1ip tmr2ip tmr1ip bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 actip: active clock tuning interrupt priority bit 1 = high priority 0 = low priority bit 6 adip: a/d converter interrupt priority bit 1 = high priority 0 = low priority bit 5 rcip: eusart receive interrupt priority bit 1 = high priority 0 = low priority bit 4 txip: eusart transmit interrupt priority bit 1 = high priority 0 = low priority bit 3 sspip: master synchronous serial port interrupt priority bit 1 = high priority 0 = low priority bit 2 ccp1ip: ccp1 interrupt priority bit 1 = high priority 0 = low priority bit 1 tmr2ip: tmr2 to pr2 match interrupt priority bit 1 = high priority 0 = low priority bit 0 tmr1ip: tmr1 overflow interrupt priority bit 1 = high priority 0 = low priority www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 130 ? 2012 microchip technology inc. register 10-11: ipr2: peripheral interrupt priority register 2 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 oscfip c1ip c2ip eeip bclip hlvdip tmr3ip ccp2ip bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 oscfip: oscillator fail interrupt priority bit 1 = high priority 0 = low priority bit 6 c1ip: comparator c1 interrupt priority bit 1 = high priority 0 = low priority bit 5 c2ip: comparator c2 interrupt priority bit 1 = high priority 0 = low priority bit 4 eeip: data eeprom/flash write operation interrupt priority bit 1 = high priority 0 = low priority bit 3 bclip: mssp bus collision interrupt priority bit 1 = high priority 0 = low priority bit 2 hlvdip: low-voltage detect interrupt priority bit 1 = high priority 0 = low priority bit 1 tmr3ip: tmr3 overflow interrupt priority bit 1 = high priority 0 = low priority bit 0 ccp2ip: ccp2 interrupt priority bit 1 = high priority 0 = low priority www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 131 pic18(l)f2x/45k50 register 10-12: ipr3: peripheral interrupt priority register 3 u-0 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? ? ctmuip usbip tmr3gip tmr1gip bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 unimplemented: read as ? 0 ? bit 3 ctmuip: ctmu interrupt priority bit 1 = high priority 0 = low priority bit 2 usbip: usb interrupt priority bit 1 = high priority 0 = low priority bit 1 tmr3gip: tmr3 gate interrupt priority bit 1 = high priority 0 = low priority bit 0 tmr1gip: tmr1 gate interrupt priority bit 1 = high priority 0 = low priority www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 132 ? 2012 microchip technology inc. 10.9 intn pin interrupts external interrupts on the rb0/int0, rb1/int1 and rb2/int2 pins are edge-triggered. if the corresponding intedgx bit in the intcon2 register is set (= 1 ), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. when a valid edge appears on the rbx/intx pin, the corresponding flag bit, intxf, is set. this interrupt can be disabled by clearing the corresponding enable bit, intxe. flag bit, intxf, must be cleared by software in the interrupt service routine before re-enabling the interrupt. all external interrupts (int0, int1 and int2) can wake- up the processor from idle or sleep modes if bit intxe was set prior to going into those modes. if the global interrupt enable bit, gie/gieh, is set, the processor will branch to the interrupt vector following wake-up. interrupt priority for int1 and int2 is determined by the value contained in the interrupt priority bits, int1ip and int2ip of the intcon3 register. there is no prior- ity bit associated with int0. it is always a high priority interrupt source. 10.10 tmr0 interrupt in 8-bit mode (which is the default), an overflow in the tmr0 register (ffh ? 00h) will set flag bit, tmr0if. in 16-bit mode, an overflow in the tmr0h:tmr0l regis- ter pair (ffffh ?? 0000h) will set tmr0if. the interrupt can be enabled/disabled by setting/clearing enable bit, tmr0ie of the intcon register. interrupt priority for timer0 is determined by the value contained in the interrupt priority bit, tmr0ip of the intcon2 register. see section 12.0 ?timer0 module? for further details on the timer0 module. 10.11 portb/portc interrupt-on- change an input change on portb<7:4> or portc<2:0> sets flag bit, iocif of the intcon register. the interrupt can be enabled/disabled by setting/clearing enable bit, iocie of the intcon register. pins must also be individually enabled with the iocb/iocc register. interrupt priority for interrupt-on-change is determined by the value contained in the interrupt priority bit, iocip of the intcon2 register. 10.12 context saving during interrupts during interrupts, the return pc address is saved on the stack. additionally, the wreg, status and bsr registers are saved on the fast return stack. if a fast return from interrupt is not used (see section 6.2.2 ?fast register stack? ), the user may need to save the wreg, status and bsr registers on entry to the interrupt service routine. depending on the user?s application, other registers may also need to be saved. example 10-1 saves and restores the wreg, status and bsr registers during an interrupt service routine. example 10-1: saving status, wr eg and bsr registers in ram movwf w_temp ; w_temp is in virtual bank movff status, status_temp ; status_temp located anywhere movff bsr, bsr_temp ; bsr_tmep located anywhere ; ; user isr code ; movff bsr_temp, bsr ; restore bsr movf w_temp, w ; restore wreg movff status_temp, status ; restore status www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 133 pic18(l)f2x/45k50 table 10-1: registers associated with interrupts name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page anselb ? ? ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 155 intcon gie/gieh peie/giel tmr0ie int0ie iocie tmr0if int0if iocif 120 intcon2 r bpu intedg0 intedg1 intedg2 ?tmr0ip ?iocip 121 intcon3 int2ip int1ip ? int2ie int1ie ? int2if int1if 122 iocb iocb7 iocb6 iocb5 iocb4 ? ? ? ? 158 iocc iocc7 iocc6 iocc5 iocc4 ? iocc2 iocc1 iocc0 158 ipr1 actip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 129 ipr2 oscfip c1ip c2ip eeip bclip hlvdip tmr3ip ccp2ip 130 ipr3 ? ? ? ? ctmuip usbip tmr3gip tmr1gip 131 pie1 actie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 126 pie2 oscfie c1ie c2ie eeie bclie hlvdie tmr3ie ccp2ie 127 pie3 ? ? ? ? ctmuie usbie tmr3gie tmr1gie 128 pir1 actif adif rcif txif sspif ccp1if tmr2if tmr1if 123 pir2 oscfif c1if c2if eeif bclif hlvdif tmr3if ccp2if 124 pir3 ? ? ? ? ctmuif usbif tmr3gif tmr1gif 125 portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 153 rcon ipen sboren ? r i t o p d p or b or 68 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used for interrupts. table 10-2: configuration registers associated with interrupts name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page config3h mclre sdomx ? t3cmx ? ? pbaden ccp2mx 391 config4l debug xinst icprt ? ? lvp ? strven 392 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used for interrupts. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 134 ? 2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 135 pic18(l)f2x/45k50 11.0 i/o ports depending on the device selected and features enabled, there are up to five ports available. all pins of the i/o ports are multiplexed with one or more alternate functions from the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. each port has five registers for its operation. these registers are: ? tris register (data direction register) ? port register (reads the levels on the pins of the device) ? lat register (output latch) ? ansel register (analog input control) ? slrcon register (port slew rate control) the data latch (lat register) is useful for read-modify- write operations on the value that the i/o pins are driving. a simplified model of a generic i/o port, without the interfaces to other peripherals, is shown in figure 11-1 . figure 11-1: generic i/o port operation 11.1 porta registers porta is an 8-bit wide, bidirectional port. the corresponding data direction register is trisa. setting a trisa bit (= 1 ) will make the corresponding porta pin an input (i.e., disable the output driver). clearing a trisa bit (= 0 ) will make the corresponding porta pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). reading the porta register reads the status of the pins, whereas writing to it, will write to the port latch. the data latch (lata) register is also memory mapped. read-modify-write operations on the lata register read and write the latched output value for porta. the ra4 pin is multiplexed with the timer0 module clock input and one of the comparator outputs to become the ra4/t0cki/c1out pin. pins ra6 and ra7 are multiplexed with the main oscillator pins; they are enabled as oscillator or i/o pins by the selection of the main oscillator in the configuration register (see section 26.1 ?configuration bits? for details). when they are not used as port pins, ra6 and ra7 and their associated tris and lat bits are read as ? 0 ?. the other porta pins are multiplexed with analog inputs, the analog v ref + and v ref - inputs, and the comparator voltage reference output. the operation of pins ra<3:0> and ra5 as analog is selected by setting the ansela<5, 3:0> bits in the ansela register which is the default setting after a power-on reset. pins ra0 through ra5 may also be used as comparator inputs or outputs by setting the appropriate bits in the cm1con0 and cm2con0 registers. the ra4/t0cki/c1out pin is a schmitt trigger input. all other porta pins have ttl input levels and full cmos output drivers. the trisa register controls the drivers of the porta pins, even when they are being used as analog inputs. the user should ensure the bits in the trisa register are maintained set when using them as analog inputs. example 11-1: initializing porta data bus wr lat wr tris rd port data latch tris latch rd tris input buffer i/o pin (1) q d ck q d ck en qd en rd lat or port note 1: i/o pins have diode protection to v dd and v ss . trisx anselx note: on a power-on reset, ra5 and ra<3:0> are configured as analog inputs and read as ? 0 ?. ra4 is configured as a digital input. movlb 0xf ; set bsr for banked sfrs clrf lata ; initialize porta by ; clearing output ; data latches clrf ansela ; configure i/o ; for digital inputs movlw 0cfh ; value used to ; initialize data ; direction movwf trisa ; set ra<3:0> as inputs ; ra<5:4> as outputs www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 136 ? 2012 microchip technology inc. table 11-1: porta i/o summary pin name function tris setting ansel setting pin ty pe buffer type description ra0/c12in0-/an0 ra0 0x o dig lata<0> data output; not affected by analog input. 10 i ttl porta<0> data input; disabled when analog input enabled. c12in0- 11 i an comparators c1 and c2 inverting input. an0 11 i an analog input 0. ra1/c12in1-/an1 ra1 0x o dig lata<1> data output; not affected by analog input. 10 i ttl porta<1> data input; disabled when analog input enabled. c12in1- 11 i an comparators c1 and c2 inverting input. an1 11 i an analog input 1. ra2/c2in+/an2/ dacout/v ref - ra2 0x o dig lata<2> data output; not affected by analog input; disabled when dacout enabled. 10 i ttl porta<2> data input; disabled when analog input enabled; disabled when dacout enabled. c2in+ 11 i an comparator c2 non-inverting input. an2 11 i an analog output 2. dacout x1 o an dac reference output. v ref - 11 i an a/d reference voltage (low) input. ra3/c1in+/an3/ v ref + ra3 0x o dig lata<3> data output; not affected by analog input. 10 i ttl porta<3> data input; disabled when analog input enabled. c1in+ 11 i an comparator c1 non-inverting input. an3 11 i an analog input 3. v ref + 11 i an a/d reference voltage (high) input. ra4/c1out/srq/ t0cki ra4 0 ? o dig lata<4> data output. 1 ? i st porta<4> data input; default configuration on por. c1out 0 ? o dig comparator c1 output. srq 0 ? o dig sr latch q output; take priority over ccp 5 output. t0cki 1 ? i st timer0 external clock input. ra5/c2out/ srnq/ss1 / hlvdin/an4 ra5 0x o dig lata<5> data output; not affected by analog input. 10 i ttl porta<5> data input; disabled when analog input enabled. c2out 00 o dig comparator c2 output. srnq 00 o dig sr latch q output. ss1 10 i ttl spi slave select input (mssp). hlvdin 11 i an high/low-voltage detect input. an4 11 i an a/d input 4. ra6/clko/osc2 ra6 0 ? o dig lata<6> data output; enabled in intosc modes when clko is not enabled. 1 ? i ttl porta<6> data input; enabled in intosc modes when clko is not enabled. clko x ? o dig in rc mode, osc2 pin outputs clko which has 1/4 the fre- quency of osc1 and denotes the instruction cycle rate. osc2 x ? o xtal oscillator crystal output; connects to crystal or resonator in crystal oscillator mode. legend: an = analog input or output; ttl = ttl compatible input; hv = high voltage; od = open drain; xtal = crystal; cmos = cmos compatible input or output; st = schmitt trigger input with cmos levels; i 2 c tm = schmitt trigger input with i 2 c. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 137 pic18(l)f2x/45k50 ra7/clki/osc1 ra7 0 ? o dig lata<7> data output; disabled in external oscillator modes. 1 ? i ttl porta<7> data input; disabled in external oscillator modes. clki x ? i an external clock source input; always associated with pin function osc1. osc1 x ? i xtal oscillator crystal input or external clock source input st buffer when configured in rc mode; cmos otherwise. table 11-1: porta i/o summary (continued) pin name function tris setting ansel setting pin ty pe buffer type description legend: an = analog input or output; ttl = ttl compatible input; hv = high voltage; od = open drain; xtal = crystal; cmos = cmos compatible input or output; st = schmitt trigger input with cmos levels; i 2 c tm = schmitt trigger input with i 2 c. table 11-2: registers associated with porta name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ansela ? ? ansa5 ? ansa3 ansa2 ansa1 ansa0 154 cm1con0 c1on c1out c1oe c1pol c1sp c1r c1ch<1:0> 319 cm2con0 c2on c2out c2oe c2pol c2sp c2r c2ch<1:0> 319 vrefcon1 dacen daclps dacoe ? dacpss<1:0> ? dacnss 349 vrefcon2 ? ? ? dacr<4:0> 350 hlvdcon vdirmag bgvst irvst hlvden hlvdl<3:0> 379 porta ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 153 lata lata7 lata6 lata5 lata4 lata3 lata2 lata1 lata0 157 slrcon ? ? ? slre slrd slrc slrb slra 159 srcon0 srlen srclk<2:0> srqen srnqen srps srpr 342 ssp1con1 wcol sspov sspen ckp sspm<3:0> 262 t0con tmr0on t08bit t0cs t0se psa t0ps<2:0> 161 trisa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 156 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used for porta. table 11-3: configuration regist ers associated with porta name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page config1h ieso fcmen pclken ?fosc<3:0> 388 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used for porta. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 138 ? 2012 microchip technology inc. 11.1.1 porta output priority each porta pin is multiplexed with other functions. the pins, their combined functions and their output priorities are briefly described here. for additional information, refer to the appropriate section in this data sheet. when multiple outputs are enabled, the actual pin control goes to the peripheral with the higher priority. table 11-4 lists the porta pin functions from the highest to the lowest priority. analog input functions, such as adc and comparator, are not shown in the priority lists. these inputs are active when the i/o pin is set for analog mode using the anselx registers. digital output functions may control the pin when it is in analog mode with the priority shown below. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 139 pic18(l)f2x/45k50 table 11-4: port pin function priority port bit port function priority by port pin porta portb portc portd (2) porte (2) 0 ra0 sda sosco rb0 rc0 rd0 re0 1 ra1 scl sosci sck ccp2 (3) re1 p1c (1) rd1 rb1 rc1 2 dacout ccp1 ra2 p1b (1) p1a rd2 re2 rb2 ctpls rc2 3ra3sdo (3) mclr ccp2 (4) rd3 v pp re3 rb3 4srqp1d (1) d- c1out rb4 rd4 ra4 5 srnq d+ p1b c2out rd5 ra5 rb5 6osc2pgctx/ck clko icdck p1c ra6 rb6 rd6 rc6 7osc1pgdrx/dt ra7 icddt p1d rb7 rc7 rd7 note 1: pic18(l)f2xk50 devices. 2: pic18(l)f45k50 devices. 3: function default pin. 4: function alternate pin. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 140 ? 2012 microchip technology inc. 11.2 portb registers portb is an 8-bit wide, bidirectional port. the corresponding data direction register is trisb. setting a trisb bit (= 1 ) will make the corresponding portb pin an input (i.e., disable the output driver). clearing a trisb bit (= 0 ) will make the corresponding portb pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). the data latch register (latb) is also memory mapped. read-modify-write operations on the latb register read and write the latched output value for portb. example 11-2: initializing portb 11.2.1 portb output priority each portb pin is multiplexed with other functions. the pins, their combined functions and their output priorities are briefly described here. for additional information, refer to the appropriate section in this data sheet. when multiple outputs are enabled, the actual pin control goes to the peripheral with the higher priority. table 11-4 lists the portb pin functions from the highest to the lowest priority. analog input functions, such as adc, comparator and sr latch inputs, are not shown in the priority lists. these inputs are active when the i/o pin is set for analog mode using the anselx registers. digital output functions may control the pin when it is in analog mode with the priority shown below. 11.3 additional portb pin functions portb pins rb<7:4> have an interrupt-on-change option. all portb pins have a weak pull-up option. 11.3.1 weak pull-ups each of the portb pins has an individually controlled weak internal pull-up. when set, each bit of the wpub register enables the corresponding pin pull-up. when cleared, the rbpu bit of the intcon2 register enables pull-ups on all pins which also have their corresponding wpub bit set. when set, the rbpu bit disables all weak pull-ups. the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are disabled on a power-on reset. 11.3.2 interrupt-on-change four of the portb pins (rb<7:4>) are individually configurable as interrupt-on-change pins. control bits in the iocb register enable (when set) or disable (when clear) the interrupt function for each pin. when set, the iocie bit of the intcon register enables interrupts on all pins which also have their corresponding iocb bit set. when clear, the iocie bit disables all interrupt-on-changes. only pins configured as inputs can cause this interrupt to occur (i.e., any rb<7:4> pin configured as an output is excluded from the interrupt-on-change comparison). for enabled interrupt-on-change pins, the values are compared with the old value latched on the last read of portb. the ?mismatch? outputs of the last read are or?d together to set the interrupt-on-change interrupt flag bit (iocif) in the intcon register. this interrupt can wake the device from the sleep mode, or any of the idle modes. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of portb to clear the mis- match condition (except when portb is the source or destination of a movff instruction). b) execute at least one instruction after reading or writing portb, then clear the flag bit, iocif. movlb 0xf ; set bsr for banked sfrs clrf latb ; initialize portb by ; clearing output ; data latches movlw 0f0h ; value for init movwf anselb ; enable rb<3:0> for ; digital input pins ; (not required if config bit ; pbaden is clear) movlw 0cfh ; value used to ; initialize data ; direction movwf trisb ; set rb<3:0> as inputs ; rb<5:4> as outputs ; rb<7:6> as inputs note: on a power-on reset, rb<5:0> are configured as analog inputs by default and read as ? 0 ?; rb<7:6> are configured as digital inputs. when the pbaden configuration bit is set to ? 0 ?, rb<5:0> will alternatively be configured as digital inputs on por. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 141 pic18(l)f2x/45k50 a mismatch condition will continue to set the iocif flag bit. reading or writing portb will end the mismatch condition and allow the iocif bit to be cleared. the latch holding the last read value is not affected by a mclr nor brown-out reset. after either one of these resets, the iocif flag will continue to be set if a mismatch is present. the interrupt-on-change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt-on-change feature. polling of portb is not recommended while using the interrupt-on-change feature. 11.3.3 alternate functions portb is multiplexed with several peripheral functions ( table 11-5 ). the pins have ttl input buffers. some of these pin functions can be relocated to alternate pins using the control fuse bits in config3h. rb3 is the default pin for sdo. clearing the sdomx bit moves the sdo pin function to rc7. two other pin functions, t3cki and ccp2, can be relocated from their default pins to portb pins by clearing the control fuses in config3h. clearing t3cmx and ccp2mx moves the pin functions to rb5 and rb3, respectively. note: if a change on the i/o pin should occur when the read operation is being executed (start of the q2 cycle), then the iocif interrupt flag may not get set. furthermore, since a read or write on a port affects all bits of that port, care must be taken when using multiple pins in interrupt-on-change mode. changes on one pin may not be seen while servicing changes on another pin. table 11-5: portb i/o summary pin function tris setting ansel setting pin type buffer type description rb0/int0/flt0 / sri/sda/sdi/an12 rb0 0x o dig latb<0> data output; not affected by analog input. 10 i ttl portb<0> data input; disabled when analog input enabled. int0 10 i st external interrupt 0. flt0 10 i st pwm fault input for eccp auto-shutdown. sri 10 i st sr latch input. sda 10 i/o i 2 ci 2 c tm data i/o (mssp). sdi 10 i st spi data in (mssp). an12 11 i an analog input 12. rb1/int1/p1c/ sck/scl/c12in3-/ an10 rb1 0x o dig latb<1> data output; not affected by analog input. 10 i ttl portb<1> data input; disabled when analog input enabled. int1 10 i st external interrupt 1. p1c (3) 00 o dig enhanced ccp1 pwm output 3. sck 00 o dig mssp spi clock output. 10 i st mssp spi clock input. scl 00 o dig mssp i 2 c tm clock output. 10 ii 2 c mssp i 2 c tm clock input. c12in3- 11 i an comparators c1 and c2 inverting input. an10 11 i an analog input 10. legend: an = analog input or output; ttl = ttl compatible input; hv = high voltage; od = open drain; xtal = crystal; cmos = cmos compatible input or output; st = schmitt trigger input with cmos levels; i 2 c tm = schmitt trigger input with i 2 c. note 1: default pin assignment for sdo when configuration bit sdomx is set. 2: alternate pin assignment for t3cki and ccp2 when configuration bits t3cmx and ccp2mx are clear. 3: function is on portd/porte for pic18(l)f45k50 devices. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 142 ? 2012 microchip technology inc. rb2/int2/cted1/ p1b/an8 rb2 0x o dig latb<2> data output; not affected by analog input. 10 i ttl portb<2> data input; disabled when analog input enabled. int2 10 i st external interrupt 2. cted1 10 i st ctmu edge 1 input. p1b (3) 00 o dig enhanced ccp1 pwm output 2. an8 11 i an analog input 8. rb3/cted2/ccp2/ sdo/c12in2-/an9 rb3 0x o dig latb<3> data output; not affected by analog input. 10 i ttl portb<3> data input; disabled when analog input enabled. cted2 10 i st ctmu edge 2 input. ccp2 (2) 00 o dig compare 2 output/pwm 2 output. 10 i st capture 2 input. sdo (1) 00 o dig mssp spi data output. c12in2- 11 i an comparators c1 and c2 inverting input. an9 11 i an analog input 9. rb4/iocb4/p1d/ an11 rb4 0x o dig latb<4> data output; not affected by analog input. 10 i ttl portb<4> data input; disabled when analog input enabled. iocb4 10 i ttl interrupt-on-change pin. p1d (3) 00 o dig enhanced ccp1 pwm output 4. an11 11 i an analog input 11. rb5/iocb5/t3cki/ t1g/an13 rb5 0x o dig latb<5> data output; not affected by analog input. 10 i ttl portb<5> data input; disabled when analog input enabled. iocb5 10 i ttl interrupt-on-change pin 1. t3cki (2) 10 i st timer3 clock input. t1g 10 i st timer1 external clock gate input. an13 11 i an analog input 13. rb6/iocb6/pgc rb6 0 ? o dig latb<6> data output; not affected by analog input. 1 ? i ttl portb<6> data input; disabled when analog input enabled. iocb6 1 ? i ttl interrupt-on-change pin. pgc x ? i st in-circuit debugger and icsp tm programming clock input. rb7/iocb7/pgd rb7 0 ? o dig latb<7> data output; not affected by analog input. 1 ? i ttl portb<7> data input; disabled when analog input enabled. iocb7 1 ? i ttl interrupt-on-change pin. pgd x ? o dig in-circuit debugger and icsp tm programming data output. x ? i st in-circuit debugger and icsp tm programming data input. table 11-5: portb i/o summary (continued) pin function tris setting ansel setting pin type buffer type description legend: an = analog input or output; ttl = ttl compatible input; hv = high voltage; od = open drain; xtal = crystal; cmos = cmos compatible input or output; st = schmitt trigger input with cmos levels; i 2 c tm = schmitt trigger input with i 2 c. note 1: default pin assignment for sdo when configuration bit sdomx is set. 2: alternate pin assignment for t3cki and ccp2 when configuration bits t3cmx and ccp2mx are clear. 3: function is on portd/porte for pic18(l)f45k50 devices. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 143 pic18(l)f2x/45k50 table 11-6: registers associated with portb name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page anselb ? ? ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 155 eccp1as eccp1ase eccp1as<2:0> pss1ac<1:0> pss1bd<1:0> 210 ccp1con p1m<1:0> dc1b<1:0> ccp1m<3:0> 206 ccp2con ? ? dc2b<1:0> ccp2m<3:0> 206 intcon gie/gieh peie/giel tmr0ie int0ie iocie tmr0if int0if iocif 120 intcon2 rbpu intedg0 intedg1 intedg2 ? tmr0ip ? iocip 121 intcon3 int2ip int1ip ? int2ie int1ie ? int2if int1if 122 iocb iocb7 iocb6 iocb5 iocb4 ? ? ? ? 158 latb latb7 latb6 latb5 latb4 latb3 latb2 latb1 latb0 157 portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 153 slrcon ? ? ? slre (1) slrd (1) slrc slrb slra 159 t1gcon tmr1ge t1gpol t1gtm t1gspm t1ggo/done t1gval t1gss<1:0> 175 t3con tmr3cs<1:0> t3ckps<1:0> soscen t3sync rd16 tmr3on 174 trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 156 wpub wpub7 wpub6 wpub5 wpub4 wpub3 wpub2 wpub1 wpub0 157 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used for portb. note 1: available on pic18(l)f45k50 devices only. table 11-7: configuration regist ers associated with portb name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page config3h mclre sdomx ?t3cmx ? ? pbaden ccp2mx 391 config4l debug xinst icprt ? ?lvp (1) ? strven 392 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used for portb. note 1: can only be changed when in high voltage programming mode. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 144 ? 2012 microchip technology inc. 11.4 portc registers portc is an 8-bit wide, bidirectional port. the corresponding data direction register is trisc. setting a trisc bit (= 1 ) will make the corresponding portc pin an input (i.e., disable the output driver). clearing a trisc bit (= 0 ) will make the corresponding portc pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). the data latch register (latc) is also memory mapped. read-modify-write operations on the latc register read and write the latched output value for portc. portc is multiplexed with several peripheral functions ( table 11-8 ). the pins have schmitt trigger input buf- fers. some of these pin functions can be relocated to alter- nate pins using the control fuse bits in config3h. rc0 is the default pin for t3cki. clearing the t3cmx bit moves the pin function to rb5. rc1 is the default pin for the ccp2 peripheral pin. clearing the ccp2mx bit moves the pin function to the rb3 pin. when enabling peripheral functions, care should be taken in defining tris bits for each portc pin. the eusart and mssp peripherals override the tris bit to make a pin an output or an input, depending on the peripheral configuration. refer to the corresponding peripheral section for additional information. the contents of the trisc register are affected by peripheral overrides. reading trisc always returns the current contents, even though a peripheral device may be overriding one or more of the pins. example 11-3: initializing portc 11.4.1 portc output priority each portc pin is multiplexed with other functions. the pins, their combined functions and their output priorities are briefly described here. for additional information, refer to the appropriate section in this data sheet. when multiple outputs are enabled, the actual pin control goes to the peripheral with the higher priority. table 11-4 lists the portc pin functions from the highest to the lowest priority. analog input functions, such as adc, comparator and sr latch inputs, are not shown in the priority lists. these inputs are active when the i/o pin is set for analog mode using the anselx registers. digital output functions may control the pin when it is in analog mode with the priority shown below. 11.4.2 interrupt-on-change all of the portc pins (rc<7:4> and rc<2:0>) are individually configurable as interrupt-on-change pins. control bits in the iocc register enable (when set) or disable (when clear) the interrupt function for each pin. see section 11.3.2 ?interrupt-on-change? for details on operation of interrupt-on-change. note: on a power-on reset, these pins are configured as analog inputs. movlb 0xf ; set bsr for banked sfrs clrf latc ; initialize portc by ; clearing output ; data latches movlw 0cfh ; value used to ; initialize data ; direction movwf trisc ; set rc<3:0> as inputs ; rc<5:4> as outputs ; rc<7:6> as inputs movlw 30h ; value used to ; enable digital inputs movwf anselc ; rc<3:2> dig input enable ; no ansel bits for rc<1:0> ; rc<7:6> dig input enable www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 145 pic18(l)f2x/45k50 table 11-8: portc i/o summary pin name function tris setting ansel setting pin type buffer type description rc0/iocc0/t3cki/ t3g/t1cki/sosco rc0 0 ? o dig latc<0> data output; not affected by analog input. 1 ? i st portc<0> data input; disabled when analog input enabled. iocc0 1 ? i ttl interrupt-on-change pin. t3cki (1) 1 ? i st timer3 clock input. t3g 1 ? i st timer3 external clock gate input. t1cki 1 ? i st timer1 clock input. sosco x ? o xtal secondary oscillator output. rc1/iocc1/ccp2/ sosci rc1 0 ? o dig latc<1> data output; not affected by analog input. 1 ? i st portc<1> data input; disabled when analog input enabled. iocc1 1 ? i ttl interrupt-on-change pin. ccp2 (1) 0 ? o dig compare 2 output/pwm 2 output. 1 ? i st capture 2 input. sosci x ? i xtal secondary oscillator input. rc2/ctpls/p1a/ ccp1/iocc2/an14 rc2 00 o dig latc<2> data output; not affected by analog input. 10 i st portc<2> data input; disabled when analog input enabled. ctpls 00 o dig ctmu pulse generator output. p1a 00 o dig enhanced ccp1 pwm output 1. ccp1 00 o dig compare 1 output/pwm 1 output. 10 i st capture 1 input. iocc2 1 ? i ttl interrupt-on-change pin. an14 11 i an analog input 14. d-/iocc4 d- ?? i xcvr usb bus differential minus line input. ?? o xcvr usb bus differential minus line output. iocc4 ?? i st interrupt-on-change pin. d+/iocc5 d+ ?? i xcvr usb bus differential minus line input. ?? o xcvr usb bus differential minus line output. iocc5 ?? i st interrupt-on-change pin. legend: an = analog input or output; ttl = ttl compatible input; hv = high voltage; od = open drain; xtal = crystal; cmos = cmos compatible input or output; st = schmitt trigger input with cmos levels; i 2 c tm = schmitt trigger input with i 2 c. note 1: default pin assignment for t3cki and ccp2 when configuration bits t3cmx and ccp2mx are set. 2: alternate pin assignment for sdo when configuration bit sdomx is clear. 3: function is on portd/porte for pic18(l)f45k50 devices. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 146 ? 2012 microchip technology inc. pin name function tris setting ansel setting pin type buffer type description rc6/iocc6/tx/ck/ an18 rc6 00 o dig latc<6> data output; not affected by analog input. 10 i st portc<6> data input; disabled when analog input enabled. iocc6 10 i ttl interrupt-on-change pin. tx 10 o dig eusart asynchronous transmit data output. ck 10 o dig eusart synchronous serial clock output. 10 i st eusart synchronous serial clock input. an18 11 i an analog input 18. rc7/iocc7/sdo/rx/ dt/an19 rc7 00 o dig latc<7> data output; not affected by analog input. 10 i st portc<7> data input; disabled when analog input enabled. iocc7 10 i ttl interrupt-on-change pin. sdo (2) 10 o dig alternate mssp spi data output. rx 10 i st eusart asynchronous receive data in. dt 10 o dig eusart synchronous serial data output. 10 i st eusart synchronous serial data input. an19 11 i an analog input 19. legend: an = analog input or output; ttl = ttl compatible input; hv = high voltage; od = open drain; xtal = crystal; cmos = cmos compatible input or output; st = schmitt trigger input with cmos levels; i 2 c tm = schmitt trigger input with i 2 c. note 1: default pin assignment for t3cki and ccp2 when configuration bits t3cmx and ccp2mx are set. 2: alternate pin assignment for sdo when configuration bit sdomx is clear. 3: function is on portd/porte for pic18(l)f45k50 devices. table 11-8: portc i/o summary (continued) www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 147 pic18(l)f2x/45k50 table 11-9: registers associated with portc name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page anselc ansc7 ansc6 ? ? ? ansc2 ? ? 155 eccp1as eccp1ase eccp1as<2:0> pss1ac<1:0> pss1bd<1:0> 210 ccp1con p1m<1:0> dc1b<1:0> ccp1m<3:0> 206 ccp2con ? ? dc2b<1:0> ccp2m<3:0> 206 ctmuconh ctmuen ? ctmusidl tgen edgen edgseqen idissen cttrig 335 latc latc7 latc6 ? ? ? latc2 latc1 latc0 157 portc rc7 rc6 ? ? ? rc2 rc1 rc0 153 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 280 slrcon ? ? ? slre (1) slrd (1) slrc slrb slra 159 ssp1con1 wcol sspov sspen ckp sspm<3:0> 262 t1con tmr1cs<1:0> t1ckps<1:0> soscen t1sync rd16 tmr1on 174 t3con tmr3cs<1:0> t3ckps<1:0> soscen t3sync rd16 tmr3on 174 t3gcon tmr3ge t3gpol t3gtm t3gspm t3ggo/done t3gval t3gss 175 trisc trisc7 trisc6 ? ? ? trisc2 trisc1 trisc0 156 txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 279 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used for portc. note 1: available on pic18(l)f45k50 devices only. table 11-10: configurat ion registers associated with portc name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page config3h mclre sdomx ? t3cmx ? ? pbaden ccp2mx 391 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used for portc. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 148 ? 2012 microchip technology inc. 11.5 portd registers portd is an 8-bit wide, bidirectional port. the corresponding data direction register is trisd. setting a trisd bit (= 1 ) will make the corresponding portd pin an input (i.e., disable the output driver). clearing a trisd bit (= 0 ) will make the corresponding portd pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). the data latch register (latd) is also memory mapped. read-modify-write operations on the latd register read and write the latched output value for portd. all pins on portd are implemented with schmitt trigger input buffers. each pin is individually configurable as an input or output. all of the portd pins are multiplexed with analog and digital peripheral modules. see table 11-11 . example 11-4: initializing portd 11.5.1 portd output priority each portd pin is multiplexed with other functions. the pins, their combined functions and their output priorities are briefly described here. for additional information, refer to the appropriate section in this data sheet. when multiple outputs are enabled, the actual pin control goes to the peripheral with the higher priority. table 11-4 lists the portd pin functions from the highest to the lowest priority. analog input functions, such as adc, comparator and sr latch inputs, are not shown in the priority lists. these inputs are active when the i/o pin is set for analog mode using the anselx registers. digital output functions may control the pin when it is in analog mode with the priority shown below. note: portd is only available on 40-pin and 44-pin devices. note: on a power-on reset, these pins are configured as analog inputs. movlb 0xf ; set bsr for banked sfrs clrf latd ; initialize portd by ; clearing output ; data latches movlw 0cfh ; value used to ; initialize data ; direction movwf trisd ; set rd<3:0> as inputs ; rd<5:4> as outputs ; rd<7:6> as inputs movlw 30h ; value used to ; enable digital inputs movwf anseld ; rd<3:0> dig input enable ; rc<7:6> dig input enable www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 149 pic18(l)f2x/45k50 table 11-11: portd i/o summary pin name function tris setting ansel setting pin type buffer type description rd0/an20 rd0 00 o dig latd<0> data output; not affected by analog input. 10 i st portd<0> data input; disabled when analog input enabled. an20 11 i an analog input 20. rd1/an21 rd1 00 o dig latd<1> data output; not affected by analog input. 10 i st portd<1> data input; disabled when analog input enabled. an21 11 i an analog input 21. rd2/an22 rd2 00 o dig latd<2> data output; not affected by analog input. 10 i st portd<2> data input; disabled when analog input enabled. an22 11 i an analog input 22. rd3/an23 rd3 00 o dig latd<3> data output; not affected by analog input. 10 i st portd<3> data input; disabled when analog input enabled. an23 11 i an analog input 23. rd4/an24 rd4 00 o dig latd<4> data output; not affected by analog input. 10 i st portd<4> data input; disabled when analog input enabled. an24 11 i an analog input 24. rd5/p1b/an25 rd5 00 o dig latd<5> data output; not affected by analog input. 10 i st portd<5> data input; disabled when analog input enabled. p1b 00 o dig enhanced ccp1 pwm output 2. an25 11 i an analog input 25. rd6/p1c/an26 rd6 00 o dig latd<6> data output; not affected by analog input. 10 i st portd<6> data input; disabled when analog input enabled. p1c 00 o dig enhanced ccp1 pwm output 3. an26 11 i an analog input 26. rd7/p1d/an27 rd7 00 o dig latd<7> data output; not affected by analog input. 10 i st portd<7> data input; disabled when analog input enabled. p1d 00 o dig enhanced ccp1 pwm output 4. an27 11 i an analog input 27. legend: an = analog input or output; ttl = ttl compatible input; hv = high voltage; od = open drain; xtal = crystal; cmos = cmos compatible input or output; st = schmitt trigger input with cmos levels; i 2 c tm = s chmitt trigger input with i 2 c. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 150 ? 2012 microchip technology inc. table 11-12: registers associated with portd name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page anseld (1) ansd7 ansd6 ansd5 ansd4 ansd3 ansd2 ansd1 ansd0 155 ccp1con p1m<1:0> dc1b<1:0> ccp1m<3:0> 206 latd (1) latd7 latd6 latd5 latd4 latd3 latd2 latd1 latd0 157 portd (1) rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 153 slrcon (1) ? ? ? slre slrd slrc slrb slra 159 ssp1con1 wcol sspov sspen ckp sspm<3:0> 262 trisd (1) trisd7 trisd6 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 156 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used for portd. note 1: available on pic18(l)f45k50 devices only. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 151 pic18(l)f2x/45k50 11.6 porte registers depending on the particular pic18(l)f2x/45k50 device selected, porte is implemented in two different ways. 11.6.1 porte on 40/44-pin devices for pic18(l)f2x/45k50 devices, porte is a 4-bit wide port. three pins (re0/an5, re1/an6 and re2/ an7) are individually configurable as inputs or outputs. these pins have schmitt trigger input buffers. when selected as an analog input, these pins will read as ? 0 ?s. the corresponding data direction register is trise. setting a trise bit (= 1 ) will make the corresponding porte pin an input (i.e., disable the output driver). clearing a trise bit (= 0 ) will make the corresponding porte pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). trise controls the direction of the rex pins, even when they are being used as analog inputs. the user must make sure to keep the pins configured as inputs when using them as analog inputs. the data latch register (late) is also memory mapped. read-modify-write operations on the late register read and write the latched output value for porte. the fourth pin of porte (mclr /v pp /re3) is an input- only pin. its operation is controlled by the mclre configuration bit. when selected as a port pin (mclre = 0 ), it functions as a digital input-only pin; as such, it does not have tris or lat bits associated with its operation. otherwise, it functions as the device?s master clear input. in either configuration, re3 also functions as the programming voltage input during programming. example 11-5: initializing porte 11.6.2 porte on 28-pin devices for pic18(l)f2xk50 devices, porte is only available when master clear functionality is disabled (mclr = 0 ). in these cases, porte is a single bit, input-only port comprised of re3 only. the pin oper- ates as previously described. 11.6.3 re3 weak pull-up the port re3 pin has an individually controlled weak internal pull-up. when set, the wpue3 (trise<7>) bit enables the re3 pin pull-up. the rbpu bit of the intcon2 register controls pull-ups on both portb and porte. when rbpu = 0 , the weak pull-ups become active on all pins which have the wpue3 or wpubx bits set. when set, the rbpu bit disables all weak pull-ups. the pull-ups are disabled on a power- on reset. when the re3 port pin is configured as mclr , (config3h<7>, mclre = 1 and config4l<2>, lvp = 0 ), or configured for low-volt- age programming, (mclre = x and lvp = 1 ), the pull- up is always enabled and the wpue3 bit has no effect. 11.6.4 porte output priority each porte pin is multiplexed with other functions. the pins, their combined functions and their output priorities are briefly described here. for additional information, refer to the appropriate section in this data sheet. when multiple outputs are enabled, the actual pin control goes to the peripheral with the higher priority. table 11-4 lists the porte pin functions from the highest to the lowest priority. analog input functions, such as adc, comparator and sr latch inputs, are not shown in the priority lists. these inputs are active when the i/o pin is set for analog mode using the anselx registers. digital output functions may control the pin when it is in analog mode with the priority shown below. note: on a power-on reset, re<2:0> are configured as analog inputs. note: on a power-on reset, re3 is enabled as a digital input-only if master clear functionality is disabled. clrf late ; initialize porte by ; clearing output ; data latches clrf ansele ; configure analog pins ; for digital only movlw 05h ; value used to ; initialize data ; direction movwf trise ; set re<0> as input ; re<1> as output ; re<2> as input www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 152 ? 2012 microchip technology inc. table 11-13: porte i/o summary pin function tris setting ansel setting pin type buffer type description re0/an5 re0 00 o dig late<0> data output; not affected by analog input. 10 i st porte<0> data input; disabled when analog input enabled. an5 11 i an analog input 5. re1/an6 re1 00 o dig late<1> data output; not affected by analog input. 10 i st porte<1> data input; disabled when analog input enabled. an6 11 i an analog input 6. re2/an7 re2 00 o dig late<2> data output; not affected by analog input. 10 i st porte<2> data input; disabled when analog input enabled. an7 11 i an analog input 7. re3/v pp /mclr re3 ? ? i st porte<3> data input; enabled when configuration bit mclre = 0 . v pp ? ? p an programming voltage input; always available mclr ?? i st active-low master clear (device reset) input; enabled when configuration bit mclre = 1 . legend: an = analog input or output; ttl = ttl compatible input; hv = high voltage; od = open drain; xtal = crystal; cmos = cmos compatible input or output; st = schmitt trigger input with cmos levels; i 2 c tm = schmitt trigger input with i 2 c. table 11-14: registers associated with porte name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ansele (1) ? ? ? ? ? anse2 anse1 anse0 156 intcon2 rbpu intedg0 intedg1 intedg2 ? tmr0ip ? iocip 121 late (1) ? ? ? ? ? late2 late1 late0 157 porte ? ? ? ?re3 re2 (1) re1 (1) re0 (1) 154 slrcon ? ? ?slre (1) slrd (1) slrc slrb slra 159 trise wpue3 ? ? ? ? trise2 (1) trise1 (1) trise0 (1) 156 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used for porte. note 1: available on pic18(l)f45k50 devices only. table 11-15: configurat ion registers associated with porte name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page config3h mclre sdomx ? t3cmx ? ? pbaden ccp2mx 391 config4l debug xinst ? ? ? lvp (1) ? strven 392 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used for interrupts. note 1: can only be changed when in high-voltage programming mode. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 153 pic18(l)f2x/45k50 11.7 port analog control most port pins are multiplexed with analog functions such as the analog-to-digital converter and comparators. when these i/o pins are to be used as analog inputs it is necessary to disable the digital input buffer to avoid excessive current caused by improper biasing of the digital input. individual control of the digital input buffers on pins which share analog functions is provided by the ansela, anselb, anselc, anseld and ansele registers. setting an ansx bit high will disable the associated digital input buffer and cause all reads of that pin to return ? 0 ? while allowing analog functions of that pin to operate correctly. the state of the ansx bits has no affect on digital output functions. a pin with the associated trisx bit clear and ansx bit set will still operate as a digital output but the input mode will be analog. this can cause unexpected behavior when performing read- modify-write operations on the affected port. all ansel register bits default to ? 1 ? upon por and bor, disabling digital inputs for their associated port pins. all tris register bits default to ? 1 ? upon por or bor, disabling digital outputs for their associated port pins. as a result, all port pins that have an ansel register will default to analog inputs upon por or bor. 11.8 port slew rate control the output slew rate of each port is programmable to select either the standard transition rate or a reduced transition rate of approximately 0.1 times the standard to minimize emi. the reduced transition time is the default slew rate for all ports. 11.9 register definitions ? port control register 11-1: portx (1) : portx register r/w-u/x r/w-u/x r/w-u/x r/w-u/x r/w-u/x r/w-u/x r/w-u/x r/w-u/x rx7 rx6 rx5 rx4 rx3 rx2 rx1 rx0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? ?1? = bit is set ?0? = bit is cleared x = bit is unknown -n/n = value at por and bor/value at all other resets bit 7-0 rx<7:0>: portx i/o bit values (2) note 1: register description for port a, portb, portc and portd. 2: writes to portx are written to corresponding latx register. reads from portx register is return of i/o pin values. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 154 ? 2012 microchip technology inc. register 11-2: porte: porte register u-0 u-0 u-0 u-0 r/w-u/x r/w-u/x r/w-u/x r/w-u/x ? ? ? ?re3 (1) re2 (2), (3) re1 (2), (3) re0 (2), (3) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? ?1? = bit is set ?0? = bit is cleared x = bit is unknown -n/n = value at por and bor/value at all other resets bit 7-4 unimplemented: read as ? 0 ? bit 3 re3: porte input bit value (1) bit 2-0 re<2:0>: porte i/o bit values (2), (3) note 1: port is available as input-only when mclre = 0 . 2: writes to portx are written to corresponding latx register. reads from portx register is return of i/o pin values. 3: available on pic18(l)f45k50 devices. register 11-3: ansela ? porta analog select register u-0 u-0 r/w-1 u-0 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ansa5 ? ansa3 ansa2 ansa1 ansa0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5 ansa5: ra5 analog select bit 1 = digital input buffer disabled 0 = digital input buffer enabled bit 4 unimplemented: read as ? 0 ? bit 3-0 ansa<3:0>: ra<3:0> analog select bit 1 = digital input buffer disabled 0 = digital input buffer enabled www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 155 pic18(l)f2x/45k50 register 11-4: anselb ? portb analog select register u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5-0 ansb<5:0>: rb<5:0> analog select bit 1 = digital input buffer disabled 0 = digital input buffer enabled register 11-5: anselc ? portc analog select register r/w-1 r/w-1 u-0 u-0 u-0 r/w-1 u-0 u-0 ansc7 ansc6 ? ? ? ansc2 ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 ansc<7:6>: rc<7:6> analog select bit 1 = digital input buffer disabled 0 = digital input buffer enabled bit 5-3 unimplemented: read as ? 0 ? bit 2 ansc<2>: rc<2> analog select bit 1 = digital input buffer disabled 0 = digital input buffer enabled bit 1-0 unimplemented: read as ? 0 ? register 11-6: anseld ? portd analog select register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ansd7 ansd6 ansd5 ansd4 ansd3 ansd2 ansd1 ansd0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 ansd<7:0>: rd<7:0> analog select bit 1 = digital input buffer disabled 0 = digital input buffer enabled www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 156 ? 2012 microchip technology inc. register 11-7: ansele ? porte analog select register u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 ? ? ? ? ? anse2 (1) anse1 (1) anse0 (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-3 unimplemented: read as ? 0 ? bit 2-0 anse<2:0>: re<2:0> analog select bit (1) 1 = digital input buffer disabled 0 = digital input buffer enabled note 1: available on pic18(l)f45k50 devices only. register 11-8: trisx: portx tri-state register (1) r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 trisx7 trisx6 trisx5 trisx4 trisx3 trisx2 trisx1 trisx0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 trisx<7:0>: portx tri-state control bit 1 = portx pin configured as an input (tri-stated) 0 = portx pin configured as an output note 1: register description for trisa, trisb, trisc and trisd. register 11-9: trise: porte tri-state register r/w-1 u-0 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 wpue3 ? ? ? ?trise2 (1) trise1 (1) trise0 (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 wpue3: weak pull-up register bits 1 = pull-up enabled on port pin 0 = pull-up disabled on port pin bit 6-3 unimplemented: read as ? 0 ? bit 2-0 trise<2:0>: porte tri-state control bit (1) 1 = porte pin configured as an input (tri-stated) 0 = porte pin configured as an output note 1: available on pic18(l)f45k50 devices only. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 157 pic18(l)f2x/45k50 register 11-10: latx: portx output latch register (1) r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u latx7 latx6 latx5 latx4 latx3 latx2 latx1 latx0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 latx<7:0>: portx output latch bit value (2) note 1: register description for lata, latb, latc and latd. 2: writes to porta are written to corresponding lata register. reads from porta register is return of i/o pin values. register 11-11: late: porte output latch register (1) u-0 u-0 u-0 u-0 u-0 r/w-x/u r/w-x/u r/w-x/u ? ? ? ? ? late2 late1 late0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-3 unimplemented: read as ? 0 ? bit 2-0 late<2:0>: porte output latch bit value (2) note 1: available on pic18(l)f45k50 devices only. 2: writes to porte are written to corresponding late register. reads from porte register is return of i/o pin values. register 11-12: wpub: weak pull-up portb register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 wpub7 wpub6 wpub5 wpub4 wpub3 wpub2 wpub1 wpub0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 wpub<7:0>: weak pull-up register bits 1 = pull-up enabled on portb pin 0 = pull-up disabled on portb pin www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 158 ? 2012 microchip technology inc. register 11-14: iocc: interrupt- on-change portc control register register 11-13: iocb: interrupt- on-change portb control register r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 iocb7 iocb6 iocb5 iocb4 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 iocb<7:4>: interrupt-on-change portb control bits 1 = interrupt-on-change enabled (1) 0 = interrupt-on-change disabled bit 3-0 unimplemented: read as ? 0 ? note 1: interrupt-on-change requires that the iocie bit (intcon<3>) is set. r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 iocc7 iocc6 iocc5 iocc4 ? iocc2 iocc1 iocc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 iocc<7:4>: interrupt-on-change portc control bits 1 = interrupt-on-change enabled (1) 0 = interrupt-on-change disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 iocc<2:0>: interrupt-on-change portc control bits 1 = interrupt-on-change enabled (1) 0 = interrupt-on-change disabled note 1: interrupt-on-change requires that the iocie bit (intcon<3>) is set. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 159 pic18(l)f2x/45k50 register 11-15: slrcon: sl ew rate control register u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ?slre ( 1 ) slrd ( 1 ) slrc slrb slra bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-5 unimplemented: read as ? 0 ? bit 4 slre: porte slew rate control bit (1) 1 = all outputs on porte slew at a limited rate 0 = all outputs on porte slew at the standard rate bit 3 slrd: portd slew rate control bit (1) 1 = all outputs on portd slew at a limited rate 0 = all outputs on portd slew at the standard rate bit 2 slrc: portc slew rate control bit 1 = all outputs on portc slew at a limited rate 0 = all outputs on portc slew at the standard rate bit 1 slrb: portb slew rate control bit 1 = all outputs on portb slew at a limited rate 0 = all outputs on portb slew at the standard rate bit 0 slra: porta slew rate control bit 1 = all outputs on porta slew at a limited rate (2) 0 = all outputs on porta slew at the standard rate note 1: these bits are available on pic18(l)f45k50 devices. 2: the slew rate of ra6 defaults to standard rate when the pin is used as clko. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 160 ? 2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 161 pic18(l)f2x/45k50 12.0 timer0 module the timer0 module incorporates the following features: ? software selectable operation as a timer or counter in both 8-bit or 16-bit modes ? readable and writable registers ? dedicated 8-bit, software programmable prescaler ? selectable clock source (internal or external) ? edge select for external clock ? interrupt-on-overflow the t0con register ( register 12-1 ) controls all aspects of the module?s operation, including the prescale selection. it is both readable and writable. a simplified block diagram of the timer0 module in 8-bit mode is shown in figure 12-1 . figure 12-2 shows a simplified block diagram of the timer0 module in 16-bit mode. 12.1 register definitions: timer0 control register 12-1: t0con: ti mer0 control register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 tmr0on t08bit t0cs t0se psa tops<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 tmr0on: timer0 on/off control bit 1 = enables timer0 0 = stops timer0 bit 6 t08bit : timer0 8-bit/16-bit control bit 1 = timer0 is configured as an 8-bit timer/counter 0 = timer0 is configured as a 16-bit timer/counter bit 5 t0cs : timer0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (f osc /4) bit 4 t0se : timer0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa : timer0 prescaler assignment bit 1 = timer0 prescaler is not assigned. timer0 clock input bypasses prescaler. 0 = timer0 prescaler is assigned. timer0 clock input comes from prescaler output. bit 2-0 t0ps<2:0> : timer0 prescaler select bits 111 = 1:256 prescale value 110 = 1:128 prescale value 101 = 1:64 prescale value 100 = 1:32 prescale value 011 = 1:16 prescale value 010 = 1:8 prescale value 001 = 1:4 prescale value 000 = 1:2 prescale value www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 162 ? 2012 microchip technology inc. 12.2 timer0 operation timer0 can operate as either a timer or a counter; the mode is selected with the t0cs bit of the t0con register. in timer mode (t0cs = 0 ), the module increments on every clock by default unless a different prescaler value is selected (see section 12.4 ?prescaler? ). timer0 incrementing is inhibited for two instruction cycles following a tmr0 register write. the user can work around this by adjusting the value written to the tmr0 register to compensate for the anticipated missing increments. the counter mode is selected by setting the t0cs bit (= 1 ). in this mode, timer0 increments either on every rising or falling edge of pin ra4/t0cki. the increment- ing edge is determined by the timer0 source edge select bit, t0se of the t0con register; clearing this bit selects the rising edge. restrictions on the external clock input are discussed below. an external clock source can be used to drive timer0; however, it must meet certain requirements (see table 29-12 ) to ensure that the external clock can be synchronized with the internal phase clock (t osc ). there is a delay between synchronization and the onset of incrementing the timer/counter. 12.3 timer0 reads and writes in 16-bit mode tmr0h is not the actual high byte of timer0 in 16-bit mode; it is actually a buffered version of the real high byte of timer0 which is neither directly readable nor writable (refer to figure 12-2 ). tmr0h is updated with the contents of the high byte of timer0 during a read of tmr0l. this provides the ability to read all 16 bits of timer0 without the need to verify that the read of the high and low byte were valid. invalid reads could otherwise occur due to a rollover between successive reads of the high and low byte. similarly, a write to the high byte of timer0 must also take place through the tmr0h buffer register. writing to tmr0h does not directly affect timer0. instead, the high byte of timer0 is updated with the contents of tmr0h when a write occurs to tmr0l. this allows all 16 bits of timer0 to be updated at once. figure 12-1: timer0 block diagram (8-bit mode) note: upon reset, timer0 is enabled in 8-bit mode with clock input from t0cki max. prescale. t0cki pin t0se 0 1 1 0 t0cs f osc /4 programmable prescaler sync with internal clocks tmr0l (2 t cy delay) internal data bus psa t0ps<2:0> set tmr0if on overflow 3 8 8 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 163 pic18(l)f2x/45k50 figure 12-2: timer0 block di agram (16-bit mode) 12.4 prescaler an 8-bit counter is available as a prescaler for the timer0 module. the prescaler is not directly readable or writable; its value is set by the psa and t0ps<2:0> bits of the t0con register which determine the prescaler assignment and prescale ratio. clearing the psa bit assigns the prescaler to the timer0 module. when the prescaler is assigned, prescale values from 1:2 through 1:256 in integer power-of-2 increments are selectable. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf tmr0 , movwf tmr0 , bsf tmr0 , etc.) clear the prescaler count. 12.4.1 switching prescaler assignment the prescaler assignment is fully under software control and can be changed ?on-the-fly? during program execution. 12.5 timer0 interrupt the tmr0 interrupt is generated when the tmr0 reg- ister overflows from ffh to 00h in 8-bit mode, or from ffffh to 0000h in 16-bit mode. this overflow sets the tmr0if flag bit. the interrupt can be masked by clear- ing the tmr0ie bit of the intcon register. before re-enabling the interrupt, the tmr0if bit must be cleared by software in the interrupt service routine. since timer0 is shut down in sleep mode, the tmr0 interrupt cannot awaken the processor from sleep. table 12-1: registers associated with timer0 note: upon reset, timer0 is enabled in 8-bit mode with clock input from t0cki max. prescale. t0cki pin t0se 0 1 1 0 t0cs f osc /4 programmable prescaler sync with internal clocks tmr0l (2 t cy delay) internal data bus 8 psa t0ps<2:0> set tmr0if on overflow 3 tmr0 tmr0h high byte 8 8 8 read tmr0l write tmr0l 8 note: writing to tmr0 when the prescaler is assigned to timer0 will clear the prescaler count but will not change the prescaler assignment. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie/gieh peie/giel tmr0ie int0ie iocie tmr0if int0if iocif 120 intcon2 rbpu intedg0 intedg1 intedg2 ?tmr0ip ? iocip 121 t0con tmr0on t08bit t0cs t0se psa t0ps<2:0> 161 tmr0h timer0 register, high byte ? tmr0l timer0 register, low byte ? trisa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 156 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used by timer0. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 164 ? 2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 165 pic18(l)f2x/45k50 13.0 timer1/3 module with gate control the timer1/3 module is a 16-bit timer/counter with the following features: ? 16-bit timer/counter register pair (tmrxh:tmrxl) ? programmable internal or external clock source ? 2-bit prescaler ? dedicated secondary 32 khz oscillator circuit ? optionally synchronized comparator out ? multiple timer1/3 gate (count enable) sources ? interrupt on overflow ? wake-up on overflow (external clock, asynchronous mode only) ? 16-bit read/write operation ? time base for the capture/compare function ? special event trigger (with ccp/eccp) ? selectable gate source polarity ? gate toggle mode ? gate single-pulse mode ? gate value status ? gate event interrupt figure 13-1 is a block diagram of the timer1/3 module. figure 13-1: timer1/3 block diagram tmrxh tmrxl txsync txckps<1:0> prescaler 1, 2, 4, 8 0 1 synchronized clock input 2 set flag bit tmrxif on overflow tmrx (2),(4) tmrxon note 1: st buffer is high speed type when using txcki. 2: timer1/3 register increments on rising edge. 3: synchronize does not operate while in sleep. 4: see figure 13-2 for 16-bit read/write mode block diagram. 5: t1cki is not available when the secondary oscillator is enabled. (soscgo = 1 or soscen = 1 ) 6: t3cki is not available when the secondary oscillator is enabled, unless t3cmx = 1 . 7: synchronized comparator output should not be used in conjunction with synchronized txcki. txg f osc /4 internal clock soscout 1 0 txcki tmrxcs<1:0> (5) synchronize (3),(7) det sleep input tmrxge 0 1 00 01 10 11 txgpol d q ck q 0 1 txgval txgtm single pulse acq. control txgspm txggo/done txgss<1:0> 10 11 00 01 f osc internal clock reserved r d en q q1 rd txgcon data bus det interrupt tmrxgif set txclk f osc /2 internal clock d en q txg_in tmrxon timer2 match pr2 sync_c2out (7) sync_c1out (7) to comparator module ,(6) soscen secondary oscillator module see figure 2-4 txclk_ext_src (1) www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 166 ? 2012 microchip technology inc. 13.1 timer1/3 operation the timer1/3 module is a 16-bit incrementing counter which is accessed through the tmrxh:tmrxl register pair. writes to tmrxh or tmrxl directly update the counter. when used with an internal clock source, the module is a timer and increments on every instruction cycle. when used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source. timer1/3 is enabled by configuring the tmrxon and tmrxge bits in the txcon and txgcon registers, respectively. table 13-1 displays the timer1/3 enable selections. 13.2 clock source selection the tmrxcs<1:0> and soscen bits of the txcon register are used to select the clock source for timer1/3. the dedicated secondary oscillator circuit can be used as the clock source for timer1 and timer3, simultaneously. any of the soscen bits will enable the secondary oscillator circuit and select it as the clock source for that particular timer. table 13-2 displays the clock source selections. 13.2.1 internal clock source when the internal clock source is selected the tmrxh:tmrxl register pair will increment on multiples of f osc as determined by the timer1/3 prescaler. when the f osc internal clock source is selected, the timer1/3 register value will increment by four counts every instruction clock cycle. due to this condition, a 2 lsb error in resolution will occur when reading the timer1/3 value. to utilize the full resolution of timer1/3, an asynchronous input signal must be used to gate the timer1/3 clock input. the following asynchronous sources may be used: ? asynchronous event on the txg pin to timer1/3 gate ? c1 or c2 comparator input to timer1/3 gate 13.2.2 external clock source when the external clock source is selected, the timer1/3 module may work as a timer or a counter. when enabled to count, timer1/3 is incremented on the rising edge of the external clock input of the txcki pin. this external clock source can be synchronized to the microcontroller system clock or it can run asynchronously. when used as a timer with a clock oscillator, an external 32.768 khz crystal can be used in conjunction with the dedicated secondary internal oscillator circuit. table 13-1: timer1/3 enable selections tmrxon tmrxge timer1/3 operation 00 off 01 off 10 always on 11 count enabled note: in counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: ? timer1/3 enabled after por ? write to tmrxh or tmrxl ? timer1/3 is disabled ? timer1/3 is disabled (tmrxon = 0 ) when txcki is high then timer1/3 is enabled (tmrxon= 1 ) when txcki is low. table 13-2: clock source selections tmrxcs1 tmrxcs0 soscen clock source 01x system clock (f osc ) 00x instruction clock (f osc /4) 100 external clocking on txcki pin 101 oscillator circuit on sosci/sosco pins www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 167 pic18(l)f2x/45k50 13.3 timer1/3 prescaler timer1/3 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. the txckps bits of the txcon register control the prescale counter. the prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to tmrxh or tmrxl. 13.4 secondary oscillator a dedicated secondary low-power 32.768 khz oscillator circuit is built-in between pins sosci (input) and sosco (amplifier output). this internal circuit is to be used in conjunction with an external 32.768 khz crystal. the oscillator circuit is enabled by setting the soscen bit of the txcon register, the soscgo bit of the osccon2 register or by selecting the secondary oscillator as the system clock by setting scs<1:0> = 01 in the osccon register. the oscillator will continue to run during sleep. 13.5 timer1/3 operation in asynchronous counter mode if control bit txsync of the txcon register is set, the external clock input is not synchronized. the timer increments asynchronously to the internal phase clocks. if external clock source is selected then the timer will continue to run during sleep and can generate an interrupt on overflow, which will wake-up the processor. however, special precautions in software are needed to read/write the timer (see section 13.5.1 ?reading and writing timer1/3 in asynchronous counter mode? ). 13.5.1 reading and writing timer1/3 in asynchronous counter mode reading tmrxh or tmrxl while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). however, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. for writes, it is recommended that the user simply stop the timer and write the desired values. a write contention may occur by writing to the timer registers, while the register is incrementing. this may produce an unpredictable value in the tmrxh:tmrxl register pair. 13.6 timer1/3 16-bit read/write mode timer1/3 can be configured to read and write all 16 bits of data, to and from, the 8-bit tmrxl and tmrxh reg- isters, simultaneously. the 16-bit read and write opera- tions are enabled by setting the rd16 bit of the txcon register. to accomplish this function, the tmrxh register value is mapped to a buffer register called the tmrxh buffer register. while in 16-bit mode, the tmrxh register is not directly readable or writable and all read and write operations take place through the use of this tmrxh buffer register. when a read from the tmrxl register is requested, the value of the tmrxh register is simultaneously loaded into the tmrxh buffer register. when a read from the tmrxh register is requested, the value is provided from the tmrxh buffer register instead. this provides the user with the ability to accurately read all 16 bits of the timer1/3 value from a single instance in time. in contrast, when not in 16-bit mode, the user must read each register separately and determine if the values have become invalid due to a rollover that may have occurred between the read operations. when a write request of the tmrxl register is requested, the tmrxh buffer register is simultaneously updated with the contents of the tmrxh register. the value of tmrxh must be preloaded into the tmrxh buffer register prior to the write request for the tmrxl register. this provides the user with the ability to write all 16 bits to the tmrxl:tmrxh register pair at the same time. any requests to write to the tmrxh directly does not clear the timer1/3 prescaler value. the prescaler value is only cleared through write requests to the tmrxl register. note: the oscillator requires a start-up and stabilization time before use. thus, soscen should be set and a suitable delay observed prior to enabling timer1/3. note: when switching from synchronous to asynchronous operation, it is possible to skip an increment. when switching from asynchronous to synchronous operation, it is possible to produce an additional increment. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 168 ? 2012 microchip technology inc. figure 13-2: timer1/3 16-bit read/write mode block diagram 13.7 timer1/3 gate timer1/3 can be configured to count freely or the count can be enabled and disabled using timer1/3 gate circuitry. this is also referred to as timer1/3 gate enable. timer1/3 gate can also be driven by multiple selectable sources. 13.7.1 timer1/3 gate enable the timer1/3 gate enable mode is enabled by setting the tmrxge bit of the txgcon register. the polarity of the timer1/3 gate enable mode is configured using the txgpol bit of the txgcon register. when timer1/3 gate enable mode is enabled, timer1/3 will increment on the rising edge of the timer1/3 clock source. when timer1/3 gate enable mode is disabled, no incrementing will occur and timer1/3 will hold the current count. see figure 13-4 for timing details. 13.7.2 timer1/3 gate source selection the timer1/3 gate source can be selected from one of four different sources. source selection is controlled by the txgss bits of the txgcon register. the polarity for each available source is also selectable. polarity selection is controlled by the txgpol bit of the txgcon register. 13.7.2.1 txg pin gate operation the txg pin is one source for timer1/3 gate control. it can be used to supply an external source to the timer1/3 gate circuitry. 13.7.2.2 timer2 match gate operation the tmr2 register will increment until it matches the value in the pr2 register. on the very next increment cycle, tmr2 will be reset to 00h. when this reset occurs, a low-to-high pulse will automatically be gener- ated and internally supplied to the timer1/3 gate circuitry. see section 13.7.2 ?timer1/3 gate source selection? for more information. 13.7.2.3 comparator c1 gate operation the output resulting from a comparator 1 operation can be selected as a source for timer1/3 gate control. the comparator 1 output (sync_c1out) can be synchronized to the timer1/3 clock or left asynchronous. for more information see section 19.8.4 ?synchronizing comparator output to timer1? . 13.7.2.4 comparator c2 gate operation the output resulting from a comparator 2 operation can be selected as a source for timer1/3 gate control. the comparator 2 output (sync_c2out) can be synchronized to the timer1/3 clock or left asynchronous. for more information see section 19.8.4 ?synchronizing comparator output to timer1? . table 13-3: timer1/3 gate enable selections txclk txgpol txg timer1/3 operation ? 00 counts ? 01 holds count ? 10 holds count ? 11 counts tmr1l internal data bus 8 set tmr1if on overflow tmr1 tmr1h high byte 8 8 8 read tmr1l write tmr1l 8 from timer1/3 circuitry table 13-4: timer1/3 gate sources txgss timer1/3 gate source 00 timer1/3 gate pin (txg) 01 timer2 match to pr2 (tmr2 increments to match pr2) 10 comparator 1 output sync_c1out (optionally timer1/3 synchronized output) 11 comparator 2 output sync_c2out (optionally timer1/3 synchronized output) www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 169 pic18(l)f2x/45k50 13.7.3 timer1/3 gate toggle mode when timer1/3 gate toggle mode is enabled, it is pos- sible to measure the full-cycle length of a timer1/3 gate signal, as opposed to the duration of a single level pulse. the timer1/3 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. see figure 13-5 for timing details. timer1/3 gate toggle mode is enabled by setting the txgtm bit of the txgcon register. when the txgtm bit is cleared, the flip-flop is cleared and held clear. this is necessary in order to control which edge is measured. 13.7.4 timer1/3 gate single-pulse mode when timer1/3 gate single-pulse mode is enabled, it is possible to capture a single-pulse gate event. timer1/3 gate single-pulse mode is first enabled by setting the txgspm bit in the txgcon register. next, the txggo/done bit in the txgcon register must be set. the timer1/3 will be fully enabled on the next incrementing edge. on the next trailing edge of the pulse, the txggo/done bit will automatically be cleared. no other gate events will be allowed to increment timer1/3 until the txggo/done bit is once again set in software. clearing the txgspm bit of the txgcon register will also clear the txggo/done bit. see figure 13-6 for timing details. enabling the toggle mode and the single-pulse mode simultaneously will permit both sections to work together. this allows the cycle times on the timer1/3 gate source to be measured. see figure 13-7 for timing details. 13.7.5 timer1/3 gate value status when timer1/3 gate value status is utilized, it is possible to read the most current level of the gate control value. the value is stored in the txgval bit in the txgcon register. the txgval bit is valid even when the timer1/3 gate is not enabled (tmrxge bit is cleared). 13.7.6 timer1/3 gate event interrupt when timer1/3 gate event interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. when the falling edge of txgval occurs, the tmrxgif flag bit in the pir3 register will be set. if the tmrxgie bit in the pie3 register is set, then an interrupt will be recognized. the tmrxgif flag bit operates even when the timer1/3 gate is not enabled (tmrxge bit is cleared). for more information on selecting high or low priority status for the timer1/3 gate event interrupt see section 10.0 ?interrupts? . note: enabling toggle mode at the same time as changing the gate polarity may result in indeterminate operation. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 170 ? 2012 microchip technology inc. 13.8 timer1/3 interrupt the timer1/3 register pair (tmrxh:tmrxl) increments to ffffh and rolls over to 0000h. when timer1/3 rolls over, the timer1/3 interrupt flag bit of the pir1/2 register is set. to enable the interrupt on rollover, you must set these bits: ? tmrxon bit of the txcon register ? tmrxie bits of the pie1 or pie2 registers ? peie/giel bit of the intcon register ? gie/gieh bit of the intcon register the interrupt is cleared by clearing the tmrxif bit in the interrupt service routine. for more information on selecting high or low priority status for the timer1/3 overflow interrupt, see section 10.0 ?interrupts? . 13.9 timer1/3 operation during sleep timer1/3 can only operate during sleep when set up in asynchronous counter mode. in this mode, an external crystal or clock source can be used to increment the counter. to set up the timer to wake the device: ? tmrxon bit of the txcon register must be set ? tmrxie bit of the pie1/2 register must be set ? peie/giel bit of the intcon register must be set ? txsync bit of the txcon register must be set ? tmrxcs bits of the txcon register must be configured ? soscen bit of the txcon register must be configured the device will wake-up on an overflow and execute the next instruction. if the gie/gieh bit of the intcon register is set, the device will call the interrupt service routine. the secondary oscillator will continue to operate in sleep regardless of the txsync bit setting. 13.10 eccp/ccp capture/compare time base the ccp modules use the tmrxh:tmrxl register pair as the time base when operating in capture or compare mode. in capture mode, the value in the tmrxh:tmrxl register pair is copied into the ccprxh:ccprxl register pair on a configured event. in compare mode, an event is triggered when the value ccprxh:ccprxl register pair matches the value in the tmrxh:tmrxl register pair. this event can be a special event trigger. for more information, see section 15.0 ?capture/compare/pwm modules? . 13.11 eccp/ccp special event trigger when any of the ccp?s are configured to trigger a special event, the trigger will clear the tmrxh:tmrxl register pair. this special event does not cause a timer1/3 interrupt. the ccp module may still be configured to generate a ccp interrupt. in this mode of operation, the ccprxh:ccprxl register pair becomes the period register for timer1/3. timer1/3 should be synchronized and f osc /4 should be selected as the clock source in order to utilize the special event trigger. asynchronous operation of timer1/3 can cause a special event trigger to be missed. in the event that a write to tmrxh or tmrxl coincides with a special event trigger from the ccp, the write will take precedence. for more information, see section 18.2.8 ?special event trigger? . note: the tmrxh:tmrxl register pair and the tmrxif bit should be cleared before enabling interrupts. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 171 pic18(l)f2x/45k50 figure 13-3: timer1/3 incrementing edge figure 13-4: timer1/3 gate enable mode txcki = 1 when tmrx enabled txcki = 0 when tmrx enabled note 1: arrows indicate counter increments. 2: in counter mode, a falling edge must be registered by the count er prior to the first incrementing rising edge of the clock. tmrxge txgpol txg_in txcki txgval timer1/3 n n + 1 n + 2 n + 3 n + 4 www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 172 ? 2012 microchip technology inc. figure 13-5: timer1/3 gate toggle mode figure 13-6: timer1/3 gate single-pulse mode tmrxge txgpol txgtm txtxg_in txcki txgval timer1/3 n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 tmrxge txgpol txg_in txcki txgval timer1/3 n n + 1 n + 2 txgspm txggo/ done set by software cleared by hardware on falling edge of txgval set by hardware on falling edge of txgval cleared by software cleared by software tmrxgif counting enabled on rising edge of txg www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 173 pic18(l)f2x/45k50 figure 13-7: timer1/3 gate single-p ulse and toggle combined mode 13.12 peripheral module disable when a peripheral module is not used or inactive, the module can be disabled by setting the module disable bit in the pmd registers. this will reduce power con- sumption to an absolute minimum. setting the pmd bits holds the module in reset and disconnects the module?s clock source. the module disable bits for timer1 (tmr1md) and timer3 (tmr3md) are in the pmd0 register. see section 4.0 ?power-managed modes? for more information. tmrxge txgpol txg_in txcki txgval timer1/3 nn + 1 n + 2 txgspm txggo/ done set by software cleared by hardware on falling edge of txgval set by hardware on falling edge of txgval cleared by software cleared by software tmrxgif txgtm counting enabled on rising edge of txg n + 4 n + 3 www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 174 ? 2012 microchip technology inc. 13.13 register definitions: timer1/3 control register 13-1: txcon: timer1/3 control register r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w-0/0 r/w-0/u tmrxcs<1:0> txckps<1:0> soscen txs ync rd16 tmrxon bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 tmrxcs<1:0>: timer1/3 clock source select bits 11 = reserved. do not use. 10 = timer1/3 clock source is pin or oscillator: if soscen = 0 : external clock from txcki pin (on the rising edge) if soscen = 1 : crystal oscillator on sosci/sosco pins 01 = timer1/3 clock source is system clock (f osc ) 00 = timer1/3 clock source is instruction clock (f osc /4) bit 5-4 txckps<1:0>: timer1/3 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 soscen: secondary oscillator enable control bit 1 = dedicated secondary oscillator circuit enabled 0 = dedicated secondary oscillator circuit disabled bit 2 tx s ync : timer1/3 external clock input synchronization control bit tmrxc s<1:0> = 1x 1 = do not synchronize external clock input 0 = synchronize external clock input with system clock (f osc ) tmrxc s<1:0> = 0x this bit is ignored. timer1/3 uses the internal clock when tmrxcs<1:0> = 0x . bit 1 rd16: 16-bit read/write mode enable bit 1 = enables register read/write of timer1/3 in one 16-bit operation 0 = enables register read/write of timer1/3 in two 8-bit operation bit 0 tmrxon: timer1/3 on bit 1 = enables timer1/3 0 = stops timer1/3 clears timer1/3 gate flip-flop www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 175 pic18(l)f2x/45k50 register 13-2: txgcon: timer1/3 gate control register r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w/hc-0/u r-x/x r/w-0/u r/w-0/u tmrxge txgpol txgtm txgspm txggo/done txgval txgss<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared hc = bit is cleared by hardware bit 7 tmrxge: timer1/3 gate enable bit if tmrxon = 0 : this bit is ignored if tmrxon = 1 : 1 = timer1/3 counting is controlled by the timer1/3 gate function 0 = timer1/3 counts regardless of timer1/3 gate function bit 6 txgpol: timer1/3 gate polarity bit 1 = timer1/3 gate is active-high (timer1/3 counts when gate is high) 0 = timer1/3 gate is active-low (timer1/3 counts when gate is low) bit 5 txgtm: timer1/3 gate toggle mode bit 1 = timer1/3 gate toggle mode is enabled 0 = timer1/3 gate toggle mode is disabled and toggle flip-flop is cleared timer1/3 gate flip-flop toggles on every rising edge. bit 4 txgspm: timer1/3 gate single-pulse mode bit 1 = timer1/3 gate single-pulse mode is enabled and is controlling timer1/3 gate 0 = timer1/3 gate single-pulse mode is disabled bit 3 txggo/done : timer1/3 gate single-pulse acquisition status bit 1 = timer1/3 gate single-pulse acquisition is ready, waiting for an edge 0 = timer1/3 gate single-pulse acquisition has completed or has not been started this bit is automatically cleared when txgspm is cleared. bit 2 txgval: timer1/3 gate current state bit indicates the current state of the timer1/3 gate that could be provided to tmrxh:tmrxl. unaffected by timer1/3 gate enable (tmrxge). bit 1-0 txgss<1:0>: timer1/3 gate source select bits 00 = timer1/3 gate pin 01 = timer2 match pr2 output 10 = comparator 1 optionally synchronized output (sync_c1out) 11 = comparator 2 optionally synchronized output (sync_c2out) www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 176 ? 2012 microchip technology inc. table 13-5: registers associated wi th timer1/3 as a timer/counter table 13-6: configuration registers associated with timer1/3 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page anselb ? ?ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 155 intcon gie/gieh peie/giel tmr0ie int0ie iocie tmr0if int0if iocif 120 ipr1 actip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 129 ipr2 oscfip c1ip c2ip eeip bclip hlvdip tmr3ip ccp2ip 130 ipr3 ? ? ? ? ctmuip usbip tmr3gip tmr1gip 131 pie1 actie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 126 pie2 oscfie c1ie c2ie eeie bclie hlvdie tmr3ie ccp2ie 127 pie3 ? ? ? ? ctmuie usbie tmr3gie tmr1gie 128 pir1 actif adif rcif txif sspif ccp1if tmr2if tmr1if 123 pir2 oscfif c1if c2if eeif bclif hlvdif tmr3if ccp2if 124 pir3 ? ? ? ? ctmuif usbif tmr3gif tmr1gif 125 pmd0 ? uartmd usbmd actmd ?tmr3md tmr2md tmr1md 64 t1con tmr1cs<1:0> t1ckps<1:0> soscen t1sync rd16 tmr1on 174 t1gcon tmr1ge t1gpol t1gtm t1gspm t1ggo/d one t1gval t1gss<1:0> 175 t3con tmr3cs<1:0> t3ckps<1:0> soscen t3sync rd16 tmr3on 174 t3gcon tmr3ge t3gpol t3gtm t3gspm t3ggo/d one t3gval t3gss<1:0> 175 tmrxh timer1/3 register, high byte ? tmrxl timer1/3 register, low byte ? trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 156 trisc trisc7 trisc6 ? ? ? trisc2 trisc1 trisc0 156 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page config3h mclre sdomx ? t3cmx ? ? pbaden ccp2mx 391 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 177 pic18(l)f2x/45k50 14.0 timer2 module the timer2 module incorporates the following features: ? 8-bit timer and period registers (tmr2 and pr2, respectively) ? readable and writable (both registers) ? software programmable prescaler (1:1, 1:4, 1:16) ? software programmable postscaler (1:1 to 1:16) ? interrupt on tmr2 match with pr2, respectively ? optional use as the shift clock for the mssp module see figure 14-1 for a block diagram of timer2. figure 14-1: timer2 block diagram comparator tmrx sets flag tmrx output reset postscaler prescaler prx 2 f osc /4 1:1 to 1:16 1:1, 1:4, 1:16 eq 4 bit tmrxif txoutps<3:0> txckps<1:0> www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 178 ? 2012 microchip technology inc. 14.1 timer2 operation the clock input to the timer2 module is the system instruction clock (f osc /4). tmr2 increments from 00h on each clock edge. a 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. these options are selected by the prescaler control bits, t2ckps<1:0> of the t2con register. the value of tmr2 is compared to that of the period register, pr2, on each clock cycle. when the two values match, the comparator generates a match signal as the timer output. this signal also resets the value of tmr2 to 00h on the next cycle and drives the output counter/postscaler (see section 14.2 ?timer2 interrupt? ). the tmr2 and pr2 registers are both directly readable and writable. the tmr2 register is cleared on any device reset, whereas the pr2 register initializes to ffh. both the prescaler and postscaler counters are cleared on the following events: ? a write to the tmr2 register ? a write to the t2con register ? power-on reset (por) ? brown-out reset (bor) ?mclr reset ? watchdog timer (wdt) reset ? stack overflow reset ? stack underflow reset ? reset instruction 14.2 timer2 interrupt timer2 can also generate an optional device interrupt. the timer2 output signal (tmr2-to-pr2 match) provides the input for the 4-bit counter/postscaler. this counter generates the tmr2 match interrupt flag which is latched in tmr2if of the pir1 register. the interrupt is enabled by setting the tmr2 match interrupt enable bit, tmr2ie of the pie1 register. interrupt priority is selected with the tmr2ip bit in the ipr1 register. a range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, t2outps<3:0>, of the t2con register. 14.3 timer2 output the unscaled output of tmr2 is available primarily to the ccp modules, where it is used as a time base for operations in pwm mode. timer2 can be optionally used as the shift clock source for the mssp module operating in spi mode by setting sspm<3:0> = 0011 in the sspxcon1 register. additional information is provided in section 16.0 ?master synchronous serial port (mssp) module? . 14.4 timer2 operation during sleep the timer2 timers cannot be operated while the processor is in sleep mode. the contents of the tmr2 and pr2 registers will remain unchanged while the processor is in sleep mode. 14.5 peripheral module disable when a peripheral module is not used or inactive, the module can be disabled by setting the module disable bit in the pmd registers. this will reduce power con- sumption to an absolute minimum. setting the pmd bits holds the module in reset and disconnects the module?s clock source. the module disable bit for timer2 (tmr2md) is in the pmd0 register. see section 4.0 ?power-managed modes? for more information. note: tmr2 is not cleared when t2con is written. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 179 pic18(l)f2x/45k50 14.6 register definitions: timer2 control register 14-1: t2con: ti mer2 control register u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? t2outps<3:0> tmr2on t2ckps<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 unimplemented: read as ? 0 ? bit 6-3 t2outps<3:0>: timer2 output postscaler select bits 0000 = 1:1 postscaler 0001 = 1:2 postscaler 0010 = 1:3 postscaler 0011 = 1:4 postscaler 0100 = 1:5 postscaler 0101 = 1:6 postscaler 0110 = 1:7 postscaler 0111 = 1:8 postscaler 1000 = 1:9 postscaler 1001 = 1:10 postscaler 1010 = 1:11 postscaler 1011 = 1:12 postscaler 1100 = 1:13 postscaler 1101 = 1:14 postscaler 1110 = 1:15 postscaler 1111 = 1:16 postscaler bit 2 tmr2on: timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0 t2ckps<1:0>: timer2-type clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16 www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 180 ? 2012 microchip technology inc. table 14-1: summary of registers associated with timer2 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie/gieh peie/giel tmr0ie int0ie iocie tmr0if int0if iocif 120 ipr1 actip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 129 pie1 actie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 126 pir1 actif adif rcif txif sspif ccp1if tmr2if tmr1if 123 pmd0 ? uartmd usbmd actmd ? tmr3md tmr2md tmr1md 64 pr2 timer2 period register ? t2con ? t2outps<3:0> tmr2on t2ckps<1:0> 174 tmr2 timer2 register ? legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used by timer2. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 181 pic18(l)f2x/45k50 15.0 capture/compare/pwm modules the capture/compare/pwm module is a peripheral which allows the user to time and control different events, and to generate pulse-width modulation (pwm) signals. in capture mode, the peripheral allows the timing of the duration of an event. the compare mode allows the user to trigger an external event when a predetermined amount of time has expired. the pwm mode can generate pulse-width modulated signals of varying frequency and duty cycle. this family of devices contains one enhanced capture/ compare/pwm module (eccp1) and one standard capture/compare/pwm module (ccp2). the capture and compare functions are identical for the ccp/eccp modules. the difference between ccp and eccp modules are in the pulse-width modulation (pwm) function. in ccp modules, the standard pwm function is identical. in eccp modules, the enhanced pwm function has either full-bridge or half-bridge pwm output. full-bridge eccp modules have four available i/o pins while half-bridge eccp modules only have two available i/o pins. eccp pwm modules are backward compatible with ccp pwm modules and can be configured as standard pwm modules. 15.1 capture mode the capture mode function described in this section is identical for all ccp and eccp modules available on this device family. capture mode makes use of the 16-bit timer resources, timer1 and timer3. the timer resources for each ccp capture function are independent and are selected using the ccptmrs register. when an event occurs on the ccpx pin, the 16-bit ccprxh:ccprxl register pair captures and stores the 16-bit value of the tmrxh:tmrxl register pair, respectively. an event is defined as one of the following and is configured by the ccpxm<3:0> bits of the ccpxcon register: ? every falling edge ? every rising edge ? every 4th rising edge ? every 16th rising edge when a capture is made, the corresponding interrupt request flag bit ccpxif of the pir1 and pir2 register is set. the interrupt flag must be cleared in software. if another capture occurs before the value in the ccprxh:ccprxl register pair is read, the old captured value is overwritten by the new captured value. figure 15-1 shows a simplified diagram of the capture operation. figure 15-1: capture mode operation block diagram note 1: in devices with more than one ccp module, it is very important to pay close attention to the register names used. a number placed after the module acronym is used to distinguish between separate modules. for example, the ccp1con and ccp2con control the same operational aspects of two completely different ccp modules. 2: throughout this section, generic references to a ccp module in any of its operating modes may be interpreted as being equally applicable to eccp1 and ccp2. register names, module signals, i/o pins and bit names may use the generic designator ?x? to indicate the use of a numeral to distinguish a particular module, when required. ccprxh ccprxl tmrxh tmrxl set flag bit ccpxif (pirx register) capture enable ccpxm<3:0> prescaler ? 1, 4, 16 and edge detect pin ccpx system clock (f osc ) www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 182 ? 2012 microchip technology inc. 15.1.1 ccp pin configuration in capture mode, the ccpx pin should be configured as an input by setting the associated tris control bit. some ccpx outputs are multiplexed on a couple of pins. table 15-1 shows the ccp output pin multiplexing. selection of the output pin is determined by the ccpxmx bits in configuration register 3h (config3h). refer to register 26-5 for more details. 15.1.2 timer1 mode resource the 16-bit timer resource must be running in timer mode or synchronized counter mode for the ccp module to use the capture feature. in asynchronous counter mode, the capture operation may not work. see section 13.0 ?timer1/3 module with gate control? for more information on configuring the 16-bit timers. 15.1.3 software interrupt mode when the capture mode is changed, a false capture interrupt may be generated. the user should keep the ccpxie interrupt enable bit of the piex register clear to avoid false interrupts. additionally, the user should clear the ccpxif interrupt flag bit of the pirx register following any change in operating mode. note: if the ccpx pin is configured as an output, a write to the port can cause a capture condition. table 15-1: ccp pin multiplexing ccp output config 3h control bit bit value i/o pin ccp2 ccp2mx 0 rb3 1 (*) rc1 legend: * = default note: clocking the 16-bit timer resource from the system clock (f osc ) should not be used in capture mode. in order for capture mode to recognize the trigger event on the ccpx pin, the timer resource must be clocked from the instruction clock (f osc /4) or from an external clock source. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 183 pic18(l)f2x/45k50 15.1.4 ccp prescaler there are four prescaler settings specified by the ccpxm<3:0> bits of the ccpxcon register. whenever the ccp module is turned off, or the ccp module is not in capture mode, the prescaler counter is cleared. any reset will clear the prescaler counter. switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. to avoid this unexpected operation, turn the module off by clearing the ccpxcon register before changing the prescaler. example 15-1 demonstrates the code to perform this function. example 15-1: changing between capture prescalers 15.1.5 capture during sleep capture mode requires a 16-bit timerx module for use as a time base. there are four options for driving the 16-bit timerx module in capture mode. it can be driven by the system clock (f osc ), the instruction clock (f osc / 4), or by the external clock sources, the secondary oscillator (s osc ), or the txcki clock input. when the 16-bit timerx resource is clocked by f osc or f osc /4, timerx will not increment during sleep. when the device wakes from sleep, timerx will continue from its previous state. capture mode will operate during sleep when the 16-bit timerx resource is clocked by one of the external clock sources (s osc or the txcki pin). #define new_capt_ps 0x06 //capture // prescale 4th ... // rising edge ccpxcon = 0; // turn the ccp // module off ccpxcon = new_capt_ps; // turn ccp module // on with new // prescale value www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 184 ? 2012 microchip technology inc. table 15-2: registers associated with capture name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ccp1con p1m<1:0> dc1b<1:0> ccp1m<3:0> 206 ccp2con ? ? dc2b<1:0> ccp2m<3:0> 206 ccpr1h capture/compare/pwm register 1, high byte (msb) ? ccpr1l capture/compare/pwm register 1, low byte (lsb) ? ccpr2h capture/compare/pwm register 2, high byte (msb) ? ccpr2l capture/compare/pwm register 2, low byte (lsb) ? ccptmrs ? ? ? ? c2tsel ? ? c1tsel 209 intcon gie/gieh peie/giel tmr0ie int0ie iocie tmr0if int0if iocif 120 ipr1 actip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 129 ipr2 oscfip c1ip c2ip eeip bclip hlvdip tmr3ip ccp2ip 130 pie1 actie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 126 pie2 oscfie c1ie c2ie eeie bclie hlvdie tmr3ie ccp2ie 127 pir1 actif adif rcif txif sspif ccp1if tmr2if tmr1if 123 pir2 oscfif c1if c2if eeif bclif hlvdif tmr3if ccp2if 124 pmd0 ? uartmd usbmd actmd ?tmr3md tmr2md tmr1md 64 pmd1 ? msspmd ctmumd cmp2md cmp1md adcmd ccp2md ccp1md 65 t1con tmr1cs<1:0> t1ckps<1:0> soscen t1sync rd16 tmr1on 174 t1gcon tmr1ge t1gpol t1gtm t1gspm t1ggo/done t1gval t1gss<1:0> 175 t3con tmr3cs<1:0> t3ckps<1:0> soscen t3sync rd16 tmr3on 174 t3gcon tmr3ge t3gpol t3gtm t3gspm t3ggo/done t3gval t3gss<1:0> 175 tmr1h holding register for the most significant byte of the 16-bit tmr1 register ? tmr1l holding register for the least significant byte of the 16-bit tmr1 register ? tmr3h holding register for the most significant byte of the 16-bit tmr3 register ? tmr3l holding register for the least significant byte of the 16-bit tmr3 register ? trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 156 trisc trisc7 trisc6 ? ? ? trisc2 trisc1 trisc0 156 legend: ? = unimplemented location, read as ? 0 ?. shaded bits are not used by capture mode. table 15-3: configuration regist ers associated with capture name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page config3h mclre sdomx ? t3cmx ? ? pbaden ccp2mx 391 legend: ? = unimplemented location, read as ? 0 ?. shaded bits are not used by capture mode. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 185 pic18(l)f2x/45k50 15.2 compare mode the compare mode function described in this section is identical for all ccp and eccp modules available on this device family. compare mode makes use of the 16-bit timer resources, timer1 and timer3. the 16-bit value of the ccprxh:ccprxl register pair is constantly compared against the 16-bit value of the tmrxh:tmrxl register pair. when a match occurs, one of the following events can occur: ? toggle the ccpx output ? set the ccpx output ? clear the ccpx output ? generate a special event trigger ? generate a software interrupt the action on the pin is based on the value of the ccpxm<3:0> control bits of the ccpxcon register. at the same time, the interrupt flag ccpxif bit is set. all compare modes can generate an interrupt. figure 15-2 shows a simplified diagram of the compare operation. figure 15-2: compare mode operation block diagram 15.2.1 ccp pin configuration the user must configure the ccpx pin as an output by clearing the associated tris bit. some ccpx outputs are multiplexed on a couple of pins. table 15-1 shows the ccp output pin multiplexing. selection of the output pin is determined by the ccpxmx bits in configuration register 3h (config3h). refer to register 26-5 for more details. 15.2.2 timerx mode resource in compare mode, 16-bit timerx resource must be running in either timer mode or synchronized counter mode. the compare operation may not work in asynchronous counter mode. see section 13.0 ?timer1/3 module with gate control? for more information on configuring the 16-bit timerx resources. 15.2.3 software interrupt mode when generate software interrupt mode is chosen (ccpxm<3:0> = 1010 ), the ccpx module does not assert control of the ccpx pin (see the ccpxcon register). ccprxh ccprxl tmrxh tmrxl comparator qs r output logic special event trigger set ccpxif interrupt flag (pir x) match tris ccpxm<3:0> mode select output enable pin special event trigger function on ? eccp1 and ccp2 will: - reset timerx ? tmrxh:tmrxl = 0x0000 - timerx interrupt flag, (tmrxif) is not set additional function on ? ccp2 will - set adcon0<1>, go/done bit to start an adc conversion if adcon<0>, adon = 1 , and if adcon1<7>, trigsel = 0. ccpx 4 note: clearing the ccpxcon register will force the ccpx compare output latch to the default low level. this is not the port i/o data latch. note: clocking timerx from the system clock (f osc ) should not be used in compare mode. in order for compare mode to recognize the trigger event on the ccpx pin, timerx must be clocked from the instruction clock (f osc /4) or from an external clock source. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 186 ? 2012 microchip technology inc. 15.2.4 special event trigger when special event trigger mode is selected (ccpxm<3:0> = 1011 ), and a match of the tmrxh:tmrxl and the ccprxh:ccprxl registers occurs, all ccpx and eccpx modules will immediately: ? set the ccp interrupt flag bit ? ccpxif ? ccp2 will start an adc conversion, if the adc is enabled and trigsel is configured for ccp2. on the next timerx rising clock edge: ? a reset of timerx register pair occurs ? tmrxh:tmrxl = 0x0000, this special event trigger mode does not: ? assert control over the ccpx or eccpx pins. ? set the tmrxif interrupt bit when the tmrxh:tmrxl register pair is reset. (tmrxif gets set on a timerx overflow.) if the value of the ccprxh:ccprxl registers are modified when a match occurs, the user should be aware that the automatic reset of timerx occurs on the next rising edge of the clock. therefore, modifying the ccprxh:ccprxl registers before this reset occurs will allow the timerx to continue without being reset, inadvertently resulting in the next event being advanced or delayed. the special event trigger mode allows the ccprxh:ccprxl register pair to effectively provide a 16-bit programmable period register for timerx. 15.2.5 compare during sleep the compare mode is dependent upon the system clock (f osc ) for proper operation. since f osc is shut down during sleep mode, the compare mode will not function properly during sleep. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 187 pic18(l)f2x/45k50 table 15-4: registers associated with compare name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ccp1con p1m<1:0> dc1b<1:0> ccp1m<3:0> 206 ccp2con ? ? dc2b<1:0> ccp2m<3:0> 206 ccpr1h capture/compare/pwm register 1, high byte (msb) ? ccpr1l capture/compare/pwm register 1, low byte (lsb) ? ccpr2h capture/compare/pwm register 2, high byte (msb) ? ccpr2l capture/compare/pwm register 2, low byte (lsb) ? ccptmrs ? ? ? ? c2tsel ? ? c1tsel 209 adcon1 trigsel ? ? ? pvcfg<1:0> nvcfg<1:0> 307 intcon gie/gieh peie/giel tmr0ie int0ie iocie tmr0if int0if iocif 120 ipr1 actip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 129 ipr2 oscfip c1ip c2ip eeip bclip hlvdip tmr3ip ccp2ip 130 pie1 actie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 126 pie2 oscfie c1ie c2ie eeie bclie hlvdie tmr3ie ccp2ie 127 pir1 actif adif rcif txif sspif ccp1if tmr2if tmr1if 123 pir2 oscfif c1if c2if eeif bclif hlvdif tmr3if ccp2if 124 pmd0 ? uartmd usbmd actmd ?tmr3md tmr2md tmr1md 64 pmd1 ? msspmd ctmumd cmp2md cmp1md adcmd ccp2md ccp1md 65 t1con tmr1cs<1:0> t1ckps<1:0> soscen t1sync rd16 tmr1on 174 t1gcon tmr1ge t1gpol t1gtm t1gspm t1ggo/d one t1gval t1gss<1:0> 175 t3con tmr3cs<1:0> t3ckps<1:0> soscen t 3s ync rd16 tmr3on 174 t3gcon tmr3ge t3gpol t3gtm t3gspm t3ggo/d one t3gval t3gss<1:0> 175 tmr1h holding register for the most significant byte of the 16-bit tmr1 register ? tmr1l holding register for the least sign ificant byte of the 16-bit tmr1 register ? tmr3h holding register for the most significant byte of the 16-bit tmr3 register ? tmr3l holding register for the least sign ificant byte of the 16-bit tmr3 register ? trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 156 trisc trisc7 trisc6 ? ? ? trisc2 trisc1 trisc0 156 legend: ? = unimplemented location, read as ? 0 ?. shaded bits are not used by capture mode. table 15-5: configuration regist ers associated with capture name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page config3h mclre sdomx ? t3cmx ? ? pbaden ccp2mx 391 legend: ? = unimplemented location, read as ? 0 ?. shaded bits are not used by capture mode. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 188 ? 2012 microchip technology inc. 15.3 pwm overview pulse-width modulation (pwm) is a scheme that provides power to a load by switching quickly between fully on and fully off states. the pwm signal resembles a square wave where the high portion of the signal is considered the on state and the low portion of the signal is considered the off state. the high portion, also known as the pulse width, can vary in time and is defined in steps. a larger number of steps applied, which lengthens the pulse width, also supplies more power to the load. lowering the number of steps applied, which shortens the pulse width, supplies less power. the pwm period is defined as the duration of one complete cycle or the total amount of on and off time combined. pwm resolution defines the maximum number of steps that can be present in a single pwm period. a higher resolution allows for more precise control of the pulse width time and in turn the power that is applied to the load. the term duty cycle describes the proportion of the on time to the off time and is expressed in percentages, where 0% is fully off and 100% is fully on. a lower duty cycle corresponds to less power applied and a higher duty cycle corresponds to more power applied. figure 15-3 shows a typical waveform of the pwm signal. 15.3.1 standard pwm operation the standard pwm function described in this section is available and identical for ccp and eccp modules. the standard pwm mode generates a pulse-width modulation (pwm) signal on the ccpx pin with up to 10 bits of resolution. the period, duty cycle, and resolution are controlled by the following registers: ? pr2 register ? t2con register ? ccprxl registers ? ccpxcon registers figure 15-4 shows a simplified block diagram of pwm operation. figure 15-3: ccp pwm output signal figure 15-4: simplified pwm block diagram 15.3.2 setup for pwm operation the following steps should be taken when configuring the ccp module for standard pwm operation: 1. disable the ccpx pin output driver by setting the associated tris bit. 2. load the pr2 register for timer2 with the pwm period value. 3. configure the ccp module for the pwm mode by loading the ccpxcon register with the appropriate values. 4. load the ccprxl register and the dcxb<1:0> bits of the ccpxcon register, with the pwm duty cycle value. note 1: the corresponding tris bit must be cleared to enable the pwm output on the ccpx pin. 2: clearing the ccpxcon register will relinquish control of the ccpx pin. period pulse width tmr2 = 0 tmr2 = ccprxh:ccpxcon<5:4> tmr2 = pr2 ccprxl ccprxh (2) (slave) comparator tmr2 pr2 (1) rq s duty cycle registers ccpxcon<5:4> clear timer, toggle ccpx pin and latch duty cycle note 1: the 8-bit timer tmr2 register is concatenated with the 2-bit internal system clock (f osc ), or two bits of the prescaler, to create the 10-bit time base. 2: in pwm mode, ccprxh is a read-only register. tris ccpx comparator www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 189 pic18(l)f2x/45k50 5. configure and start the 8-bit timer2: ? clear the tmr2if interrupt flag bit of the pir1 register. see note 1 below. ? configure the t2ckps bits of the t2con register with the timer prescale value. ? enable the timer by setting the tmr2on bit of the t2con register. 6. enable pwm output pin: ? wait until the timer overflows and the tmr2if bit of the pir1 register is set. see note 1 below. ? enable the ccpx pin output driver by clearing the associated tris bit. 15.3.3 pwm period the pwm period is specified by the pr2 register of 8-bit timer2. the pwm period can be calculated using the formula of equation 15-1 . equation 15-1: pwm period when tmr2 is equal to pr2, the following three events occur on the next increment cycle: ? tmr2 is cleared ? the ccpx pin is set. (exception: if the pwm duty cycle = 0%, the pin will not be set.) ? the pwm duty cycle is latched from ccprxl into ccprxh. 15.3.4 pwm duty cycle the pwm duty cycle is specified by writing a 10-bit value to multiple registers: ccprxl register and dcxb<1:0> bits of the ccpxcon register. the ccprxl contains the eight msbs and the dcxb<1:0> bits of the ccpxcon register contain the two lsbs. ccprxl and dcxb<1:0> bits of the ccpxcon register can be written to at any time. the duty cycle value is not latched into ccprxh until after the period completes (i.e., a match between pr2 and tmr2 registers occurs). while using the pwm, the ccprxh register is read-only. equation 15-2 is used to calculate the pwm pulse width. equation 15-3 is used to calculate the pwm duty cycle ratio. equation 15-2: pulse width equation 15-3: duty cycle ratio the ccprxh register and a 2-bit internal latch are used to double buffer the pwm duty cycle. this double buffering is essential for glitchless pwm operation. the 8-bit timer tmr2 register is concatenated with either the 2-bit internal system clock (f osc ), or two bits of the prescaler, to create the 10-bit time base. the system clock is used if the timer2 prescaler is set to 1:1. when the 10-bit time base matches the ccprxh and 2-bit latch, then the ccpx pin is cleared (see figure 15-4 ). note 1: in order to send a complete duty cycle and period on the first pwm output, the above steps must be included in the setup sequence. if it is not critical to start with a complete pwm signal on the first output, then step 5 may be ignored. note: the timer postscaler (see section 14.0 ?timer2 module? ) is not used in the determination of the pwm frequency. pwm period pr 2 ?? 1 + ?? 4t osc ? ? ? = (tmr2 prescale value) note 1: t osc = 1/f osc pulse width ccprxl:ccpxcon<5:4> ?? ? = t osc ? (tmr2 prescale value) duty cycle ratio ccprxl:ccpxcon<5:4> ?? 4pr 2 1 + ?? ---------------------------------------------------------------------- - = www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 190 ? 2012 microchip technology inc. 15.3.5 pwm resolution the resolution determines the number of available duty cycles for a given period. for example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. the maximum pwm resolution is 10 bits when pr2 is 255. the resolution is a function of the pr2 register value as shown by equation 15-4 . equation 15-4: pwm resolution 15.3.6 operation in sleep mode in sleep mode, the tmr2 register will not increment and the state of the module will not change. if the ccpx pin is driving a value, it will continue to drive that value. when the device wakes up, tmr2 will continue from its previous state. 15.3.7 changes in system clock frequency the pwm frequency is derived from the system clock frequency. any changes in the system clock frequency will result in changes to the pwm frequency. see section 3.0 ?oscillator module (with fail-safe clock monitor)? for additional details. 15.3.8 effects of reset any reset will force all ports to input mode and the ccp registers to their reset states. note: if the pulse width value is greater than the period the assigned pwm pin(s) will remain unchanged. resolution 4pr 2 1 + ?? ?? log 2 ?? log ----------------------------------------- - bits = table 15-6: example pwm frequencies and resolutions (f osc = 32 mhz) pwm frequency 1.95 khz 7.81 khz 31.25 khz 125 khz 250 khz 333.3 khz timer prescale (1, 4, 16) 16 4 1 1 1 1 pr2 value 0xff 0xff 0xff 0x3f 0x1f 0x17 maximum resolution (bits) 10 10 10 8 7 6.6 table 15-7: example pwm frequencies and resolutions (f osc = 20 mhz) pwm frequency 1.22 khz 4.88 khz 19.53 khz 78.12 khz 156.3 khz 208.3 khz timer prescale (1, 4, 16) 16 4 1 1 1 1 pr2 value 0xff 0xff 0xff 0x3f 0x1f 0x17 maximum resolution (bits) 10 10 10 8 7 6.6 table 15-8: example pwm frequencies and resolutions (f osc = 8 mhz) pwm frequency 1.22 khz 4.90 khz 19.61 khz 76.92 khz 153.85 khz 200.0 khz timer prescale (1, 4, 16) 16 4 1 1 1 1 pr2 value 0x65 0x65 0x65 0x19 0x0c 0x09 maximum resolution (bits) 8 8 8 6 5 5 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 191 pic18(l)f2x/45k50 table 15-10: configurat ion registers associated with capture table 15-9: registers associated with standard pwm name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ccp1con p1m<1:0> dc1b<1:0> ccp1m<3:0> 206 ccp2con ? ? dc2b<1:0> ccp2m<3:0> 206 ccptmrs ? ? ? ? c2tsel ? ? c1tsel 209 intcon gie/gieh peie/giel tmr0ie int0ie iocie tmr0if int0if iocif 120 ipr1 actip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 129 ipr2 oscfip c1ip c2ip eeip bclip hlvdip tmr3ip ccp2ip 130 pie1 actie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 126 pie2 oscfie c1ie c2ie eeie bclie hlvdie tmr3ie ccp2ie 127 pir1 actif adif rcif txif sspif ccp1if tmr2if tmr1if 123 pir2 oscfif c1if c2if eeif bclif hlvdif tmr3if ccp2if 124 pmd0 ? uartmd usbmd actmd ? tmr3md tmr2md tmr1md 64 pmd1 ? msspmd ctmumd cmp2md cmp1md adcmd ccp2md ccp1md 65 pr2 timer2 period register ? t2con ?t2outps<3:0>tmr2on t2ckps<1:0> 179 tmr2 timer2 period register ? trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 156 trisc trisc7 trisc6 ? ? ? trisc2 trisc1 trisc0 156 legend: ? = unimplemented location, read as ? 0 ?. shaded bits are not used by capture mode. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page config3h mclre sdomx ? t3cmx ? ? pbaden ccp2mx 391 legend: ? = unimplemented location, read as ? 0 ?. shaded bits are not used by capture mode. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 192 ? 2012 microchip technology inc. 15.4 pwm (enhanced mode) the enhanced pwm function described in this section is available for ccp module eccp1. the enhanced pwm mode generates a pulse-width modulation (pwm) signal on up to four different output pins with up to 10 bits of resolution. the period, duty cycle, and resolution are controlled by the following registers: ? pr2 register ? t2con register ? ccprxl registers ? ccpxcon registers the eccp modules have the following additional pwm registers which control auto-shutdown, auto-restart, dead-band delay and pwm steering modes: ? eccpxas registers ? pstrxcon registers ? pwmxcon registers the enhanced pwm module can generate the following five pwm output modes: ? single pwm ? half-bridge pwm ? full-bridge pwm, forward mode ? full-bridge pwm, reverse mode ? single pwm with pwm steering mode to select an enhanced pwm output mode, the pxm<1:0> bits of the ccpxcon register must be configured appropriately. the pwm outputs are multiplexed with i/o pins and are designated pxa, pxb, pxc and pxd. the polarity of the pwm pins is configurable and is selected by setting the ccpxm bits in the ccpxcon register appropriately. figure 15-5 shows an example of a simplified block diagram of the enhanced pwm module. table 15-11 shows the pin assignments for various enhanced pwm modes. figure 15-5: example simplified block diagram of the enhanced pwm mode note 1: the corresponding tris bit must be cleared to enable the pwm output on the ccpx pin. 2: clearing the ccpxcon register will relinquish control of the ccpx pin. 3: any pin not used in the enhanced pwm mode is available for alternate pin functions, if applicable. 4: to prevent the generation of an incomplete waveform when the pwm is first enabled, the eccp module waits until the start of a new pwm period before generating a pwm signal. ccprxl ccprxh (slave) comparator tmr2 comparator pr2 (1) rq s duty cycle registers dcxb<1:0> clear timer, toggle pwm pin and latch duty cycle note 1: the 8-bit timer tmr2 register is concatenated with the 2-bit internal q clock, or two bits of the prescaler to create the 10-bi t time base. 2: pxc and pxd are not available on half-bridge eccp modules. trisx ccpx/pxa trisx pxb trisx pxc (2) trisx pxd (2) output controller pxm<1:0> 2 ccpxm<3:0> 4 pwmxcon ccpx/pxa pxb pxc pxd www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 193 pic18(l)f2x/45k50 figure 15-6: example pwm (enhanced mode) output relationships (active-high state) table 15-11: example pin assignments for various pwm enhanced modes eccp mode pxm<1:0> ccpx/pxa pxb pxc pxd single 00 yes (1) yes (1) yes (1) yes (1) half-bridge 10 yes yes no no full-bridge, forward 01 yes yes yes yes full-bridge, reverse 11 yes yes yes yes note 1: pwm steering enables outputs in single mode. 0 period 00 10 01 11 signal prx+1 pxm<1:0> pxa modulated pxa modulated pxb modulated pxa active pxb inactive pxc inactive pxd modulated pxa inactive pxb modulated pxc active pxd inactive pulse width (single output) (half-bridge) (full-bridge, forward) (full-bridge, reverse) delay (1) delay (1) relationships: ? period = 4 * t osc * (prx + 1) * (tmrx prescale value) ? pulse width = t osc * (ccprxl<7:0>:ccpxcon<5:4>) * (tmrx prescale value) ? delay = 4 * t osc * (pwmxcon<6:0>) note 1: dead-band delay is programmed using the pwmxcon register ( section 15.4.5 ?programmable dead-band delay mode? ). www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 194 ? 2012 microchip technology inc. figure 15-7: example enhanced pwm outp ut relationships (active-low state) 0 period 00 10 01 11 signal prx+1 pxm<1:0> pxa modulated pxa modulated pxb modulated pxa active pxb inactive pxc inactive pxd modulated pxa inactive pxb modulated pxc active pxd inactive pulse width (single output) (half-bridge) (full-bridge, forward) (full-bridge, reverse) delay (1) delay (1) relationships: ? period = 4 * t osc * (prx + 1) * (tmrx prescale value) ? pulse width = t osc * (ccprxl<7:0>:ccpxcon<5:4>) * (tmrx prescale value) ? delay = 4 * t osc * (pwmxcon<6:0>) note 1: dead-band delay is programmed using the pwmxcon register ( section 15.4.5 ?programmable dead-band delay mode? ). www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 195 pic18(l)f2x/45k50 15.4.1 half-bridge mode in half-bridge mode, two pins are used as outputs to drive push-pull loads. the pwm output signal is output on the ccpx/pxa pin, while the complementary pwm output signal is output on the pxb pin (see figure 15-9 ). this mode can be used for half-bridge applications, as shown in figure 15-9 , or for full-bridge applications, where four power switches are being modulated with two pwm signals. in half-bridge mode, the programmable dead-band delay can be used to prevent shoot-through current in half- bridge power devices. the value of the pdc<6:0> bits of the pwmxcon register sets the number of instruction cycles before the output is driven active. if the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. see section 15.4.5 ?programmable dead-band delay mode? for more details of the dead-band delay operations. since the pxa and pxb outputs are multiplexed with the port data latches, the associated tris bits must be cleared to configure pxa and pxb as outputs. figure 15-8: example of half- bridge pwm output figure 15-9: example of half-bridge applications period pulse width td td (1) pxa (2) pxb (2) td = dead-band delay period (1) (1) note 1: at this time, the tmrx register is equal to the prx register. 2: output signals are shown as active-high. pxa pxb fet driver fet driver load + - + - fet driver fet driver v+ load fet driver fet driver pxa pxb standard half-bridge circuit (?push-pull?) half-bridge output driving a full-bridge circuit www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 196 ? 2012 microchip technology inc. 15.4.2 full-bridge mode in full-bridge mode, all four pins are used as outputs. an example of full-bridge application is shown in figure 15-10 . in the forward mode, pin ccpx/pxa is driven to its active state, pin pxd is modulated, while pxb and pxc will be driven to their inactive state as shown in figure 15-11 . in the reverse mode, pxc is driven to its active state, pin pxb is modulated, while pxa and pxd will be driven to their inactive state as shown figure 15-11 . pxa, pxb, pxc and pxd outputs are multiplexed with the port data latches. the associated tris bits must be cleared to configure the pxa, pxb, pxc and pxd pins as outputs. figure 15-10: example of full-bridge application pxa pxc fet driver fet driver v+ v- load fet driver fet driver pxb pxd qa qb qd qc www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 197 pic18(l)f2x/45k50 figure 15-11: example of full-bridge pwm output period pulse width pxa (2) pxb (2) pxc (2) pxd (2) forward mode (1) period pulse width pxa (2) pxc (2) pxd (2) pxb (2) reverse mode (1) (1) (1) note 1: at this time, the tmrx register is equal to the prx register. 2: output signal is shown as active-high. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 198 ? 2012 microchip technology inc. 15.4.2.1 direction change in full-bridge mode in the full-bridge mode, the pxm1 bit in the ccpxcon register allows users to control the forward/reverse direction. when the application firmware changes this direction control bit, the module will change to the new direction on the next pwm cycle. a direction change is initiated in software by changing the pxm1 bit of the ccpxcon register. the following sequence occurs four timer cycles prior to the end of the current pwm period: ? the modulated outputs (pxb and pxd) are placed in their inactive state. ? the associated unmodulated outputs (pxa and pxc) are switched to drive in the opposite direction. ? pwm modulation resumes at the beginning of the next period. see figure 15-12 for an illustration of this sequence. the full-bridge mode does not provide dead-band delay. as one output is modulated at a time, dead-band delay is generally not required. there is a situation where dead-band delay is required. this situation occurs when both of the following conditions are true: 1. the direction of the pwm output changes when the duty cycle of the output is at or near 100%. 2. the turn off time of the power switch, including the power device and driver circuit, is greater than the turn on time. figure 15-13 shows an example of the pwm direction changing from forward to reverse, at a near 100% duty cycle. in this example, at time t1, the output pxa and pxd become inactive, while output pxc becomes active. since the turn off time of the power devices is longer than the turn on time, a shoot-through current will flow through power devices qc and qd (see figure 15-10 ) for the duration of ?t?. the same phenomenon will occur to power devices qa and qb for pwm direction change from reverse to forward. if changing pwm direction at high duty cycle is required for an application, two possible solutions for eliminating the shoot-through current are: 1. reduce pwm duty cycle for one pwm period before changing directions. 2. use switch drivers that can drive the switches off faster than they can drive them on. other options to prevent shoot-through current may exist. figure 15-12: example of pwm direction change pulse width period (1) signal note 1: the direction bit pxm1 of the ccpxcon register is written any time during the pwm cycle. 2: when changing directions, the pxa and pxc signals switch before the end of the current pwm cycle. the modulated pxb and pxd signals are inactive at this ti me. the length of this time is (timer2 prescale)/f osc . period (2) pxa (active-high) pxb (active-high) pxc (active-high) pxd (active-high) pulse width www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 199 pic18(l)f2x/45k50 figure 15-13: example of pwm direct ion change at near 100% duty cycle 15.4.3 enhanced pwm auto- shutdown mode the pwm mode supports an auto-shutdown mode that will disable the pwm outputs when an external shutdown event occurs. auto-shutdown mode places the pwm output pins into a predetermined state. this mode is used to help prevent the pwm from damaging the application. the auto-shutdown sources are selected using the eccpxas register. a shutdown event may be generated by: ?a logic ? 0 ? on the fltx pin ? comparator cx (async_cxout) ? setting the eccpxase bit in firmware a shutdown condition is indicated by the eccpxase (auto-shutdown event status) bit of the eccpxas register. if the bit is a ? 0 ?, the pwm pins are operating normally. if the bit is a ? 1 ?, the pwm outputs are in the shutdown state. when a shutdown event occurs, two things happen: the eccpxase bit is set to ? 1 ?. the eccpxase will remain set until cleared in firmware or an auto-restart occurs (see section 15.4.4 ?auto-restart mode? ). the enabled pwm pins are asynchronously placed in their shutdown states. the pwm output pins are grouped into pairs [pxa/pxc ] and [pxb/pxd]. the state of each pin pair is determined by the pssxac<1:0> and pssxbd<1:0> bits of the eccpxas register. each pin pair may be placed into one of three states: ? drive logic ? 1 ? ? drive logic ? 0 ? ? tri-state (high-impedance) forward period reverse period pxa t on t off t = t off ? t on pxb pxc pxd external switch d potential shoot-through current note 1: all signals are shown as active-high. 2: t on is the turn-on delay of pow er switch qc and its driver. 3: t off is the turn-off delay of power switch qd and its driver. external switch c t1 pw pw note 1: the auto-shutdown condition is a level- based signal, not an edge-based signal. as long as the level is present, the auto- shutdown will persist. 2: writing to the eccpxase bit is disabled while an auto-shutdown condition persists. 3: once the auto-shutdown condition has been removed and the pwm restarted (either through firmware or auto-restart), the pwm signal will always restart at the beginning of the next pwm period. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 200 ? 2012 microchip technology inc. figure 15-14: pwm auto-shutdown wi th firmware restart (pxrsen = 0 ) 15.4.4 auto-restart mode the enhanced pwm can be configured to automatically restart the pwm signal once the auto- shutdown condition has been removed. auto-restart is enabled by setting the pxrsen bit in the pwmxcon register. if auto-restart is enabled, the eccpxase bit will remain set as long as the auto-shutdown condition is active. when the auto-shutdown condition is removed, the eccpxase bit will be cleared via hardware and normal operation will resume. figure 15-15: pwm auto-shutdown with auto-restart (pxrsen = 1 ) shutdown pwm eccpxase bit activity event shutdown event occurs shutdown event clears pwm resumes pwm period start of pwm period eccpxase cleared by firmware timer overflow timer overflow timer overflow timer overflow missing pulse (auto-shutdown) missing pulse (eccpxase not clear) timer overflow shutdown pwm eccpxase bit activity event shutdown event occurs shutdown event clears pwm period start of pwm period eccpxase cleared by hardware timer overflow timer overflow timer overflow timer overflow missing pulse (auto-shutdown) missing pulse (eccpxase not clear) timer overflow pwm resumes www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 201 pic18(l)f2x/45k50 15.4.5 programmable dead-band delay mode in half-bridge applications where all power switches are modulated at the pwm frequency, the power switches normally require more time to turn off than to turn on. if both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off. during this brief interval, a very high current ( shoot-through current ) will flow through both power switches, shorting the bridge supply. to avoid this potentially destructive shoot- through current from flowing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. in half-bridge mode, a digitally programmable dead- band delay is available to avoid shoot-through current from destroying the bridge power switches. the delay occurs at the signal transition from the non-active state to the active state. see figure 15-16 for illustration. the lower seven bits of the associated pwmxcon register ( register 15-5 ) sets the delay period in terms of microcontroller instruction cycles (t cy or 4 t osc ). figure 15-16: example of half- bridge pwm output figure 15-17: example of half-bridge applications period pulse width td td (1) pxa (2) pxb (2) td = dead-band delay period (1) (1) note 1: at this time, the tmrx register is equal to the prx register. 2: output signals are shown as active-high. pxa pxb fet driver fet driver v+ v- load + v - + v - standard half-bridge circuit (?push-pull?) www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 202 ? 2012 microchip technology inc. 15.4.6 pwm steering mode in single output mode, pwm steering allows any of the pwm pins to be the modulated signal. additionally, the same pwm signal can be simultaneously available on multiple pins. once the single output mode is selected (ccpxm<3:2> = 11 and pxm<1:0> = 00 of the ccpxcon register), the user firmware can bring out the same pwm signal to one, two, three or four output pins by setting the appropriate steering enable bits (strxa, strxb, strxc and/or strxd) of the pstrxcon register, as shown in table 15-12 . while the pwm steering mode is active, ccpxm<1:0> bits of the ccpxcon register select the pwm output polarity for the pxd, pxc, pxb and pxa pins. the pwm auto-shutdown operation also applies to pwm steering mode as described in section 15.4.3 ?enhanced pwm auto-shutdown mode? . an auto- shutdown event will only affect pins that have pwm outputs enabled. figure 15-18: simplified steering block diagram 15.4.6.1 steering synchronization the strxsync bit of the pstrxcon register gives the user two selections of when the steering event will happen. when the strxsync bit is ? 0 ?, the steering event will happen at the end of the instruction that writes to the pstrxcon register. in this case, the output signal at the pxa, pxb, pxc and pxd pins may be an incomplete pwm waveform. this operation is useful when the user firmware needs to immediately remove a pwm signal from the pin. when the strxsync bit is ? 1 ?, the effective steering update will happen at the beginning of the next pwm period. in this case, steering on/off the pwm output will always produce a complete pwm waveform. figures 15-19 and 15-20 illustrate the timing diagrams of the pwm steering depending on the strxsync setting. note: the associated tris bits must be set to output (? 0 ?) to enable the pin output driver in order to see the pwm signal on the pin. 1 0 tris pxa pin port data pxa signal strxa 1 0 tris pxb pin port data strxb 1 0 tris pxc pin port data strxc 1 0 tris pxd pin port data strxd note 1: port outputs are configured as shown when the ccpxcon register bits pxm<1:0> = 00 and ccpxm<3:2> = 11 . 2: single pwm output requires setting at least one of the strx bits. ccpxm1 ccpxm0 ccpxm1 ccpxm0 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 203 pic18(l)f2x/45k50 15.4.7 start-up considerations when any pwm mode is used, the application hardware must use the proper external pull-up and/or pull-down resistors on the pwm output pins. the ccpxm<1:0> bits of the ccpxcon register allow the user to choose whether the pwm output signals are active-high or active-low for each pair of pwm output pins (pxa/pxc and pxb/pxd). the pwm output polarities must be selected before the pwm pin output drivers are enabled. changing the polarity configuration while the pwm pin output drivers are enabled is not recommended since it may result in damage to the application circuits. the pxa, pxb, pxc and pxd output latches may not be in the proper states when the pwm module is initialized. enabling the pwm pin output drivers at the same time as the enhanced pwm modes may cause damage to the application circuit. the enhanced pwm modes must be enabled in the proper output mode and complete a full pwm cycle before enabling the pwm pin output drivers. the completion of a full pwm cycle is indicated by the tmr2if bit of the pir1 register being set as the second pwm period begins. figure 15-19: example of steering even t at end of instruction (strxsync = 0) figure 15-20: example of steering event at beginning of instruction (strxsync = 1) note: when the microcontroller is released from reset, all of the i/o pins are in the high- impedance state. the external circuits must keep the power switch devices in the off state until the microcontroller drives the i/o pins with the proper signal levels or activates the pwm output(s). pwm p1n = pwm strx p1 pic18(l)f2x/45k50 ds30684a-page 204 ? 2012 microchip technology inc. 15.4.8 setup for eccp pwm operation using eccp1 and timer2 the following steps should be taken when configuring the eccp1 module for pwm operation using timer2: 1. configure the pwm pins to be used (p1a, p1b, p1c, and p1d): ? configure pwm outputs to be used as inputs by setting the corresponding tris bits. this prevents spurious outputs during setup. ? set the pstr1con bits for each pwm output to be used. 2. set the pwm period by loading the pr2 register. 3. configure auto-shutdown as off or select the source with the ccp1as<2:0> bits of the eccp1as register. 4. configure the auto-shutdown sources as needed: ? configure each comparator used. ? configure the comparator inputs as analog. ? configure the flt0 input pin and clear ansb0. 5. force a shutdown condition (off included): ? configure safe starting output levels by setting the default shutdown drive states with the pss1ac<1:0> and pss1bd<1:0> bits of the eccp1as register. ? clear the p1rsen bit of the pwm1con register. ? set the ccp1as bit of the eccp1as register. 6. configure the eccp1 module for the desired pwm mode and configuration by loading the ccp1con register with the appropriate values: ? select one of the available output configura- tions and direction with the p1m<1:0> bits. ? select the polarities of the pwm output signals with the ccp1m<3:0> bits. 7. set the 10-bit pwm duty cycle: ? load the eight ms bits into the ccpr1l register. ? load the two ls bits into the dc<1:0> bits of the ccp1con register. 8. for half-bridge output mode, set the dead- band delay by loading p1dc<6:0> bits of the pwm1con register with the appropriate value. 9. configure and start tmr2: ? set the tmr2 prescale value by loading the t2ckps bits of the t2con register. ? start timer2 by setting the tmr2on bit. 10. enable the eccp1/p1a, p1b, p1c and/or p1d pin outputs by clearing the respective tris bits. 11. start the pwm: ? if shutdown auto-restart is used, then set the p1rsen bit of the pwm1con register. ? if shutdown auto-restart is not used, then clear the ccp1ase bit of the eccp1as register. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 205 pic18(l)f2x/45k50 table 15-12: registers associated with enhanced pwm name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page eccp1as eccp1ase eccp1as<2:0> pss1ac<1:0> pss1bd<1:0> 210 ccp1con p1m<1:0> dc1b<1:0> ccp1m<3:0> 206 ccptmrs ? ? ? ?c2tsel ? ? c1tsel 209 intcon gie/gieh peie/giel tmr0ie int0ie iocie tmr0if int0if iocif 120 ipr1 actip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 129 ipr2 oscfip c1ip c2ip eeip bclip hlvdip tmr3ip ccp2ip 130 pie1 actie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 126 pie2 oscfie c1ie c2ie eeie bclie hlvdie tmr3ie ccp2ie 127 pir1 actif adif rcif txif sspif ccp1if tmr2if tmr1if 123 pir2 oscfif c1if c2if eeif bclif hlvdif tmr3if ccp2if 124 pmd0 ? uartmd usbmd actmd ? tmr3md tmr2md tmr1md 64 pmd1 ? msspmd ctmumd cmp2md cmp1md adcmd ccp2md ccp1md 65 pr2 timer2 period register ? pstr1con ? ? ? str1sync str1d str1c str1b str1a 211 pwm1con p1rsen p1dc<6:0> 211 t2con ? t2outps<3:0> tmr2on t2ckps<1:0> 179 tmr2 timer2 period register ? trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 156 trisc trisc7 trisc6 ? ? ?trisc2 trisc1 trisc0 156 trisd (1) trisd7 trisd6 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 156 legend: ? = unimplemented location, read as ? 0 ?. shaded bits are not used by capture mode. note 1: these registers/bits are available on pic18(l)f45k50 devices. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 206 ? 2012 microchip technology inc. 15.5 register definitions: eccp control register 15-1: ccpxcon: standard ccpx control register u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? dcxb<1:0> ccpxm<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other reset ?1? = bit is set ?0? = bit is cleared bit 7-6 unused bit 5-4 dcxb<1:0>: pwm duty cycle least significant bits capture mode: unused compare mode: unused pwm mode: these bits are the two lsbs of the pwm duty cycle. the eight msbs are found in ccprxl. bit 3-0 ccpxm<3:0>: eccpx mode select bits 0000 = capture/compare/pwm off (resets the module) 0001 = reserved 0010 = compare mode: toggle output on match 0011 = reserved 0100 = capture mode: every falling edge 0101 = capture mode: every rising edge 0110 = capture mode: every 4th rising edge 0111 = capture mode: every 16th rising edge 1000 = compare mode: set output on compare match (ccpx pin is set, ccpxif is set) 1001 = compare mode: clear output on compare match (ccpx pin is cleared, ccpxif is set) 1010 = compare mode: generate software interrupt on compare match (ccpx pin is unaffected, ccpxif is set) 1011 = compare mode: special event trigger (ccpx pin is unaffected, ccpxif is set) timerx (selected by cxtsel bits) is reset adon is set, starting a/d conversion if a/d module is enabled and trigsel is clear (1) 11xx =: pwm mode note 1: this feature is available on ccp2 only. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 207 pic18(l)f2x/45k50 register 15-2: ccpxcon: enhanced ccpx control register r/x-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pxm<1:0> dcxb<1:0> ccpxm<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other reset ?1? = bit is set ?0? = bit is cleared bit 7-6 pxm<1:0> : enhanced pwm output configuration bits if ccpxm<3:2> = 00, 01, 10 : (capture/compare modes) xx = pxa assigned as capture/compare input; pxb, pxc, pxd assigned as port pins half-bridge eccp modules (1) : if ccpxm<3:2> = 11 : (pwm modes) 0x = single output; pxa modulated; pxb assigned as port pin 1x = half-bridge output; pxa, pxb modulated with dead-band control full-bridge eccp modules (1) : if ccpxm<3:2> = 11 : (pwm modes) 00 = single output; pxa modulated; pxb, pxc, pxd assigned as port pins 01 = full-bridge output forward; pxd modulated; pxa active; pxb, pxc inactive 10 = half-bridge output; pxa, pxb modulated with dead-band control; pxc, pxd assigned as port pins 11 = full-bridge output reverse; pxb modulated; pxc active; pxa, pxd inactive bit 5-4 dcxb<1:0>: pwm duty cycle least significant bits capture mode: unused compare mode: unused pwm mode: these bits are the two lsbs of the pwm duty cycle. the eight msbs are found in ccprxl. note 1: see table 15-1 to determine full-bridge and half-bridge eccps for the device being used. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 208 ? 2012 microchip technology inc. bit 3-0 ccpxm<3:0>: eccpx mode select bits 0000 = capture/compare/pwm off (resets the module) 0001 = reserved 0010 = compare mode: toggle output on match 0011 = reserved 0100 = capture mode: every falling edge 0101 = capture mode: every rising edge 0110 = capture mode: every 4th rising edge 0111 = capture mode: every 16th rising edge 1000 = compare mode: set output on compare match (ccpx pin is set, ccpxif is set) 1001 = compare mode: clear output on compare match (ccpx pin is cleared, ccpxif is set) 1010 = compare mode: generate software interrupt on compare match (ccpx pin is unaffected, ccpxif is set) 1011 = compare mode: special event trigger (ccpx pin is unaffected, ccpxif is set) timerx is reset half-bridge eccp modules (1) : 1100 = pwm mode: pxa active-high; pxb active-high 1101 = pwm mode: pxa active-high; pxb active-low 1110 = pwm mode: pxa active-low; pxb active-high 1111 = pwm mode: pxa active-low; pxb active-low full-bridge eccp modules (1) : 1100 = pwm mode: pxa, pxc active-high; pxb, pxd active-high 1101 = pwm mode: pxa, pxc active-high; pxb, pxd active-low 1110 = pwm mode: pxa, pxc active-low; pxb, pxd active-high 1111 = pwm mode: pxa, pxc active-low; pxb, pxd active-low register 15-2: ccpxcon: enhanced ccpx control register (continued) note 1: see table 15-1 to determine full-bridge and half-bridge eccps for the device being used. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 209 pic18(l)f2x/45k50 register 15-3: ccptmrs: pwm timer selection control register 0 u-0 u-0 u-0 u-0 r/w-0 u-0 u-0 r/w-0 ? ? ? ? c2tsel ? ? c1tsel bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-4 unimplemented: read as ? 0 ? bit 3 c2tsel: ccp2 timer selection bit 0 = ccp2 ? capture/compare modes use tmr1, pwm modes use tmr2 1 = ccp2 ? capture/compare modes use tmr3, pwm modes use tmr2 bit 2-1 unimplemented: read as ? 0 ? bit 0 c1tsel: eccp1 timer selection bit 0 = eccp1 ? capture/compare modes use tmr1, pwm modes use tmr2 1 = eccp1 ? capture/compare modes use tmr3, pwm modes use tmr2 www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 210 ? 2012 microchip technology inc. register 15-4: eccpxas: ccpx auto-shutdown control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eccpxase eccpxas<2:0> pssxac<1:0> pssxbd<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 eccpxase: ccpx auto-shutdown event status bit if pxrsen = 1 ; 1 = an auto-shutdown event occurred; eccpxase bit will automatically clear when event goes away; ccpx outputs in shutdown state 0 = ccpx outputs are operating if pxrsen = 0 ; 1 = an auto-shutdown event occurred; bit must be cleared in software to restart pwm; ccpx outputs in shutdown state 0 = ccpx outputs are operating bit 6-4 eccpxas<2:0>: ccpx auto-shutdown source select bits (1) 000 = auto-shutdown is disabled 001 = comparator c1 (async_c1out) ? output high will cause shutdown event 010 = comparator c2 (async_c2out) ? output high will cause shutdown event 011 = either comparator c1 or c2 ? output high will cause shutdown event 100 =flt0 pin - low level will cause shutdown event 101 =flt0 pin or comparator c1 (async_c1out) ? low level will cause shutdown event 110 =flt0 pin or comparator c2 (async_c2out) ? low level will cause shutdown event 111 =flt0 pin or comparators c1 or c2 ? low level will cause shutdown event bit 3-2 pssxac<1:0>: pins pxa and pxc shutdown state control bits 00 = drive pins pxa and pxc to ? 0 ? 01 = drive pins pxa and pxc to ? 1 ? 1x = pins pxa and pxc tri-state bit 1-0 pssxbd<1:0>: pins pxb and pxd shutdown state control bits 00 = drive pins pxb and pxd to ? 0 ? 01 = drive pins pxb and pxd to ? 1 ? 1x = pins pxb and pxd tri-state note 1: if c1sync or c2sync bits in the cm2con1 register are enabled, the shutdown will be delayed by timer1. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 211 pic18(l)f2x/45k50 register 15-5: pwmxcon: enhanced pwm control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pxrsen pxdc<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 pxrsen: pwm restart enable bit 1 = upon auto-shutdown, the eccpxase bit clears automatically once the shutdown event goes away; the pwm restarts automatically 0 = upon auto-shutdown, eccpxase must be cleared in software to restart the pwm bit 6-0 pxdc<6:0>: pwm delay count bits pxdcx = number of f osc /4 (4 * t osc ) cycles between the scheduled time when a pwm signal should transition active and the actual time it transitions active register 15-6: pstrxcon: pwm steering control register (1) u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 ? ? ? strxsync strxd strxc strxb strxa bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-5 unimplemented: read as ? 0 ? bit 4 strxsync: steering sync bit 1 = output steering update occurs on next pwm period 0 = output steering update occurs at the beginning of the instruction cycle boundary bit 3 strxd: steering enable bit d 1 = pxd pin has the pwm waveform with polarity control from ccpxm<1:0> 0 = pxd pin is assigned to port pin bit 2 strxc: steering enable bit c 1 = pxc pin has the pwm waveform with polarity control from ccpxm<1:0> 0 = pxc pin is assigned to port pin bit 1 strxb: steering enable bit b 1 = pxb pin has the pwm waveform with polarity control from ccpxm<1:0> 0 = pxb pin is assigned to port pin bit 0 strxa: steering enable bit a 1 = pxa pin has the pwm waveform with polarity control from ccpxm<1:0> 0 = pxa pin is assigned to port pin note 1: the pwm steering mode is available only when the ccpxcon register bits ccpxm<3:2> = 11 and pxm<1:0> = 00 . www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 212 ? 2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 213 pic18(l)f2x/45k50 16.0 master synchronous serial port (mssp) module 16.1 module overview the master synchronous serial port (mssp) module is a serial interface useful for communicating with other peripheral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, display drivers, a/d converters, etc. the mssp module can operate in one of two modes: ? serial peripheral interface (spi) ? inter-integrated circuit (i 2 c?) the spi interface supports the following modes and features: ?master mode ? slave mode ? clock parity ? slave select synchronization (slave mode only) ? daisy chain connection of slave devices figure 16-1 is a block diagram of the spi interface module. figure 16-1: mssp block diagram (spi mode) ( ) read write data bus sspxsr reg sspxm<3:0> bit 0 shift clock ss control enable edge select clock select tmr2 output t osc prescaler 4, 16, 64 2 edge select 2 (ckp, cke) 4 tris bit sdo sspxbuf reg sdi ss sck baud rate generator (sspxadd) www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 214 ? 2012 microchip technology inc. the i 2 c interface supports the following modes and features: ?master mode ? slave mode ? byte nacking (slave mode) ? limited multi-master support ? 7-bit and 10-bit addressing ? start and stop interrupts ? interrupt masking ? clock stretching ? bus collision detection ? general call address matching ?address masking ? address hold and data hold modes ? selectable sda hold times figure 16-2 is a block diagram of the i 2 c interface module in master mode. figure 16-3 is a diagram of the i 2 c interface module in slave mode. figure 16-2: mssp block diagram (i 2 c? master mode) read write sspxsr start bit, stop bit, start bit detect, sspxbuf internal data bus set/reset: s, p, sspxstat, wcol, sspov shift clock msb lsb sda acknowledge generate (sspxcon2) stop bit detect write collision detect clock arbitration state counter for end of xmit/rcv scl scl in bus collision sda in receive enable (rcen) clock cntl clock arbitrate/bcol detect (hold off clock source) [sspxm 3:0] baud rate reset sen, pen (sspxcon2) generator (sspxadd) address match detect set sspif, bclif www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 215 pic18(l)f2x/45k50 figure 16-3: mssp block diagram (i 2 c? slave mode) read write sspxsr reg match detect sspxadd reg start and stop bit detect sspxbuf reg internal data bus addr match set, reset s, p bits (sspxstat reg) scl sda shift clock msb lsb sspxmsk reg www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 216 ? 2012 microchip technology inc. 16.2 spi mode overview the serial peripheral interface (spi) bus is a synchronous serial data communication bus that operates in full-duplex mode. devices communicate in a master/slave environment where the master device initiates the communication. a slave device is controlled through a chip select known as slave select. the spi bus specifies four signal connections: ? serial clock (sck) ? serial data out (sdo) ? serial data in (sdi) ? slave select (ss ) figure 16-1 shows the block diagram of the mssp module when operating in spi mode. the spi bus operates with a single master device and one or more slave devices. when multiple slave devices are used, an independent slave select connection is required from the master device to each slave device. figure 16-4 shows a typical connection between a master device and multiple slave devices. the master selects only one slave at a time. most slave devices have tri-state outputs so their output signal appears disconnected from the bus when they are not selected. transmissions involve two shift registers, eight bits in size, one in the master and one in the slave. with either the master or the slave device, data is always shifted out one bit at a time, with the most significant bit (msb) shifted out first. at the same time, a new least significant bit (lsb) is shifted into the same register. figure 16-5 shows a typical connection between two processors configured as master and slave devices. data is shifted out of both shift registers on the programmed clock edge and latched on the opposite edge of the clock. the master device transmits information out on its sdo output pin which is connected to, and received by, the slave?s sdi input pin. the slave device transmits infor- mation out on its sdo output pin, which is connected to, and received by, the master?s sdi input pin. to begin communication, the master device first sends out the clock signal. both the master and the slave devices should be configured for the same clock polarity. the master device starts a transmission by sending out the msb from its shift register. the slave device reads this bit from that same line and saves it into the lsb position of its shift register. during each spi clock cycle, a full-duplex data transmission occurs. this means that at the same time, the slave device is sending out the msb from its shift register and the master device is reading this bit from that same line and saving it as the lsb of its shift register. after eight bits have been shifted out, the master and slave have exchanged register values. if there is more data to exchange, the shift registers are loaded with new data and the process repeats itself. whether the data is meaningful or not (dummy data), depends on the application software. this leads to three scenarios for data transmission: ? master sends useful data and slave sends dummy data. ? master sends useful data and slave sends useful data. ? master sends dummy data and slave sends useful data. transmissions may involve any number of clock cycles. when there is no more data to be transmitted, the master stops sending the clock signal and it deselects the slave. every slave device connected to the bus that has not been selected through its slave select line must disre- gard the clock and transmission signals and must not transmit out any data of its own. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 217 pic18(l)f2x/45k50 figure 16-4: spi master and multiple slave connection 16.2.1 spi mode registers the mssp module has five registers for spi mode operation. these are: ? mssp status register (sspxstat) ? mssp control register 1 (sspxcon1) ? mssp control register 3 (sspxcon3) ? mssp data buffer register (sspxbuf) ? mssp address register (sspxadd) ? mssp shift register (sspxsr) (not directly accessible) sspxcon1 and sspxstat are the control and status registers in spi mode operation. the sspxcon1 register is readable and writable. the lower six bits of the sspxstat are read-only. the upper two bits of the sspxstat are read/write. in one spi master mode, sspxadd can be loaded with a value used in the baud rate generator. more information on the baud rate generator is available in section 16.7 ?baud rate generator? . sspxsr is the shift register used for shifting data in and out. sspxbuf provides indirect access to the sspxsr register. sspxbuf is the buffer register to which data bytes are written, and from which data bytes are read. in receive operations, sspxsr and sspxbuf together create a buffered receiver. when sspxsr receives a complete byte, it is transferred to sspxbuf and the sspif interrupt is set. during transmission, the sspxbuf is not buffered. a write to sspxbuf will write to both sspxbuf and sspxsr. 16.2.2 spi mode operation when initializing the spi, several options need to be specified. this is done by programming the appropriate control bits (sspxcon1<5:0> and sspxstat<7:6>). these control bits allow the following to be specified: ? master mode (sck is the clock output) ? slave mode (sck is the clock input) ? clock polarity (idle state of sck) ? data input sample phase (middle or end of data output time) ? clock edge (output data on rising/falling edge of sck) ? clock rate (master mode only) ? slave select mode (slave mode only) to enable the serial port, sspx enable bit, sspxen of the sspxcon1 register, must be set. to reset or recon- figure spi mode, clear the sspxen bit, re-initialize the sspxconx registers and then set the sspxen bit. this configures the sdi, sdo, sck and ss pins as serial port pins. for the pins to behave as the serial port function, some must have their data direction bits (in the tris register) appropriately programmed as follows: ? sdi must have corresponding tris bit set ? sdo must have corresponding tris bit cleared ? sck (master mode) must have corresponding tris bit cleared ? sck (slave mode) must have corresponding tris bit set ?ss must have corresponding tris bit set spi master sclk sdo sdi general i/o general i/o general i/o sclk sdi sdo ss spi slave #1 sclk sdi sdo ss spi slave #2 sclk sdi sdo ss spi slave #3 www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 218 ? 2012 microchip technology inc. any serial port function that is not desired may be overridden by programming the corresponding data direction (tris) register to the opposite value. the mssp consists of a transmit/receive shift register (sspxsr) and a buffer register (sspxbuf). the sspxsr shifts the data in and out of the device, msb first. the sspxbuf holds the data that was written to the sspxsr until the received data is ready. once the eight bits of data have been received, that byte is moved to the sspxbuf register. then, the buffer full detect bit, bf of the sspxstat register, and the interrupt flag bit, sspif, are set. this double-buffering of the received data (sspxbuf) allows the next byte to start reception before reading the data that was just received. any write to the sspxbuf register during transmission/reception of data will be ignored and the write collision detect bit, wcol of the sspxcon1 register, will be set. user software must clear the wcol bit to allow the following write(s) to the sspxbuf register to complete successfully. when the application software is expecting to receive valid data, the sspxbuf should be read before the next byte of data to transfer is written to the sspxbuf. the buffer full bit, bf of the sspxstat register, indicates when sspxbuf has been loaded with the received data (transmission is complete). when the sspxbuf is read, the bf bit is cleared. this data may be irrelevant if the spi is only a transmitter. generally, the mssp interrupt is used to determine when the transmission/reception has completed. if the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. figure 16-5: spi mast er/slave connection serial input buffer (sspx) shift register (sspxsr) msb lsb sdo sdi processor 1 sck spi master sspxm<3:0> = 00xx serial input buffer (sspxbuf) shift register (sspxsr) lsb msb sdi sdo processor 2 sck spi slave sspxm<3:0> = 010x serial clock ss slave select general i/o (optional) = 1010 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 219 pic18(l)f2x/45k50 16.2.3 spi master mode the master can initiate the data transfer at any time because it controls the sck line. the master determines when the slave (processor 2, figure 16-5 ) is to broadcast data by the software protocol. in master mode, the data is transmitted/received as soon as the sspxbuf register is written to. if the spi is only going to receive, the sdo output could be dis- abled (programmed as an input). the sspxsr register will continue to shift in the signal present on the sdi pin at the programmed clock rate. as each byte is received, it will be loaded into the sspxbuf register as if a normal received byte (interrupts and status bits appropriately set). the clock polarity is selected by appropriately programming the ckp bit of the sspxcon1 register and the cke bit of the sspxstat register. this then, would give waveforms for spi communication as shown in figure 16-6 , figure 16-8 and figure 16-9 , where the msb is transmitted first. in master mode, the spi clock rate (bit rate) is user programmable to be one of the following: ?f osc /4 (or t cy ) ?f osc /16 (or 4 * t cy ) ?f osc /64 (or 16 * t cy ) ? timer2 output/2 ?f osc /(4 * (sspxadd + 1)) figure 16-6 shows the waveforms for master mode. when the cke bit is set, the sdo data is valid before there is a clock edge on sck. the change of the input sample is shown based on the state of the smp bit. the time when the sspxbuf is loaded with the received data is shown. figure 16-6: spi mode waveform (master mode) sck (ckp = 0 sck (ckp = 1 sck (ckp = 0 sck (ckp = 1 4 clock modes input sample input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 sdi sspif (smp = 1 ) (smp = 0 ) (smp = 1 ) cke = 1 ) cke = 0 ) cke = 1 ) cke = 0 ) (smp = 0 ) write to sspxbuf sspxsr to sspxbuf sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (cke = 0 ) (cke = 1 ) bit 0 www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 220 ? 2012 microchip technology inc. 16.2.4 spi slave mode in slave mode, the data is transmitted and received as external clock pulses appear on sck. when the last bit is latched, the sspif interrupt flag bit is set. before enabling the module in spi slave mode, the clock line must match the proper idle state. the clock line can be observed by reading the sck pin. the idle state is determined by the ckp bit of the sspxcon1 register. while in slave mode, the external clock is supplied by the external clock source on the sck pin. this external clock must meet the minimum high and low times as specified in the electrical specifications. while in sleep mode, the slave can transmit/receive data. the shift register is clocked from the sck pin input and when a byte is received, the device will gen- erate an interrupt. if enabled, the device will wake-up from sleep. 16.2.4.1 daisy-chain configuration the spi bus can sometimes be connected in a daisy- chain configuration. the first slave output is connected to the second slave input, the second slave output is connected to the third slave input, and so on. the final slave output is connected to the master input. each slave sends out, during a second group of clock pulses, an exact copy of what was received during the first group of clock pulses. the whole chain acts as one large communication shift register. the daisy- chain feature only requires a single slave select line from the master device. figure 16-7 shows the block diagram of a typical daisy-chain connection when operating in spi mode. in a daisy-chain configuration, only the most recent byte on the bus is required by the slave. setting the boen bit of the sspxcon3 register will enable writes to the sspxbuf register, even if the previous byte has not been read. this allows the software to ignore data that may not apply to it. 16.2.5 slave select synchronization the slave select can also be used to synchronize communication. the slave select line is held high until the master device is ready to communicate. when the slave select line is pulled low, the slave knows that a new transmission is starting. if the slave fails to receive the communication properly, it will be reset at the end of the transmission, when the slave select line returns to a high state. the slave is then ready to receive a new transmission when the slave select line is pulled low again. if the slave select line is not used, there is a risk that the slave will even- tually become out of sync with the master. if the slave misses a bit, it will always be one bit off in future trans- missions. use of the slave select line allows the slave and master to align themselves at the beginning of each transmission. the ss pin allows a synchronous slave mode. the spi must be in slave mode with ss pin control enabled (sspxcon1<3:0> = 0100 ). when the ss pin is low, transmission and reception are enabled and the sdo pin is driven. when the ss pin goes high, the sdo pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. external pull-up/pull-down resistors may be desirable depending on the applica- tion. when the spi module resets, the bit counter is forced to ? 0 ?. this can be done by either forcing the ss pin to a high level or clearing the sspxen bit. note 1: when the spi is in slave mode with ss pin control enabled (sspxcon1<3:0> = 0100 ), the spi module will reset if the ss pin is set to v dd . 2: when the spi is used in slave mode with cke set; the user must enable ss pin control. 3: while operated in spi slave mode the smp bit of the sspxstat register must remain clear. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 221 pic18(l)f2x/45k50 figure 16-7: spi daisy-chain connection figure 16-8: slave sele ct synchronous waveform spi master sclk sdo sdi general i/o sclk sdi sdo ss spi slave #1 sclk sdi sdo ss spi slave #2 sclk sdi sdo ss spi slave #3 sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 sdo bit 7 bit 6 bit 7 sspif interrupt cke = 0 ) cke = 0 ) write to sspxbuf sspxsr to sspxbuf ss flag bit 0 bit 7 bit 0 bit 6 sspxbuf to sspxsr shift register sspxsr and bit count are reset www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 222 ? 2012 microchip technology inc. figure 16-9: spi mode wavefo rm (slave mode with cke = 0 ) figure 16-10: spi mode waveform (slave mode with cke = 1 ) sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspif interrupt cke = 0 ) cke = 0 ) write to sspxbuf sspxsr to sspxbuf ss flag optional bit 0 detection active write collision valid sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspif interrupt cke = 1 ) cke = 1 ) write to sspxbuf sspxsr to sspxbuf ss flag not optional write collision detection active valid www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 223 pic18(l)f2x/45k50 16.2.6 spi operation in sleep mode in spi master mode, module clocks may be operating at a different speed than when in full-power mode; in the case of the sleep mode, all clocks are halted. special care must be taken by the user when the mssp clock is much faster than the system clock. in slave mode, when mssp interrupts are enabled, after the master completes sending data, an mssp interrupt will wake the controller from sleep. if an exit from sleep mode is not desired, mssp interrupts should be disabled. in spi master mode, when the sleep mode is selected, all module clocks are halted and the transmission/ reception will remain in that state until the device wakes. after the device returns to run mode, the module will resume transmitting and receiving data. in spi slave mode, the spi transmit/receive shift register operates asynchronously to the device. this allows the device to be placed in sleep mode and data to be shifted into the spi transmit/receive shift register. when all eight bits have been received, the mssp interrupt flag bit will be set and if enabled, will wake the device. table 16-1: registers associ ated with spi operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ansela ? ? ansa5 ? ansa3 ansa2 ansa1 ansa0 154 anselb ? ? ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 155 intcon gie/gieh peie/giel tmr0ie int0ie iocie tmr0if int0if iocif 120 ipr1 actip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 129 pie1 actie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 126 pir1 actif adif rcif txif sspif ccp1if tmr2if tmr1if 123 pmd1 ? msspmd ctmumd cmp2md cmp1md adcmd ccp2md ccp1md 65 ssp1buf ssp1 receive buffer/transmit register ? ssp1con1 wcol sspov sspen ckp sspm<3:0> 262 ssp1con3 acktim pcie scie boen sdaht sbcde ahen dhen 265 ssp1stat smp cke d/a p s r/w ua bf 261 trisa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 156 trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 156 trisc trisc7 trisc6 ? ? ? trisc2 trisc1 trisc0 156 legend: shaded bits are not used by the mssp in spi mode. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 224 ? 2012 microchip technology inc. 16.3 i 2 c mode overview the inter-integrated circuit bus (i 2 c) is a multi-master serial data communication bus. devices communicate in a master/slave environment where the master devices initiate the communication. a slave device is controlled through addressing. the i 2 c bus specifies two signal connections: ? serial clock (scl) ? serial data (sda) figure 16-11 shows the block diagram of the mssp module when operating in i 2 c mode. both the scl and sda connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply voltage. pulling the line to ground is considered a logical zero and letting the line float is considered a logical one. figure 16-11 shows a typical connection between two processors configured as master and slave devices. the i 2 c bus can operate with one or more master devices and one or more slave devices. there are four potential modes of operation for a given device: ? master transmit mode (master is transmitting data to a slave) ? master receive mode (master is receiving data from a slave) ?slave transmit mode (slave is transmitting data to a master) ? slave receive mode (slave is receiving data from the master) to begin communication, a master device starts out in master transmit mode. the master device sends out a start bit followed by the address byte of the slave it intends to communicate with. this is followed by a sin- gle read/write bit, which determines whether the mas- ter intends to transmit to or receive data from the slave device. if the requested slave exists on the bus, it will respond with an acknowledge bit, otherwise known as an ack . the master then continues in either transmit mode or receive mode and the slave continues in the comple- ment, either in receive mode or transmit mode, respectively. a start bit is indicated by a high-to-low transition of the sda line while the scl line is held high. address and data bytes are sent out, most significant bit (msb) first. the read/write bit is sent out as a logical one when the master intends to read data from the slave, and is sent out as a logical zero when it intends to write data to the slave. figure 16-11: i 2 c? master/ slave connection the acknowledge bit (ack ) is an active-low signal, which holds the sda line low to indicate to the transmitter that the slave device has received the transmitted data and is ready to receive more. the transition of data bits is always performed while the scl line is held low. transitions that occur while the scl line is held high are used to indicate start and stop bits. if the master intends to write to the slave, then it repeatedly sends out a byte of data, with the slave responding after each byte with an ack bit. in this example, the master device is in master transmit mode and the slave is in slave receive mode. if the master intends to read from the slave, then it repeatedly receives a byte of data from the slave, and responds after each byte with an ack bit. in this example, the master device is in master receive mode and the slave is slave transmit mode. on the last byte of data communicated, the master device may end the transmission by sending a stop bit. if the master device is in receive mode, it sends the stop bit in place of the last ack bit. a stop bit is indicated by a low-to-high transition of the sda line while the scl line is held high. in some cases, the master may want to maintain con- trol of the bus and re-initiate another transmission. if so, the master device may send another start bit in place of the stop bit or last ack bit when it is in receive mode. the i 2 c bus specifies three message protocols; ? single message where a master writes data to a slave. ? single message where a master reads data from a slave. ? combined message where a master initiates a minimum of two writes, or two reads, or a combination of writes and reads, to one or more slaves. master scl sda scl sda slave v dd v dd www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 225 pic18(l)f2x/45k50 when one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. this detection, when used on the scl line, is called clock stretching. clock stretching give slave devices a mechanism to control the flow of data. when this detection is used on the sda line, it is called arbitration. arbitration ensures that there is only one master device communicating at any single time. 16.3.1 clock stretching when a slave device has not completed processing data, it can delay the transfer of more data through the process of clock stretching. an addressed slave device may hold the scl clock line low after receiving or sending a bit, indicating that it is not yet ready to continue. the master that is communicating with the slave will attempt to raise the scl line in order to transfer the next bit, but will detect that the clock line has not yet been released. because the scl connection is open-drain, the slave has the ability to hold that line low until it is ready to continue communicating. clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming data. 16.3.2 arbitration each master device must monitor the bus for start and stop bits. if the device detects that the bus is busy, it cannot begin a new message until the bus returns to an idle state. however, two master devices may try to initiate a transmission on or about the same time. when this occurs, the process of arbitration begins. each transmitter checks the level of the sda data line and compares it to the level that it expects to find. the first transmitter to observe that the two levels do not match, loses arbitration, and must stop transmitting on the sda line. for example, if one transmitter holds the sda line to a logical one (lets it float) and a second transmitter holds it to a logical zero (pulls it low), the result is that the sda line will be low. the first transmitter then observes that the level of the line is different than expected and concludes that another transmitter is communicating. the first transmitter to notice this difference is the one that loses arbitration and must stop driving the sda line. if this transmitter is also a master device, it also must stop driving the scl line. it then can monitor the lines for a stop condition before trying to reissue its transmission. in the meantime, the other device that has not noticed any difference between the expected and actual levels on the sda line continues with its original transmission. it can do so without any compli- cations, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message. slave transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. if two master devices are sending a message to two different slave devices at the address stage, the master sending the lower slave address always wins arbitration. when two master devices send messages to the same slave address, and addresses can sometimes refer to multiple slaves, the arbitration process must continue into the data stage. arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 226 ? 2012 microchip technology inc. 16.4 i 2 c mode operation all mssp i 2 c communication is byte oriented and shifted out msb first. six sfr registers and two interrupt flags interface the module with the pic ? microcontroller and user software. two pins, sda and scl, are exercised by the module to communicate with other external i 2 c devices. 16.4.1 byte format all communication in i 2 c is done in 9-bit segments. a byte is sent from a master to a slave or vice-versa, followed by an acknowledge bit sent back. after the 8th falling edge of the scl line, the device outputting data on the sda changes that pin to an input and reads in an acknowledge value on the next clock pulse. the clock signal, scl, is provided by the master. data is valid to change while the scl signal is low, and sampled on the rising edge of the clock. changes on the sda line while the scl line is high define special conditions on the bus, explained below. 16.4.2 definition of i 2 c terminology there is language and terminology in the description of i 2 c communication that have definitions specific to i 2 c. that word usage is defined below and may be used in the rest of this document without explana- tion. this table was adapted from the phillips i 2 c specification. 16.4.3 sda and scl pins selection of any i 2 c mode with the sspxen bit set, forces the scl and sda pins to be open-drain. these pins should be set by the user to inputs by setting the appropriate tris bits. 16.4.4 sda hold time the hold time of the sda pin is selected by the sdaht bit of the sspxcon3 register. hold time is the time sda is held valid after the falling edge of scl. setting the sdaht bit selects a longer 300 ns minimum hold time and may help on buses with large capacitance. table 16-2: i 2 c? bus terms note: data is tied to output zero when an i 2 c mode is enabled. term description transmitter the device which shifts data out onto the bus. receiver the device which shifts data in from the bus. master the device that initiates a transfer, generates clock signals and terminates a transfer. slave the device addressed by the master. multi-master a bus with more than one device that can initiate data transfers. arbitration procedure to ensure that only one master at a time controls the bus. winning arbitration ensures that the message is not corrupted. synchronization procedure to synchronize the clocks of two or more devices on the bus. idle no master is controlling the bus, and both sda and scl lines are high. active any time one or more master devices are controlling the bus. addressed slave slave device that has received a matching address and is actively being clocked by a master. matching address address byte that is clocked into a slave that matches the value stored in sspxadd. write request slave receives a matching address with r/w bit clear, and is ready to clock in data. read request master sends an address byte with the r/w bit set, indicating that it wishes to clock data out of the slave. this data is the next and all following bytes until a restart or stop. clock stretching when a device on the bus holds scl low to stall communication. bus collision any time the sda line is sampled low by the module while it is out- putting and expected high state. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 227 pic18(l)f2x/45k50 16.4.5 start condition the i 2 c specification defines a start condition as a transition of sda from a high-to-low state while scl line is high. a start condition is always generated by the master and signifies the transition of the bus from an idle to an active state. figure 16-10 shows wave forms for start and stop conditions. a bus collision can occur on a start condition if the module samples the sda line low before asserting it low. this does not conform to the i 2 c specification that states no bus collision can occur on a start. 16.4.6 stop condition a stop condition is a transition of the sda line from a low-to-high state while the scl line is high. 16.4.7 restart condition a restart is valid any time that a stop would be valid. a master can issue a restart if it wishes to hold the bus after terminating the current transfer. a restart has the same effect on the slave that a start would, resetting all slave logic and preparing it to clock in an address. the master may want to address the same or another slave. in 10-bit addressing slave mode a restart is required for the master to clock data out of the addressed slave. once a slave has been fully addressed, matching both high and low address bytes, the master can issue a restart and the high address byte with the r/w bit set. the slave logic will then hold the clock and prepare to clock out data. after a full match with r/w clear in 10-bit mode, a prior match flag is set and maintained. until a stop condition, a high address with r/w clear, or high address match fails. 16.4.8 start/stop condition interrupt masking the scie and pcie bits of the sspxcon3 register can enable the generation of an interrupt in slave modes that do not typically support this function. slave modes where interrupt on start and stop detect are already enabled, these bits will have no effect. figure 16-12: i 2 c? start and stop conditions figure 16-13: i 2 c? restart condition note: at least one scl low time must appear before a stop is valid, therefore, if the sda line goes low then high again while the scl line stays high, only the start condition is detected. sda scl p stop condition s start condition change of data allowed change of data allowed restart condition sr change of data allowed change of data allowed www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 228 ? 2012 microchip technology inc. 16.4.9 acknowledge sequence the 9th scl pulse for any transferred byte in i 2 c is dedicated as an acknowledge. it allows receiving devices to respond back to the transmitter by pulling the sda line low. the transmitter must release control of the line during this time to shift in the response. the acknowledge (ack ) is an active-low signal, pulling the sda line low indicated to the transmitter that the device has received the transmitted data and is ready to receive more. the result of an ack is placed in the ackstat bit of the sspxcon2 register. slave software, when the ahen and dhen bits are set, allow the user to set the ack value sent back to the transmitter. the ackdt bit of the sspxcon2 register is set/cleared to determine the response. slave hardware will generate an ack response if the ahen and dhen bits of the sspxcon3 register are clear. there are certain conditions where an ack will not be sent by the slave. if the bf bit of the sspxstat register or the sspov bit of the sspxcon1 register are set when a byte is received. when the module is addressed, after the 8th falling edge of scl on the bus, the acktim bit of the sspxcon3 register is set. the acktim bit indicates the acknowledge time of the active bus. the acktim status bit is only active when the ahen bit or dhen bit is enabled. 16.5 i 2 c slave mode operation the mssp slave mode operates in one of four modes selected in the sspxm bits of sspxcon1 register. the modes can be divided into 7-bit and 10-bit addressing mode. 10-bit addressing modes operate the same as 7-bit with some additional overhead for handling the larger addresses. modes with start and stop bit interrupts operated the same as the other modes with sspif additionally get- ting set upon detection of a start, restart, or stop condition. 16.5.1 slave mode addresses the sspxadd register ( register 16-6 ) contains the slave mode address. the first byte received after a start or restart condition is compared against the value stored in this register. if the byte matches, the value is loaded into the sspxbuf register and an interrupt is generated. if the value does not match, the module goes idle and no indication is given to the software that anything happened. the sspx mask register ( register 16-5 ) affects the address matching process. see section 16.5.9 ?sspx mask register? for more information. 16.5.1.1 i 2 c slave 7-bit addressing mode in 7-bit addressing mode, the lsb of the received data byte is ignored when determining if there is an address match. 16.5.1.2 i 2 c slave 10-bit addressing mode in 10-bit addressing mode, the first received byte is compared to the binary value of ?1 1 1 1 0 a9 a8 0?. a9 and a8 are the two msb of the 10-bit address and stored in bits 2 and 1 of the sspxadd register. after the acknowledge of the high byte the ua bit is set and scl is held low until the user updates sspxadd with the low address. the low address byte is clocked in and all eight bits are compared to the low address value in sspxadd. even if there is not an address match; sspif and ua are set, and scl is held low until sspxadd is updated to receive a high byte again. when sspxadd is updated the ua bit is cleared. this ensures the module is ready to receive the high address byte on the next communication. a high and low address match as a write request is required at the start of all 10-bit addressing communication. a transmission can be initiated by issuing a restart once the slave is addressed, and clocking in the high address with the r/w bit set. the slave hardware will then acknowledge the read request and prepare to clock out data. this is only valid for a slave after it has received a complete high and low address byte match. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 229 pic18(l)f2x/45k50 16.5.2 slave reception when the r/w bit of a matching received address byte is clear, the r/w bit of the sspxstat register is cleared. the received address is loaded into the sspxbuf register and acknowledged. when the overflow condition exists for a received address, then not acknowledge is given. an overflow condition is defined as either bit bf of the sspxstat register is set, or bit sspov of the sspxcon1 register is set. the boen bit of the sspxcon3 register modi- fies this operation. for more information see register 16-4 . an mssp interrupt is generated for each transferred data byte. flag bit, sspif, must be cleared by software. when the sen bit of the sspxcon2 register is set, scl will be held low (clock stretch) following each received byte. the clock must be released by setting the ckp bit of the sspxcon1 register, except sometimes in 10-bit mode. see section 16.2.3 ?spi master mode? for more detail. 16.5.2.1 7-bit addressing reception this section describes a standard sequence of events for the mssp module configured as an i 2 c slave in 7-bit addressing mode. all decisions made by hardware or software and their effect on reception. figure 16-13 and figure 16-14 is used as a visual reference for this description. this is a step by step process of what typically must be done to accomplish i 2 c communication. 1. start bit detected. 2. s bit of sspxstat is set; sspif is set if interrupt on start detect is enabled. 3. matching address with r/w bit clear is received. 4. the slave pulls sda low sending an ack to the master, and sets sspif bit. 5. software clears the sspif bit. 6. software reads received address from sspxbuf clearing the bf flag. 7. if sen = 1 ; slave software sets ckp bit to release the scl line. 8. the master clocks out a data byte. 9. slave drives sda low sending an ack to the master, and sets sspif bit. 10. software clears sspif. 11. software reads the received byte from sspxbuf clearing bf. 12. steps 8-12 are repeated for all received bytes from the master. 13. master sends stop condition, setting p bit of sspxstat, and the bus goes idle. 16.5.2.2 7-bit reception with ahen and dhen slave device reception with ahen and dhen set operate the same as without these options with extra interrupts and clock stretching added after the 8th fall- ing edge of scl. these additional interrupts allow the slave software to decide whether it wants to ack the receive address or data byte, rather than the hard- ware. this functionality adds support for pmbus? that was not present on previous versions of this module. this list describes the steps that need to be taken by slave software to use these options for i 2 c communication. figure 16-15 displays a module using both address and data holding. figure 16-16 includes the operation with the sen bit of the sspxcon2 register set. 1. s bit of sspxstat is set; sspif is set if interrupt on start detect is enabled. 2. matching address with r/w bit clear is clocked in. sspif is set and ckp cleared after the 8th falling edge of scl. 3. slave clears the sspif. 4. slave can look at the acktim bit of the sspxcon3 register to determine if the sspif was after or before the ack. 5. slave reads the address value from sspxbuf, clearing the bf flag. 6. slave sets ack value clocked out to the master by setting ackdt. 7. slave releases the clock by setting ckp. 8. sspif is set after an ack , not after a nack. 9. if sen = 1 the slave hardware will stretch the clock after the ack. 10. slave clears sspif. 11. sspif set and ckp cleared after 8th falling edge of scl for a received data byte. 12. slave looks at acktim bit of sspxcon3 to determine the source of the interrupt. 13. slave reads the received data from sspxbuf clearing bf. 14. steps 7-14 are the same for each received data byte. 15. communication is ended by either the slave sending an ack = 1 , or the master sending a stop condition. if a stop is sent and interrupt on stop detect is disabled, the slave will only know by polling the p bit of the sststat register. note: sspif is still set after the 9th falling edge of scl even if there is no clock stretching and bf has been cleared. only if nack is sent to master is sspif not set. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 230 ? 2012 microchip technology inc. figure 16-14: i 2 c slave, 7-bit address, reception (sen = 0 , ahen = 0 , dhen = 0 ) receiving address ack receiving data ack receiving data ack = 1 a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl sspif bf sspov 12345678 12345678 12345678 9 9 9 ack is not sent. sspov set because sspxbuf is still full. cleared by software first byte of data is available in sspxbuf sspxbuf is read sspif set on 9th falling edge of scl cleared by software p bus master sends stop condition s from slave to master www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 231 pic18(l)f2x/45k50 figure 16-15: i 2 c slave, 7-bit address, reception (sen = 1 , ahen = 0 , dhen = 0 ) sen sen a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl 123456789 123456789 123456789 p sspif set on 9th scl is not held ckp is written to ? 1 ? in software, ckp is written to ? 1 ? in software, ack low because falling edge of scl releasing scl ack is not sent. bus master sends ckp sspov bf sspif sspov set because sspxbuf is still full. cleared by software first byte of data is available in sspxbuf ack = 1 cleared by software sspxbuf is read clock is held low until ckp is set to ? 1 ? releasing scl stop condition s ack ack receive address receive data receive data r/w= 0 www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 232 ? 2012 microchip technology inc. figure 16-16: i 2 c slave, 7-bit address, reception (sen = 0 , ahen = 1 , dhen = 1 ) receiving address receiving data received data p a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl bf ckp s p 12 3 4 56 7 8 9 12345678 9 12345678 master sends stop condition s data is read from sspxbuf cleared by software sspif is set on 9th falling edge of scl, after ack ckp set by software, scl is released slave software 9 acktim cleared by hardware in 9th rising edge of scl sets ackdt to not ack when dhen= 1 : ckp is cleared by hardware on 8th falling edge of scl slave software clears ackdt to ack the received byte acktim set by hardware on 8th falling edge of scl when ahen= 1 : ckp is cleared by hardware and scl is stretched address is read from ssbuf acktim set by hardware on 8th falling edge of scl ack master releases sda to slave for ack sequence no interrupt after not ack from slave ack = 1 ack ackdt acktim sspif if ahen = 1 : sspif is set www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 233 pic18(l)f2x/45k50 figure 16-17: i 2 c slave, 7-bit address, reception (sen = 1 , ahen = 1 , dhen = 1 ) receiving address receive data receive data a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl sspif bf ackdt ckp s p ack s 12 34 5678 9 12 3 4567 8 9 12 345 67 8 9 ack ack cleared by software acktim is cleared by hardware sspxbuf can be set by software, read any time before next byte is loaded release scl on 9th rising edge of scl received address is loaded into sspxbuf slave software clears ackdt to ack r/w = 0 master releases sda to slave for ack sequence the received byte when ahen = 1 ; on the 8th falling edge of scl of an address byte, ckp is cleared acktim is set by hardware on 8th falling edge of scl when dhen = 1 ; on the 8th falling edge of scl of a received data byte, ckp is cleared received data is available on sspxbuf slave sends not ack ckp is not cleared if not ack p master sends stop condition no interrupt after if not ack from slave acktim www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 234 ? 2012 microchip technology inc. 16.5.3 slave transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspxstat register is set. the received address is loaded into the sspxbuf register, and an ack pulse is sent by the slave on the ninth bit. following the ack , slave hardware clears the ckp bit and the scl pin is held low (see section 16.5.6 ?clock stretching? for more detail). by stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. the transmit data must be loaded into the sspxbuf register which also loads the sspxsr register. then the scl pin should be released by setting the ckp bit of the sspxcon1 register. the eight data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time. the ack pulse from the master-receiver is latched on the rising edge of the ninth scl input pulse. this ack value is copied to the ackstat bit of the sspxcon2 register. if ackstat is set (not ack ), then the data transfer is complete. in this case, when the not ack is latched by the slave, the slave goes idle and waits for another occurrence of the start bit. if the sda line was low (ack ), the next transmit data must be loaded into the sspxbuf register. again, the scl pin must be released by setting bit ckp. an mssp interrupt is generated for each data transfer byte. the sspif bit must be cleared by software and the sspxstat register is used to determine the status of the byte. the sspif bit is set on the falling edge of the ninth clock pulse. 16.5.3.1 slave mode bus collision a slave receives a read request and begins shifting data out on the sda line. if a bus collision is detected and the sbcde bit of the sspxcon3 register is set, the bclif bit of the pirx register is set. once a bus col- lision is detected, the slave goes idle and waits to be addressed again. user software can use the bclif bit to handle a slave bus collision. 16.5.3.2 7-bit transmission a master device can transmit a read request to a slave, and then clock data out of the slave. the list below outlines what software for a slave will need to do to accomplish a standard transmission. figure 16-17 can be used as a reference to this list. 1. master sends a start condition on sda and scl. 2. s bit of sspxstat is set; sspif is set if interrupt on start detect is enabled. 3. matching address with r/w bit set is received by the slave setting sspif bit. 4. slave hardware generates an ack and sets sspif. 5. sspif bit is cleared by user. 6. software reads the received address from sspxbuf, clearing bf. 7. r/w is set so ckp was automatically cleared after the ack. 8. the slave software loads the transmit data into sspxbuf. 9. ckp bit is set releasing scl, allowing the mas- ter to clock the data out of the slave. 10. sspif is set after the ack response from the master is loaded into the ackstat register. 11. sspif bit is cleared. 12. the slave software checks the ackstat bit to see if the master wants to clock out more data. 13. steps 9-13 are repeated for each transmitted byte. 14. if the master sends a not ack ; the clock is not held, but sspif is still set. 15. the master sends a restart condition or a stop. 16. the slave is no longer addressed. note 1: if the master ack s the clock will be stretched. 2: ackstat is the only bit updated on the rising edge of scl (9th) rather than the falling. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 235 pic18(l)f2x/45k50 figure 16-18: i 2 c slave, 7-bit address, transmission (ahen = 0 ) receiving address automatic transmitting data automatic transmitting data a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 sda scl sspif bf ckp ackstat r/w d/a s p received address when r/w is set r/w is copied from the indicates an address is read from sspxbuf scl is always held low after 9th scl falling edge matching address byte has been received masters not ack is copied to ackstat ckp is not held for not ack bf is automatically cleared after 8th falling edge of scl data to transmit is loaded into sspxbuf set by software cleared by software ack ack ack r/w = 1 s p master sends stop condition www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 236 ? 2012 microchip technology inc. 16.5.3.3 7-bit transmission with address hold enabled setting the ahen bit of the sspxcon3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. once a matching address has been clocked in, ckp is cleared and the sspif interrupt is set. figure 16-18 displays a standard waveform of a 7-bit address slave transmission with ahen enabled. 1. bus starts idle. 2. master sends start condition; the s bit of sspxstat is set; sspif is set if interrupt on start detect is enabled. 3. master sends matching address with r/w bit set. after the 8th falling edge of the scl line the ckp bit is cleared and sspif interrupt is generated. 4. slave software clears sspif. 5. slave software reads acktim bit of sspxcon3 register, and r/w and d/a of the sspxstat register to determine the source of the interrupt. 6. slave reads the address value from the sspxbuf register clearing the bf bit. 7. slave software decides from this information if it wishes to ack or not ack and sets ackdt bit of the sspxcon2 register accordingly. 8. slave sets the ckp bit releasing scl. 9. master clocks in the ack value from the slave. 10. slave hardware automatically clears the ckp bit and sets sspif after the ack if the r/w bit is set. 11. slave software clears sspif. 12. slave loads value to transmit to the master into sspxbuf setting the bf bit. 13. slave sets ckp bit releasing the clock. 14. master clocks out the data from the slave and sends an ack value on the 9th scl pulse. 15. slave hardware copies the ack value into the ackstat bit of the sspxcon2 register. 16. steps 10-15 are repeated for each byte transmitted to the master from the slave. 17. if the master sends a not ack the slave releases the bus allowing the master to send a stop and end the communication. note: sspxbuf cannot be loaded until after the ack. note: master must send a not ack on the last byte to ensure that the slave releases the scl line to receive a stop. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 237 pic18(l)f2x/45k50 figure 16-19: i 2 c slave, 7-bit address, transmission (ahen = 1 ) receiving address automatic transmitting data automatic transmitting data a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 sda scl sspif bf ackdt ackstat ckp r/w d/a received address is read from sspxbuf bf is automatically cleared after 8th falling edge of scl data to transmit is loaded into sspxbuf cleared by software slave clears ackdt to ack address master?s ack response is copied to sspxstat ckp not cleared after not ack set by software, releases scl acktim is cleared on 9th rising edge of scl acktim is set on 8th falling edge of scl when ahen = 1 ; ckp is cleared by hardware after receiving matching address. when r/w = 1 ; ckp is always cleared after ack s p master sends stop condition ack r/w = 1 master releases sda to slave for ack sequence ack ack acktim www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 238 ? 2012 microchip technology inc. 16.5.4 slave mode 10-bit address reception this section describes a standard sequence of events for the mssp module configured as an i 2 c slave in 10-bit addressing mode. figure 16-19 and is used as a visual reference for this description. this is a step by step process of what must be done by slave software to accomplish i 2 c communication. 1. bus starts idle. 2. master sends start condition; s bit of sspxstat is set; sspif is set if interrupt on start detect is enabled. 3. master sends matching high address with r/w bit clear; ua bit of the sspxstat register is set. 4. slave sends ack and sspif is set. 5. software clears the sspif bit. 6. software reads received address from sspxbuf clearing the bf flag. 7. slave loads low address into sspxadd, releasing scl. 8. master sends matching low address byte to the slave; ua bit is set. 9. slave sends ack and sspif is set. 10. slave clears sspif. 11. slave reads the received matching address from sspxbuf clearing bf. 12. slave loads high address into sspxadd. 13. master clocks a data byte to the slave and clocks out the slaves ack on the 9th scl pulse; sspif is set. 14. if sen bit of sspxcon2 is set, ckp is cleared by hardware and the clock is stretched. 15. slave clears sspif. 16. slave reads the received byte from sspxbuf clearing bf. 17. if sen is set the slave sets ckp to release the scl. 18. steps 13-17 repeat for each received byte. 19. master sends stop to end the transmission. 16.5.5 10-bit addressing with address or data hold reception using 10-bit addressing with ahen or dhen set is the same as with 7-bit modes. the only difference is the need to update the sspxadd register using the ua bit. all functionality, specifically when the ckp bit is cleared and scl line is held low are the same. figure 16-20 can be used as a reference of a slave in 10-bit addressing with ahen set. figure 16-21 shows a standard waveform for a slave transmitter in 10-bit addressing mode. note: updates to the sspxadd register are not allowed until after the ack sequence. note: if the low address does not match, sspif and ua are still set so that the slave soft- ware can set sspxadd back to the high address. bf is not set because there is no match. ckp is unaffected. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 239 pic18(l)f2x/45k50 figure 16-20: i 2 c slave, 10-bit address, reception (sen = 1 , ahen = 0 , dhen = 0 ) sspif receive first address byte ack receive second address byte ack receive data ack receive data ack 1 1 1 1 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl ua ckp 1 2345678 912345678 912345678 9 12345678 9 p master sends stop condition cleared by software receive address is software updates sspxadd data is read scl is held low set by software, while ckp = 0 from sspxbuf releasing scl when sen = 1 ; ckp is cleared after 9th falling edge of received byte read from sspxbuf and releases scl when ua = 1 ; if address matches set by hardware on 9th falling edge sspxadd it is loaded into sspxbuf scl is held low s bf www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 240 ? 2012 microchip technology inc. figure 16-21: i 2 c slave, 10-bit address, reception (sen = 0 , ahen = 1 , dhen = 0 ) receive first address byte ua receive second address byte ua receive data ack receive data 1 1 1 1 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 sda scl sspif bf ackdt ua ckp acktim 12345678 9 s ack ack 12 345678 9 12345678 91 2 sspxbuf is read from received data sspxbuf can be read anytime before the next received byte cleared by software falling edge of scl not allowed until 9th update to sspxadd is set ckp with software releases scl scl clears ua and releases update of sspxadd, set by hardware on 9th falling edge slave software clears ackdt to ack the received byte if when ahen = 1 ; on the 8th falling edge of scl of an address byte, ckp is cleared acktim is set by hardware on 8th falling edge of scl cleared by software r/w = 0 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 241 pic18(l)f2x/45k50 figure 16-22: i 2 c slave, 10-bit address, transmission (sen = 0 , ahen = 0 , dhen = 0 ) receiving address ack receiving second address byte sr receive first address byte ack transmitting data byte 1 1 1 1 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 1 1 1 1 0 a9 a8 d7 d6 d5 d4 d3 d2 d1 d0 sda scl sspif bf ua ckp r/w d/a 1 2345 6789 1 2345 6789 1 23 4 5 6789 1 23456 789 ack = 1 p master sends stop condition master sends not ack master sends restart event ack r/w = 0 s cleared by software after sspxadd is updated, ua is cleared and scl is released high address is loaded received address is data to transmit is set by software indicates an address when r/w = 1 ; r/w is copied from the set by hardware ua indicates sspxadd sspxbuf loaded with received address must be updated has been received loaded into sspxbuf releases scl masters not ack is copied matching address byte ckp is cleared on 9th falling edge of scl read from sspxbuf back into sspxadd ackstat set by hardware www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 242 ? 2012 microchip technology inc. 16.5.6 clock stretching clock stretching occurs when a device on the bus holds the scl line low effectively pausing communica- tion. the slave may stretch the clock to allow more time to handle data or prepare a response for the mas- ter device. a master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. any stretching done by a slave is invisible to the master software and han- dled by the hardware that generates scl. the ckp bit of the sspxcon1 register is used to control stretching in software. any time the ckp bit is cleared, the module will wait for the scl line to go low and then hold it. setting ckp will release scl and allow more communication. 16.5.6.1 normal clock stretching following an ack if the r/w bit of sspxstat is set, a read request, the slave hardware will clear ckp. this allows the slave time to update sspxbuf with data to transfer to the master. if the sen bit of sspxcon2 is set, the slave hardware will always stretch the clock after the ack sequence. once the slave is ready; ckp is set by software and communication resumes. 16.5.6.2 10-bit addressing mode in 10-bit addressing mode, when the ua bit is set, the clock is always stretched. this is the only time the scl is stretched without ckp being cleared. scl is released immediately after a write to sspxadd. 16.5.6.3 byte nacking when the ahen bit of sspxcon3 is set; ckp is cleared by hardware after the 8th falling edge of scl for a received matching address byte. when the dhen bit of sspxcon3 is set; ckp is cleared after the 8th falling edge of scl for received data. stretching after the 8th falling edge of scl allows the slave to look at the received address or data and decide if it wants to ack the received data. 16.5.7 clock synchronization and the ckp bit any time the ckp bit is cleared, the module will wait for the scl line to go low and then hold it. however, clearing the ckp bit will not assert the scl output low until the scl output is already sampled low. there- fore, the ckp bit will not assert the scl line until an external i 2 c master device has already asserted the scl line. the scl output will remain low until the ckp bit is set and all other devices on the i 2 c bus have released scl. this ensures that a write to the ckp bit will not violate the minimum high time requirement for scl (see figure 16-22 ). figure 16-23: clock synchronization timing note 1: the bf bit has no effect on whether the clock will be stretched or not. this is different than previous versions of the module that would not stretch the clock, clear ckp, if sspxbuf was read before the 9th falling edge of scl. 2: previous versions of the module did not stretch the clock for a transmission if sspxbuf was loaded before the 9th fall- ing edge of scl. it is now always cleared for read requests. note: previous versions of the module did not stretch the clock if the second address byte did not match. sda scl dx ? ? 1 dx wr q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 sspxcon1 ckp master device releases clock master device asserts clock www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 243 pic18(l)f2x/45k50 16.5.8 general call address support the addressing procedure for the i 2 c bus is such that the first byte after the start condition usually determines which device will be the slave addressed by the master device. the exception is the general call address which can address all devices. when this address is used, all devices should, in theory, respond with an acknowledge. the general call address is a reserved address in the i 2 c protocol, defined as address 0x00. when the gcen bit of the sspxcon2 register is set, the slave module will automatically ack the reception of this address regardless of the value stored in sspxadd. after the slave clocks in an address of all zeros with the r/w bit clear, an interrupt is generated and slave soft- ware can read sspxbuf and respond. figure 16-23 shows a general call reception sequence. in 10-bit address mode, the ua bit will not be set on the reception of the general call address. the slave will prepare to receive the second byte as data, just as it would in 7-bit mode. if the ahen bit of the sspxcon3 register is set, just as with any other address reception, the slave hardware will stretch the clock after the 8th falling edge of scl. the slave must then set its ackdt value and release the clock with communication progressing as it would normally. figure 16-24: slave mode general call address sequence 16.5.9 sspx mask register an sspx mask (sspxmsk) register ( register 16-5 ) is available in i 2 c slave mode as a mask for the value held in the sspxsr register during an address comparison operation. a zero (? 0 ?) bit in the sspxmsk register has the effect of making the corresponding bit of the received address a ?don?t care?. this register is reset to all ? 1 ?s upon any reset condition and, therefore, has no effect on standard sspx operation until written with a mask value. the sspx mask register is active during: ? 7-bit address mode: address compare of a<7:1>. ? 10-bit address mode: address compare of a<7:0> only. the sspx mask has no effect during the reception of the first (high) byte of the address. sda scl s sspif bf (sspxstat<0>) cleared by software sspxbuf is read r/w = 0 ack general call address address is compared to general call address receiving data ack 123456789123456789 d7 d6 d5 d4 d3 d2 d1 d0 after ack , set interrupt gcen (sspxcon2<7>) ? 1 ? www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 244 ? 2012 microchip technology inc. 16.6 i 2 c master mode master mode is enabled by setting and clearing the appropriate sspxm bits in the sspxcon1 register and by setting the sspxen bit. in master mode, the scl and sda lines are set as inputs and are manipulated by the mssp hardware. master mode of operation is supported by interrupt generation on the detection of the start and stop con- ditions. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit is set, or the bus is idle. in firmware controlled master mode, user code conducts all i 2 c bus operations based on start and stop bit condition detection. start and stop condition detection is the only active circuitry in this mode. all other communication is done by the user software directly manipulating the sda and scl lines. the following events will cause the sspx interrupt flag bit, sspif, to be set (sspx interrupt, if enabled): ? start condition detected ? stop condition detected ? data transfer byte transmitted/received ? acknowledge transmitted/received ? repeated start generated 16.6.1 i 2 c master mode operation the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since the repeated start condition is also the beginning of the next serial transfer, the i 2 c bus will not be released. in master transmitter mode, serial data is output through sda, while scl outputs the serial clock. the first byte transmitted contains the slave address of the receiving device (7 bits) and the read/write (r/w ) bit. in this case, the r/w bit will be logic ? 0 ?. serial data is transmitted eight bits at a time. after each byte is trans- mitted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. in master receive mode, the first byte transmitted con- tains the slave address of the transmitting device (7 bits) and the r/w bit. in this case, the r/w bit will be logic ? 1 ?. thus, the first byte transmitted is a 7-bit slave address followed by a ? 1 ? to indicate the receive bit. serial data is received via sda, while scl outputs the serial clock. serial data is received eight bits at a time. after each byte is received, an acknowledge bit is transmitted. start and stop conditions indicate the beginning and end of transmission. a baud rate generator is used to set the clock frequency output on scl. see section 16.7 ?baud rate generator? for more detail. note 1: the mssp module, when configured in i 2 c master mode, does not allow queue- ing of events. for instance, the user is not allowed to initiate a start condition and immediately write the sspxbuf register to initiate transmission before the start condition is complete. in this case, the sspxbuf will not be written to and the wcol bit will be set, indicating that a write to the sspxbuf did not occur 2: when in master mode, start/stop detection is masked and an interrupt is generated when the sen/pen bit is cleared and the generation is complete. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 245 pic18(l)f2x/45k50 16.6.2 clock arbitration clock arbitration occurs when the master, during any receive, transmit or repeated start/stop condition, releases the scl pin (scl allowed to float high). when the scl pin is allowed to float high, the baud rate gen- erator (brg) is suspended from counting until the scl pin is actually sampled high. when the scl pin is sam- pled high, the baud rate generator is reloaded with the contents of sspxadd<7:0> and begins counting. this ensures that the scl high time will always be at least one brg rollover count in the event that the clock is held low by an external device ( figure 16-25 ). figure 16-25: baud rate generator timing with clock arbitration 16.6.3 wcol status flag if the user writes the sspxbuf when a start, restart, stop, receive or transmit sequence is in progress, the wcol is set and the contents of the buffer are unchanged (the write does not occur). any time the wcol bit is set it indicates that an action on sspxbuf was attempted while the module was not idle. sda scl scl deasserted but slave holds dx ? ? 1 dx brg scl is sampled high, reload takes place and brg starts its count 03h 02h 01h 00h (hold off) 03h 02h reload brg value scl low (clock arbitration) sclscl allowed to transition high brg decrements on q2 and q4 cycles note: because queueing of events is not allowed, writing to the lower five bits of sspxcon2 is disabled until the start condition is complete. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 246 ? 2012 microchip technology inc. 16.6.4 i 2 c master mode start condition timing to initiate a start condition, the user sets the start enable bit, sen, of the sspxcon2 register. if the sda and scl pins are sampled high, the baud rate generator is reloaded with the contents of sspxadd<7:0> and starts its count. if scl and sda are both sampled high when the baud rate generator times out (t brg ), the sda pin is driven low. the action of the sda being driven low while scl is high is the start condition and causes the s bit of the sspxstat1 register to be set. following this, the baud rate gen- erator is reloaded with the contents of sspxadd<7:0> and resumes its count. when the baud rate genera- tor times out (t brg ), the sen bit of the sspxcon2 register will be automatically cleared by hardware; the baud rate generator is suspended, leaving the sda line held low and the start condition is complete. figure 16-26: first start bit timing note 1: if at the beginning of the start condition, the sda and scl pins are already sam- pled low, or if during the start condition, the scl line is sampled low before the sda line is driven low, a bus collision occurs, the bus collision interrupt flag, bclif, is set, the start condition is aborted and the i 2 c module is reset into its idle state. 2: the philips i 2 c specification states that a bus collision cannot occur on a start. sda scl s t brg 1st bit 2nd bit t brg sda = 1 , at completion of start bit, scl = 1 write to sspxbuf occurs here t brg hardware clears sen bit t brg write to sen bit occurs here set s bit (sspxstat<3>) and sets sspif bit www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 247 pic18(l)f2x/45k50 16.6.5 i 2 c master mode repeated start condition timing a repeated start condition occurs when the rsen bit of the sspxcon2 register is programmed high and the master state machine is no longer active. when the rsen bit is set, the scl pin is asserted low. when the scl pin is sampled low, the baud rate generator is loaded and begins counting. the sda pin is released (brought high) for one baud rate generator count (t brg ). when the baud rate generator times out, if sda is sampled high, the scl pin will be deasserted (brought high). when scl is sampled high, the baud rate generator is reloaded and begins counting. sda and scl must be sampled high for one t brg . this action is then followed by assertion of the sda pin (sda= 0 ) for one t brg while scl is high. scl is asserted low. following this, the rsen bit of the sspxcon2 register will be automatically cleared and the baud rate generator will not be reloaded, leaving the sda pin held low. as soon as a start condition is detected on the sda and scl pins, the s bit of the sspxstat register will be set. the sspif bit will not be set until the baud rate generator has timed out. figure 16-27: repeat start condition waveform note 1: if rsen is programmed while any other event is in progress, it will not take effect. 2: a bus collision during the repeated start condition occurs if: ? sda is sampled low when scl goes from low-to-high. ? scl goes low before sda is asserted low. this may indicate that another master is attempting to transmit a data ? 1 ?. sda scl repeated start write to sspxcon2 write to sspxbuf occurs here at completion of start bit, hardware clears rsen bit 1st bit s bit set by hardware t brg t brg sda = 1 , sda = 1 , scl (no change) scl = 1 occurs here t brg t brg t brg and sets sspif sr www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 248 ? 2012 microchip technology inc. 16.6.6 i 2 c master mode transmission transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the sspxbuf register. this action will set the buffer full flag bit, bf, and allow the baud rate generator to begin counting and start the next trans- mission. each bit of address/data will be shifted out onto the sda pin after the falling edge of scl is asserted. scl is held low for one baud rate generator rollover count (t brg ). data should be valid before scl is released high. when the scl pin is released high, it is held that way for t brg . the data on the sda pin must remain stable for that duration and some hold time after the next falling edge of scl. after the eighth bit is shifted out (the falling edge of the eighth clock), the bf flag is cleared and the master releases sda. this allows the slave device being addressed to respond with an ack bit during the ninth bit time if an address match occurred, or if data was received prop- erly. the status of ack is written into the ackstat bit on the rising edge of the ninth clock. if the master receives an acknowledge, the acknowledge status bit, ackstat, is cleared. if not, the bit is set. after the ninth clock, the sspif bit is set and the master clock (baud rate generator) is suspended until the next data byte is loaded into the sspxbuf, leaving scl low and sda unchanged ( figure 16-27 ). after the write to the sspxbuf, each bit of the address will be shifted out on the falling edge of scl until all seven address bits and the r/w bit are completed. on the falling edge of the eighth clock, the master will release the sda pin, allowing the slave to respond with an acknowledge. on the falling edge of the ninth clock, the master will sample the sda pin to see if the address was recognized by a slave. the status of the ack bit is loaded into the ackstat status bit of the sspxcon2 register. following the falling edge of the ninth clock transmission of the address, the sspif is set, the bf flag is cleared and the baud rate generator is turned off until another write to the sspxbuf takes place, holding scl low and allowing sda to float. 16.6.6.1 bf status flag in transmit mode, the bf bit of the sspxstat register is set when the cpu writes to sspxbuf and is cleared when all eight bits are shifted out. 16.6.6.2 wcol status flag if the user writes the sspxbuf when a transmit is already in progress (i.e., sspxsr is still shifting out a data byte), the wcol is set and the contents of the buffer are unchanged (the write does not occur). wcol must be cleared by software before the next transmission. 16.6.6.3 ackstat status flag in transmit mode, the ackstat bit of the sspxcon2 register is cleared when the slave has sent an acknowledge (ack = 0 ) and is set when the slave does not acknowledge (ack = 1 ). a slave sends an acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 16.6.6.4 typical transmit sequence: 1. the user generates a start condition by setting the sen bit of the sspxcon2 register. 2. sspif is set by hardware on completion of the start. 3. sspif is cleared by software. 4. the mssp module will wait the required start time before any other operation takes place. 5. the user loads the sspxbuf with the slave address to transmit. 6. address is shifted out the sda pin until all eight bits are transmitted. transmission begins as soon as sspxbuf is written to. 7. the mssp module shifts in the ack bit from the slave device and writes its value into the ackstat bit of the sspxcon2 register. 8. the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. 9. the user loads the sspxbuf with eight bits of data. 10. data is shifted out the sda pin until all eight bits are transmitted. 11. the mssp module shifts in the ack bit from the slave device and writes its value into the ackstat bit of the sspxcon2 register. 12. steps 8-11 are repeated for all transmitted data bytes. 13. the user generates a stop or restart condition by setting the pen or rsen bits of the sspxcon2 register. interrupt is generated once the stop/restart condition is complete. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 249 pic18(l)f2x/45k50 figure 16-28: i 2 c master mode waveform (transmission, 7 or 10-bit address) sda scl sspif bf (sspxstat<0>) sen a7 a6 a5 a4 a3 a2 a1 ack = 0 d7 d6 d5 d4 d3 d2 d1 d0 ack transmitting data or second half r/w = 0 transmit address to slave 123456789 123456789 p cleared by software service routine sspxbuf is written by software from sspx interrupt after start condition, sen cleared by hardware s sspxbuf written with 7-bit address and r/w start transmit scl held low while cpu responds to sspif sen = 0 of 10-bit address write sspxcon2<0> sen = 1 start condition begins from slave, clear ackstat bit sspxcon2<6> ackstat in sspxcon2 = 1 cleared by software sspxbuf written pen r/w cleared by software www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 250 ? 2012 microchip technology inc. 16.6.7 i 2 c master mode reception master mode reception is enabled by programming the receive enable bit, rcen, of the sspxcon2 register. the baud rate generator begins counting and on each rollover, the state of the scl pin changes (high-to-low/ low-to-high) and data is shifted into the sspxsr. after the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the sspxsr are loaded into the sspxbuf, the bf flag bit is set, the sspif flag bit is set and the baud rate gen- erator is suspended from counting, holding scl low. the mssp is now in idle state awaiting the next com- mand. when the buffer is read by the cpu, the bf flag bit is automatically cleared. the user can then send an acknowledge bit at the end of reception by setting the acknowledge sequence enable bit, acken, of the sspxcon2 register. 16.6.7.1 bf status flag in receive operation, the bf bit is set when an address or data byte is loaded into sspxbuf from sspxsr. it is cleared when the sspxbuf register is read. 16.6.7.2 sspov status flag in receive operation, the sspov bit is set when eight bits are received into the sspxsr and the bf flag bit is already set from a previous reception. 16.6.7.3 wcol status flag if the user writes the sspxbuf when a receive is already in progress (i.e., sspxsr is still shifting in a data byte), the wcol bit is set and the contents of the buffer are unchanged (the write does not occur). 16.6.7.4 typical receive sequence: 1. the user generates a start condition by setting the sen bit of the sspxcon2 register. 2. sspif is set by hardware on completion of the start. 3. sspif is cleared by software. 4. user writes sspxbuf with the slave address to transmit and the r/w bit set. 5. address is shifted out the sda pin until all eight bits are transmitted. transmission begins as soon as sspxbuf is written to. 6. the mssp module shifts in the ack bit from the slave device and writes its value into the ackstat bit of the sspxcon2 register. 7. the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. 8. user sets the rcen bit of the sspxcon2 regis- ter and the master clocks in a byte from the slave. 9. after the 8th falling edge of scl, sspif and bf are set. 10. master clears sspif and reads the received byte from sspxuf, clears bf. 11. master sets ack value sent to slave in ackdt bit of the sspxcon2 register and initiates the ack by setting the acken bit. 12. masters ack is clocked out to the slave and sspif is set. 13. user clears sspif. 14. steps 8-13 are repeated for each received byte from the slave. 15. master sends a not ack or stop to end communication. note: the mssp module must be in an idle state before the rcen bit is set or the rcen bit will be disregarded. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 251 pic18(l)f2x/45k50 figure 16-29: i 2 c? master mode waveform (reception, 7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 5 678 9 1234 bus master terminates transfer ack receiving data from slave receiving data from slave d0 d1 d2 d3 d4 d5 d6 d7 ack transmit address to slave sspif bf ack is not sent write to sspxcon2<0>(sen = 1 ), write to sspxbuf occurs here, ack from slave master configured as a receiver by programming sspxcon2<3> (rcen = 1 ) pen bit = 1 written here data shifted in on falling edge of clk cleared by software start xmit sen = 0 sspov sda = 0 , scl = 1 while cpu (sspxstat<0>) ack cleared by software cleared by software set sspif interrupt at end of receive set p bit (sspxstat<4>) and sspif cleared in software ack from master set sspif at end set sspif interrupt at end of acknowledge sequence set sspif interrupt at end of acknow- ledge sequence of receive set acken, start acknowledge sequence sspov is set because sspxbuf is still full sda = ackdt = 1 rcen cleared automatically rcen = 1 , start next receive write to sspxcon2<4> to start acknowledge sequence sda = ackdt (sspxcon2<5>) = 0 rcen cleared automatically responds to sspif acken begin start condition cleared by software sda = ackdt = 0 last bit is shifted into sspxsr and contents are unloaded into sspxbuf rcen master configured as a receiver by programming sspxcon2<3> (rcen = 1 ) rcen cleared automatically ack from master sda = ackdt = 0 rcen cleared automatically r/w www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 252 ? 2012 microchip technology inc. 16.6.8 acknowledge sequence timing an acknowledge sequence is enabled by setting the acknowledge sequence enable bit, acken, of the sspxcon2 register. when this bit is set, the scl pin is pulled low and the contents of the acknowledge data bit are presented on the sda pin. if the user wishes to gen- erate an acknowledge, then the ackdt bit should be cleared. if not, the user should set the ackdt bit before starting an acknowledge sequence. the baud rate generator then counts for one rollover period (t brg ) and the scl pin is deasserted (pulled high). when the scl pin is sampled high (clock arbitration), the baud rate generator counts for t brg . the scl pin is then pulled low. following this, the acken bit is automatically cleared, the baud rate generator is turned off and the mssp module then goes into idle mode ( figure 16-29 ). 16.6.8.1 wcol status flag if the user writes the sspxbuf when an acknowledge sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write does not occur). 16.6.9 stop condition timing a stop bit is asserted on the sda pin at the end of a receive/transmit by setting the stop sequence enable bit, pen, of the sspxcon2 register. at the end of a receive/transmit, the scl line is held low after the falling edge of the ninth clock. when the pen bit is set, the master will assert the sda line low. when the sda line is sampled low, the baud rate generator is reloaded and counts down to ? 0 ?. when the baud rate generator times out, the scl pin will be brought high and one t brg (baud rate generator rollover count) later, the sda pin will be deasserted. when the sda pin is sampled high while scl is high, the p bit of the sspxstat register is set. a t brg later, the pen bit is cleared and the sspif bit is set ( figure 16-30 ). 16.6.9.1 wcol status flag if the user writes the sspxbuf when a stop sequence is in progress, then the wcol bit is set and the contents of the buffer are unchanged (the write does not occur). figure 16-30: acknowledge sequen ce waveform figure 16-31: stop cond ition receive or transmit mode note: t brg = one baud rate generator period. sda scl sspif set at acknowledge sequence starts here, write to sspxcon2 acken automatically cleared cleared in t brg t brg the end of receive 8 acken = 1 , ackdt = 0 d0 9 sspif software sspif set at the end of acknowledge sequence cleared in software ack scl sda sda asserted low before rising edge of clock write to sspxcon2, set pen falling edge of scl = 1 for t brg , followed by sda = 1 for t brg 9th clock scl brought high after t brg note: t brg = one baud rate generator period. t brg t brg after sda sampled high. p bit (sspxstat<4>) is set. t brg to set up stop condition ack p t brg pen bit (sspxcon2<2>) is cleared by hardware and the sspif bit is set www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 253 pic18(l)f2x/45k50 16.6.10 sleep operation while in sleep mode, the i 2 c slave module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from sleep (if the mssp interrupt is enabled). 16.6.11 effects of a reset a reset disables the mssp module and terminates the current transfer. 16.6.12 multi-master mode in multi-master mode, the interrupt generation on the detection of the start and stop conditions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit of the sspxstat register is set, or the bus is idle, with both the s and p bits clear. when the bus is busy, enabling the ssp interrupt will generate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be monitored for arbitration to see if the signal level is the expected output level. this check is performed by hardware with the result placed in the bclif bit. the states where arbitration can be lost are: ? address transfer ? data transfer ? a start condition ? a repeated start condition ? an acknowledge condition www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 254 ? 2012 microchip technology inc. 16.6.13 multi -master communication, bus collision and bus arbitration multi-master mode support is achieved by bus arbitration. when the master outputs address/data bits onto the sda pin, arbitration takes place when the master outputs a ? 1 ? on sda, by letting sda float high and another master asserts a ? 0 ?. when the scl pin floats high, data should be stable. if the expected data on sda is a ? 1 ? and the data sampled on the sda pin is ? 0 ?, then a bus collision has taken place. the master will set the bus collision interrupt flag, bclif, and reset the i 2 c port to its idle state ( figure 16-31 ). if a transmit was in progress when the bus collision occurred, the transmission is halted, the bf flag is cleared, the sda and scl lines are deasserted and the sspxbuf can be written to. when the user services the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. if a start, repeated start, stop or acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the sda and scl lines are deasserted and the respective control bits in the sspxcon2 register are cleared. when the user services the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. the master will continue to monitor the sda and scl pins. if a stop condition occurs, the sspif bit will be set. a write to the sspxbuf will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. in multi-master mode, the interrupt generation on the detection of start and stop conditions allows the determination of when the bus is free. control of the i 2 c bus can be taken when the p bit is set in the sspxstat register, or the bus is idle and the s and p bits are cleared. figure 16-32: bus collision timing for transmit and acknowledge sda scl bclif sda released sda line pulled low by another source sample sda. while scl is high, data does not match what is driven bus collision has occurred. set bus collision interrupt (bclif) by the master. by master data changes while scl = 0 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 255 pic18(l)f2x/45k50 16.6.13.1 bus collision during a start condition during a start condition, a bus collision occurs if: a) sda or scl are sampled low at the beginning of the start condition ( figure 16-32 ). b) scl is sampled low before sda is asserted low ( figure 16-33 ). during a start condition, both the sda and the scl pins are monitored. if the sda pin is already low, or the scl pin is already low, then all of the following occur: ? the start condition is aborted, ? the bclif flag is set and ? the mssp module is reset to its idle state ( figure 16-32 ). the start condition begins with the sda and scl pins deasserted. when the sda pin is sampled high, the baud rate generator is loaded and counts down. if the scl pin is sampled low while sda is high, a bus colli- sion occurs because it is assumed that another master is attempting to drive a data ? 1 ? during the start condition. if the sda pin is sampled low during this count, the brg is reset and the sda line is asserted early ( figure 16-34 ). if, however, a ? 1 ? is sampled on the sda pin, the sda pin is asserted low at the end of the brg count. the baud rate generator is then reloaded and counts down to zero; if the scl pin is sampled as ? 0 ? during this time, a bus collision does not occur. at the end of the brg count, the scl pin is asserted low. figure 16-33: bus collision during start condition (sda only) note: the reason that bus collision is not a factor during a start condition is that no two bus masters can assert a start condi- tion at the exact same time. therefore, one master will always assert sda before the other. this condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the start condition. if the address is the same, arbitration must be allowed to continue into the data portion, repeated start or stop conditions. sda scl sen sda sampled low before sda goes low before the sen bit is set. s bit and sspif set because sspx module reset into idle state. sen cleared automatically because of bus collision. s bit and sspif set because set sen, enable start condition if sda = 1 , scl = 1 sda = 0 , scl = 1 . bclif s sspif sda = 0 , scl = 1 . sspif and bclif are cleared by software sspif and bclif are cleared by software set bclif, start condition. set bclif. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 256 ? 2012 microchip technology inc. figure 16-34: bus collision d uring start condition (scl = 0 ) figure 16-35: brg reset due to sda arbitration during start condition sda scl sen bus collision occurs. set bclif. scl = 0 before sda = 0 , set sen, enable start sequence if sda = 1 , scl = 1 t brg t brg sda = 0 , scl = 1 bclif s sspif interrupt cleared by software bus collision occurs. set bclif. scl = 0 before brg time-out, ? 0 ?? 0 ? ? 0 ? ? 0 ? sda scl sen set s less than t brg t brg sda = 0 , scl = 1 bclif s sspif s interrupts cleared by software set sspif sda = 0 , scl = 1 , scl pulled low after brg time-out set sspif ? 0 ? sda pulled low by other master. reset brg and assert sda. set sen, enable start sequence if sda = 1 , scl = 1 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 257 pic18(l)f2x/45k50 16.6.13.2 bus collision during a repeated start condition during a repeated start condition, a bus collision occurs if: a) a low level is sampled on sda when scl goes from low level to high level. b) scl goes low before sda is asserted low, indicating that another master is attempting to transmit a data ? 1 ?. when the user releases sda and the pin is allowed to float high, the brg is loaded with sspxadd and counts down to zero. the scl pin is then deasserted and when sampled high, the sda pin is sampled. if sda is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ? 0 ?, figure 16-35 ). if sda is sampled high, the brg is reloaded and begins counting. if sda goes from high-to-low before the brg times out, no bus collision occurs because no two masters can assert sda at exactly the same time. if scl goes from high-to-low before the brg times out and sda has not already been asserted, a bus collision occurs. in this case, another master is attempting to transmit a data ? 1 ? during the repeated start condition, see figure 16-36 . if, at the end of the brg time-out, both scl and sda are still high, the sda pin is driven low and the brg is reloaded and begins counting. at the end of the count, regardless of the status of the scl pin, the scl pin is driven low and the repeated start condition is complete. figure 16-36: bus collision during a repeat ed start condition (case 1) figure 16-37: bus collision during repeat ed start condition (case 2) sda scl rsen bclif s sspif sample sda when scl goes high. if sda = 0 , set bclif and release sda and scl. cleared by software ? 0 ? ? 0 ? sda scl bclif rsen s sspif interrupt cleared by software scl goes low before sda set bclif. release sda and scl. t brg t brg ? 0 ? www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 258 ? 2012 microchip technology inc. 16.6.13.3 bus collision during a stop condition bus collision occurs during a stop condition if: a) after the sda pin has been deasserted and allowed to float high, sda is sampled low after the brg has timed out. b) after the scl pin is deasserted, scl is sampled low before sda goes high. the stop condition begins with sda asserted low. when sda is sampled low, the scl pin is allowed to float. when the pin is sampled high (clock arbitration), the baud rate generator is loaded with sspxadd and counts down to 0. after the brg times out, sda is sampled. if sda is sampled low, a bus collision has occurred. this is due to another master attempting to drive a data ? 0 ? ( figure 16-37 ). if the scl pin is sampled low before sda is allowed to float high, a bus collision occurs. this is another case of another master attempting to drive a data ? 0 ? ( figure 16-38 ). figure 16-38: bus collision during a stop condition (case 1) figure 16-39: bus collision during a stop condition (case 2) sda scl bclif pen p sspif t brg t brg t brg sda asserted low sda sampled low after t brg , set bclif ? 0 ? ? 0 ? sda scl bclif pen p sspif t brg t brg t brg assert sda scl goes low before sda goes high, set bclif ? 0 ? ? 0 ? www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 259 pic18(l)f2x/45k50 table 16-3: registers associated with i 2 c? operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page anselb ? ? ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 155 intcon gie/gieh peie/giel tmr0ie int0ie iocie tmr0if int0if iocif 120 ipr1 actip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 129 ipr2 oscfip c1ip c2ip eeip bclip hlvdip tmr3ip ccp2ip 130 pie1 actie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 126 pie2 oscfie c1ie c2ie eeie bclie hlvdie tmr3ie ccp2ie 127 pir1 actif adif rcif txif sspif ccp1if tmr2if tmr1if 123 pir2 oscfif c1if c2if eeif bclif hlvdif tmr3if ccp2if 124 pmd1 ? msspmd ctmumd cmp2md cmp1md adcmd ccp2md ccp1md 65 ssp1add ssp1 address register in i 2 c slave mode. ssp1 baud rate reload register in i 2 c master mode. 267 ssp1buf ssp1 receive buffer/transmit register ? ssp1con1 wcol sspov sspen ckp sspm<3:0> 262 ssp1con2 gcen ackstat ackdt acken rcen pen rsen sen 264 ssp1con3 acktim pcie scie boen sdaht sbcde ahen dhen 265 ssp1msk ssp1 mask register bits 266 ssp1stat smp cke d/a psr/w ua bf 261 trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 156 legend: shaded bits are not used by the mssp in i 2 c mode. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 260 ? 2012 microchip technology inc. 16.7 baud rate generator the mssp module has a baud rate generator avail- able for clock generation in both i 2 c and spi master modes. the baud rate generator (brg) reload value is placed in the sspxadd register ( register 16-6 ). when a write occurs to sspxbuf, the baud rate gen- erator will automatically begin counting down. once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. an internal signal ?reload? in figure 16-39 triggers the value from sspxadd to be loaded into the brg counter. this occurs twice for each oscillation of the module clock line. the logic dictating when the reload signal is asserted depends on the mode the mssp is being operated in. table 16-4 demonstrates clock rates based on instruction cycles and the brg value loaded into sspxadd. equation 16-1: figure 16-40: baud rate genera tor block diagram f clock f osc sspxadd 1 + ?? 4 ?? ------------------------------------------------- = note: values of 0x00, 0x01 and 0x02 are not valid for sspxadd when used as a baud rate generator for i 2 c. this is an implementation limitation. sspxm<3:0> brg down counter sspxclk f osc /2 sspxadd<7:0> sspxm<3:0> scl reload control reload table 16-4: mssp clock rate w/brg f osc f cy brg value f clock (2 rollovers of brg) 32 mhz 8 mhz 13h 400 khz (1) 32 mhz 8 mhz 19h 308 khz 32 mhz 8 mhz 4fh 100 khz 16 mhz 4 mhz 09h 400 khz (1) 16 mhz 4 mhz 0ch 308 khz 16 mhz 4 mhz 27h 100 khz 4 mhz 1 mhz 09h 100 khz note 1: the i 2 c interface does not conform to the 400 khz i 2 c specification (which applies to rates greater than 100 khz) in all details, but may be used with care where higher rates are required by the application. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 261 pic18(l)f2x/45k50 16.8 register definitions: mssp control register 16-1: sspxstat: sspx status register r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a psr/w ua bf bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = val ue at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 smp: spi data input sample bit spi master mode: 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi slave mode: smp must be cleared when spi is used in slave mode in i 2 c master or slave mode: 1 = slew rate control disabled for standard speed mode (100 khz and 1 mhz) 0 = slew rate control enabled for high speed mode (400 khz) bit 6 cke: spi clock edge select bit (spi mode only) in spi master or slave mode: 1 = transmit occurs on transition from active to idle clock state 0 = transmit occurs on transition from idle to active clock state in i 2 c mode only: 1 = enable input logic so that thresholds are compliant with smbus specification 0 = disable smbus specific inputs bit 5 d/a : data/address bit (i 2 c mode only) 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4 p: stop bit (i 2 c mode only. this bit is cleared when the mssp module is disabled, sspxen is cleared.) 1 = indicates that a stop bit has been detected last (this bit is ? 0 ? on reset) 0 = stop bit was not detected last bit 3 s: start bit (i 2 c mode only. this bit is cleared when the mssp module is disabled, sspxen is cleared.) 1 = indicates that a start bit has been detected last (this bit is ? 0 ? on reset) 0 = start bit was not detected last bit 2 r/w : read/write bit information (i 2 c mode only) this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit, or not ack bit. in i 2 c slave mode: 1 = read 0 = write in i 2 c master mode: 1 = transmit is in progress 0 = transmit is not in progress or-ing this bit with sen, rsen, pen, rcen or acken will indicate if the mssp is in idle mode. bit 1 ua: update address bit (10-bit i 2 c mode only) 1 = indicates that the user needs to update the address in the sspxadd register 0 = address does not need to be updated bit 0 bf: buffer full status bit receive (spi and i 2 c modes): 1 = receive complete, sspxbuf is full 0 = receive not complete, sspxbuf is empty transmit (i 2 c mode only): 1 = data transmit in progress (does not include the ack and stop bits), sspxbuf is full 0 = data transmit complete (does not include the ack and stop bits), sspxbuf is empty www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 262 ? 2012 microchip technology inc. register 16-2: sspxcon1: ss px control register 1 r/c/hs-0 r/c/hs-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = val ue at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared hs = bit is set by hardware c = user cleared bit 7 wcol: write collision detect bit master mode: 1 = a write to the sspxbuf register was attempted while the i 2 c conditions were not valid for a transmission to be started 0 = no collision slave mode: 1 = the sspxbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6 sspov: receive overflow indicator bit (1) in spi mode: 1 = a new byte is received while the sspxbu f register is still holding the previous data. in case of overflow, the data in sspxsr is lost. overflow can only occur in slave mode. in slave mode, the user must read the sspxbuf, even if only transmitting data, to avoid setting overflow. in mast er mode, the overflow bit is not set since each new recep- tion (and transmission) is initiated by writing to the sspxbuf register (must be cleared in software). 0 = no overflow in i 2 c mode: 1 = a byte is received while the sspxbuf register is st ill holding the previous byte. sspov is a ?don?t care? in transmit mode (must be cleared in software). 0 = no overflow bit 5 sspen: synchronous serial port enable bit in both modes, when enabled, these pins must be properly configured as input or output in spi mode: 1 = enables serial port and configures sck, sdo, sdi and ss as the source of the serial port pins (2) 0 = disables serial port and configures these pins as i/o port pins in i 2 c mode: 1 = enables the serial port and configures the sda and scl pins as the source of the serial port pins (3) 0 = disables serial port and configures these pins as i/o port pins bit 4 ckp: clock polarity select bit in spi mode: 1 = idle state for clock is a high level 0 = idle state for clock is a low level in i 2 c slave mode: scl release control 1 = enable clock 0 = holds clock low (clock stretch). (used to ensure data setup time.) in i 2 c master mode: unused in this mode www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 263 pic18(l)f2x/45k50 bit 3-0 sspm<3:0>: synchronous serial port mode select bits 0000 = spi master mode, clock = f osc /4 0001 = spi master mode, clock = f osc /16 0010 = spi master mode, clock = f osc /64 0011 = spi master mode, clock = tmr2 output/2 0100 = spi slave mode, clock = sck pin, ss pin control enabled 0101 = spi slave mode, clock = sck pin, ss pin control disabled, ss can be used as i/o pin 0110 = i 2 c slave mode, 7-bit address 0111 = i 2 c slave mode, 10-bit address 1000 = i 2 c master mode, clock = f osc / (4 * (sspxadd+1)) (4) 1001 = reserved 1010 = spi master mode, clock = f osc /(4 * (sspxadd+1)) 1011 = i 2 c firmware controlled master mode (slave idle) 1100 = reserved 1101 = reserved 1110 = i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = i 2 c slave mode, 10-bit address with start and stop bit interrupts enabled note 1: in master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the sspxbuf register. 2: when enabled, these pins must be proper ly configured as input or output. 3: when enabled, the sda and scl pins must be configured as inputs. 4: sspxadd values of 0, 1 or 2 are not supported for i 2 c mode. register 16-2: sspxcon1: sspx co ntrol register 1 (continued) www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 264 ? 2012 microchip technology inc. register 16-3: sspxcon2: ss px control register 2 r/w-0 r-0 r/w-0 r/s/hc-0 r/s/hc-0 r/s/hc-0 r/s/hc-0 r/w/hc-0 gcen ackstat ackdt acken (1) rcen (1) pen (1) rsen (1) sen (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared hc = cleared by hardware s = user set bit 7 gcen: general call enable bit (in i 2 c slave mode only) 1 = enable interrupt when a general call address (0x00 or 00h) is received in the sspxsr 0 = general call address disabled bit 6 ackstat: acknowledge status bit (in i 2 c mode only) 1 = acknowledge was not received 0 = acknowledge was received bit 5 ackdt: acknowledge data bit (in i 2 c mode only) in receive mode: value transmitted when the user initiates an acknowledge sequence at the end of a receive 1 = not acknowledge 0 = acknowledge bit 4 acken (1) : acknowledge sequence enable bit (in i 2 c master mode only) in master receive mode: 1 = initiate acknowledge sequence on sda and scl pins, and transmit ackdt data bit. automatically cleared by hardware. 0 = acknowledge sequence idle bit 3 rcen (1) : receive enable bit (in i 2 c master mode only) 1 = enables receive mode for i 2 c 0 = receive idle bit 2 pen (1) : stop condition enable bit (in i 2 c master mode only) sck r elease control: 1 = initiate stop condition on sda and scl pins. automatically cleared by hardware. 0 = stop condition idle bit 1 rsen (1) : repeated start condition enabled bit (in i 2 c master mode only) 1 = initiate repeated start condition on sda and scl pins. automatically cleared by hardware. 0 = repeated start condition idle bit 0 sen (1) : start condition enabled bit (in i 2 c master mode only) in master mode: 1 = initiate start condition on sda and scl pins. automatically cleared by hardware. 0 = start condition idle in slave mode: 1 = clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = clock stretching is disabled note 1: for bits acken, rcen, pen, rsen, sen: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling) and the sspxbuf may not be written (or writes to the sspxbuf are disabled). www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 265 pic18(l)f2x/45k50 register 16-4: sspxcon3: ss px control register 3 r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 acktim pcie scie boen sdaht sbcde ahen dhen bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 acktim: acknowledge time status bit (i 2 c mode only) (3) 1 = indicates the i 2 c bus is in an acknowledge sequence, set on 8 th falling edge of scl clock 0 = not an acknowledge sequence, cleared on 9 th rising edge of scl clock bit 6 pcie : stop condition interrupt enable bit (i 2 c mode only) 1 = enable interrupt on detection of stop condition 0 = stop detection interrupts are disabled (2) bit 5 scie : start condition interrupt enable bit (i 2 c mode only) 1 = enable interrupt on detection of start or restart conditions 0 = start detection interrupts are disabled (2) bit 4 boen: buffer overwrite enable bit in spi slave mode: (1) 1 = sspxbuf updates every time that a new data byte is shifted in ignoring the bf bit 0 = if new byte is received with bf bit of the sspxstat register already set, sspov bit of the sspxcon1 register is set, and the buffer is not updated in i 2 c master mode: this bit is ignored. in i 2 c slave mode: 1 = sspxbuf is updated and ack is generated for a received address/data byte, ignoring the state of the sspov bit only if the bf bit = 0 . 0 = sspxbuf is only updated when sspov is clear bit 3 sdaht: sda hold time selection bit (i 2 c mode only) 1 = minimum of 300 ns hold time on sda after the falling edge of scl 0 = minimum of 100 ns hold time on sda after the falling edge of scl bit 2 sbcde: slave mode bus collision detect enable bit (i 2 c slave mode only) if on the rising edge of scl, sda is sampled low when the module is outputting a high state, the bclif bit of the pir2 register is set, and bus goes idle 1 = enable slave bus collision interrupts 0 = slave bus collision interrupts are disabled bit 1 ahen: address hold enable bit (i 2 c slave mode only) 1 = following the 8th falling edge of scl for a matching received address byte; ckp bit of the sspxcon1 register will be cleared and the scl will be held low. 0 = address holding is disabled note 1: for daisy-chained spi operation; allows the user to ignore all but the last received byte. sspov is still set when a new byte is received and bf = 1 , but hardware continues to write the most recent byte to sspxbuf. 2: this bit has no effect in slave modes for which start and stop condition detection is explicitly listed as enabled. 3: the acktim status bit is active only when the ahen bit or dhen bit is set. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 266 ? 2012 microchip technology inc. bit 0 dhen: data hold enable bit (i 2 c slave mode only) 1 = following the 8th falling edge of scl for a received data byte; slave hardware clears the ckp bit of the sspxcon1 register and scl is held low. 0 = data holding is disabled register 16-4: sspxcon3: sspx co ntrol register 3 (continued) note 1: for daisy-chained spi operation; allows the user to ignore all but the last received byte. sspov is still set when a new byte is received and bf = 1 , but hardware continues to write the most recent byte to sspxbuf. 2: this bit has no effect in slave modes for which start and stop condition detection is explicitly listed as enabled. 3: the acktim status bit is active only when the ahen bit or dhen bit is set. register 16-5: sspxmsk: sspx mask register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-1 msk<7:1>: mask bits 1 = the received address bit n is compared to sspxadd ? 2012 microchip technology inc. ds30684a-page 267 pic18(l)f2x/45k50 register 16-6: sspxadd: mssp address and baud rate register (i 2 c mode) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 add<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared master mode: bit 7-0 add<7:0>: baud rate clock divider bits scl pin clock period = ((add<7:0> + 1) *4)/f osc 10-bit slave mode ? most significant address byte: bit 7-3 not used: unused for most significant address byte. bit state of this register is a ?don?t care?. bit pattern sent by master is fixed by i 2 c specification and must be equal to ? 11110 ?. however, those bits are compared by hardware and are not affected by the value in this register. bit 2-1 add<2:1>: two most significant bits of 10-bit address bit 0 not used: unused in this mode. bit state is a ?don?t care?. 10-bit slave mode ? least significant address byte: bit 7-0 add<7:0>: eight least significant bits of 10-bit address 7-bit slave mode: bit 7-1 add<7:1>: 7-bit address bit 0 not used: unused in this mode. bit state is a ?don?t care?. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 268 ? 2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 269 pic18(l)f2x/45k50 17.0 enhanced universal synchronous asynchronous receiver transmitter (eusart) the enhanced universal synchronous asynchronous receiver transmitter (eusart) module is a serial i/o communications peripheral. it contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. the eusart, also known as a serial communications interface (sci), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. full-duplex mode is useful for communications with peripheral systems, such as crt terminals and personal computers. half-duplex synchronous mode is intended for communications with peripheral devices, such as a/d or d/a integrated circuits, serial eeproms or other microcontrollers. these devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device. the eusart module includes the following capabilities: ? full-duplex asynchronous transmit and receive ? two-character input buffer ? one-character output buffer ? programmable 8-bit or 9-bit character length ? address detection in 9-bit mode ? input buffer overrun error detection ? received character framing error detection ? half-duplex synchronous master ? half-duplex synchronous slave ? programmable clock and data polarity the eusart module implements the following additional features, making it ideally suited for use in local interconnect network (lin) bus systems: ? automatic detection and calibration of the baud rate ? wake-up on break reception ? 13-bit break character transmit block diagrams of the eusart transmitter and receiver are shown in figure 17-1 and figure 17-2 . figure 17-1: eusart transmi t block diagram txif txie interrupt txen tx9d msb lsb data bus txregx register transmit shift register (tsr) (8) 0 tx9 trmt tx/ck pin pin buffer and control 8 spbrgx spbrghx brg16 f osc n n + 1 multiplier x4 x16 x64 sync 1x00 0 brgh x110 0 brg16 x101 0 baud rate generator ??? www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 270 ? 2012 microchip technology inc. figure 17-2: eusart receiv e block diagram the operation of the eusart module is controlled through three registers: ? transmit status and control (txstax) ? receive status and control (rcstax) ? baud rate control (baudconx) these registers are detailed in register 17-1 , register 17-2 and register 17-3 , respectively. for all modes of eusart operation, the tris control bits corresponding to the rx/dt and tx/ck pins should be set to ? 1 ?. the eusart control will automatically reconfigure the pin from input to output, as needed. when the receiver or transmitter section is not enabled then the corresponding rx/dt or tx/ck pin may be used for general purpose input and output. rx/dt pin pin buffer and control data recovery cren oerr ferr rsr register msb lsb rx9d rcregx register fifo interrupt rcif rcie data bus 8 stop start (8) 7 1 0 rx9 ? ? ? spbrgx spbrghx brg16 rcidl f osc n n + 1 multiplier x4 x16 x64 sync 1x00 0 brgh x110 0 brg16 x101 0 baud rate generator www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 271 pic18(l)f2x/45k50 17.1 eusart asynchronous mode the eusart transmits and receives data using the standard non-return-to-zero (nrz) format. nrz is implemented with two levels: a v oh mark state which represents a ? 1 ? data bit, and a v ol space state which represents a ? 0 ? data bit. nrz refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. an nrz transmission port idles in the mark state. each character transmission consists of one start bit followed by eight or nine data bits and is always terminated by one or more stop bits. the start bit is always a space and the stop bits are always marks. the most common data format is 8 bits. each transmitted bit persists for a period of 1/(baud rate). an on-chip dedicated 8-bit/16-bit baud rate generator is used to derive standard baud rate frequencies from the system oscillator. see table 17-5 for examples of baud rate configurations. the eusart transmits and receives the lsb first. the eusart?s transmitter and receiver are functionally independent, but share the same data format and baud rate. parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit. 17.1.1 eusart asynchronous transmitter the eusart transmitter block diagram is shown in figure 17-1 . the heart of the transmitter is the serial transmit shift register (tsr), which is not directly accessible by software. the tsr obtains its data from the transmit buffer, which is the txregx register. 17.1.1.1 enabling the transmitter the eusart transmitter is enabled for asynchronous operations by configuring the following three control bits: ?txen = 1 ? sync = 0 ? spen = 1 all other eusart control bits are assumed to be in their default state. setting the txen bit of the txstax register enables the transmitter circuitry of the eusart. clearing the sync bit of the txstax register configures the eusart for asynchronous operation. setting the spen bit of the rcstax register enables the eusart and automatically configures the tx/ck i/o pin as an output. if the tx/ck pin is shared with an analog peripheral the analog i/o function must be disabled by clearing the corresponding ansel bit. 17.1.1.2 transmitting data a transmission is initiated by writing a character to the txregx register. if this is the first character, or the previous character has been completely flushed from the tsr, the data in the txregx is immediately transferred to the tsr register. if the tsr still contains all or part of a previous character, the new character data is held in the txregx until the stop bit of the previous character has been transmitted. the pending character in the txregx is then transferred to the tsr in one t cy immediately following the stop bit transmission. the transmission of the start bit, data bits and stop bit sequence commences immediately following the transfer of the data to the tsr from the txregx. 17.1.1.3 transmit data polarity the polarity of the transmit data can be controlled with the txckp bit of the baudconx register. the default state of this bit is ? 0 ? which selects high true transmit idle and data bits. setting the txckp bit to ? 1 ? will invert the transmit data resulting in low true idle and data bits. the txckp bit controls transmit data polarity only in asynchronous mode. in synchronous mode the txckp bit has a different function. 17.1.1.4 transmit interrupt flag the txif interrupt flag bit of the pir1 register is set whenever the eusart transmitter is enabled and no character is being held for transmission in the txregx. in other words, the txif bit is only clear when the tsr is busy with a character and a new character has been queued for transmission in the txregx. the txif flag bit is not cleared immediately upon writing txregx. txif becomes valid in the second instruction cycle following the write execution. polling txif immediately following the txregx write will return invalid results. the txif bit is read-only, it cannot be set or cleared by software. the txif interrupt can be enabled by setting the txie interrupt enable bit of the pie1 register. however, the txif flag bit will be set whenever the txregx is empty, regardless of the state of txie enable bit. to use interrupts when transmitting data, set the txie bit only when there is more data to send. clear the txie interrupt enable bit upon writing the last character of the transmission to the txregx. note: the txif transmitter interrupt flag is set when the txen enable bit is set. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 272 ? 2012 microchip technology inc. 17.1.1.5 tsr status the trmt bit of the txstax register indicates the status of the tsr register. this is a read-only bit. the trmt bit is set when the tsr register is empty and is cleared when a character is transferred to the tsr register from the txregx. the trmt bit remains clear until all bits have been shifted out of the tsr register. no interrupt logic is tied to this bit, so the user needs to poll this bit to determine the tsr status. 17.1.1.6 transmitting 9-bit characters the eusart supports 9-bit character transmissions. when the tx9 bit of the txstax register is set the eusart will shift 9 bits out for each character transmit- ted. the tx9d bit of the txstax register is the ninth, and most significant, data bit. when transmitting 9-bit data, the tx9d data bit must be written before writing the 8 least significant bits into the txregx. all nine bits of data will be transferred to the tsr shift register immediately after the txregx is written. a special 9-bit address mode is available for use with multiple receivers. see section 17.1.2.8 ?address detection? for more information on the address mode. 17.1.1.7 asynchronous transmission setup: 1. initialize the spbrghx:spbrgx register pair and the brgh and brg16 bits to achieve the desired baud rate (see section 17.4 ?eusart baud rate generator (brg)? ). 2. set the rx/dt and tx/ck tris controls to ? 1 ?. 3. enable the asynchronous serial port by clearing the sync bit and setting the spen bit. 4. if 9-bit transmission is desired, set the tx9 control bit. a set ninth data bit will indicate that the eight least significant data bits are an address when the receiver is set for address detection. 5. set the txckp control bit if inverted transmit data polarity is desired. 6. enable the transmission by setting the txen control bit. this will cause the txif interrupt bit to be set. 7. if interrupts are desired, set the txie interrupt enable bit. an interrupt will occur immediately provided that the gie/gieh and peie/giel bits of the intcon register are also set. 8. if 9-bit transmission is selected, the ninth bit should be loaded into the tx9d data bit. 9. load 8-bit data into the txregx register. this will start the transmission. figure 17-3: asynchronous transmission note: the tsr register is not mapped in data memory, so it is not available to the user. word 1 stop bit word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txregx word 1 brg output (shift clock) tx/ck txif bit (transmit buffer reg. empty flag) trmt bit (transmit shift reg. empty flag) 1 t cy pin www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 273 pic18(l)f2x/45k50 figure 17-4: asynchronous transmiss ion (back-to-back) transmit shift reg write to txregx brg output (shift clock) tx/ck txif bit (interrupt reg. flag) trmt bit (transmit shift reg. empty flag) word 1 word 2 word 1 word 2 start bit stop bit start bit transmit shift reg word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions. 1 t cy 1 t cy pin table 17-1: registers associated with asynchronous transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baudcon1 abdovf rcidl rxdtp txckp brg16 ? wue abden 281 intcon gie/gieh peie/giel tmr0ie int0ie iocie tmr0if int0if iocif 120 ipr1 actip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 129 pie1 actie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 126 pir1 actif adif rcif txif sspif ccp1if tmr2if tmr1if 123 pmd0 ? uartmd usbmd actmd ? tmr3md tmr2md tmr1md 64 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 280 spbrg1 eusart baud rate generator, low byte ? spbrgh1 eusart baud rate generator, high byte ? txreg1 eusart transmit register ? txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 279 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used for asynchronous transmission. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 274 ? 2012 microchip technology inc. 17.1.2 eusart asynchronous receiver the asynchronous mode would typically be used in rs-232 systems. the receiver block diagram is shown in figure 17-2 . the data is received on the rx/dt pin and drives the data recovery block. the data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial receive shift register (rsr) operates at the bit rate. when all eight or nine bits of the character have been shifted in, they are immediately transferred to a two character first-in- first-out (fifo) memory. the fifo buffering allows reception of two complete characters and the start of a third character before software must start servicing the eusart receiver. the fifo and rsr registers are not directly accessible by software. access to the received data is via the rcregx register. 17.1.2.1 enabling the receiver the eusart receiver is enabled for asynchronous operation by configuring the following three control bits: ? cren = 1 ? sync = 0 ? spen = 1 all other eusart control bits are assumed to be in their default state. setting the cren bit of the rcstax register enables the receiver circuitry of the eusart. clearing the sync bit of the txstax register configures the eusart for asynchronous operation. setting the spen bit of the rcstax register enables the eusart. the rx/dt i/o pin must be configured as an input by setting the corresponding tris control bit. if the rx/dt pin is shared with an analog peripheral the analog i/o function must be disabled by clearing the corresponding ansel bit. 17.1.2.2 receiving data the receiver data recovery circuit initiates character reception on the falling edge of the first bit. the first bit, also known as the start bit, is always a zero. the data recovery circuit counts one-half bit time to the center of the start bit and verifies that the bit is still a zero. if it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the start bit. if the start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. the bit is then sampled by a majority detect circuit and the resulting ? 0 ? or ? 1 ? is shifted into the rsr. this repeats until all data bits have been sampled and shifted into the rsr. one final bit time is measured and the level sampled. this is the stop bit, which is always a ? 1 ?. if the data recovery circuit samples a ? 0 ? in the stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this character. see section 17.1.2.5 ?receive framing error? for more information on framing errors. immediately after all data bits and the stop bit have been received, the character in the rsr is transferred to the eusart receive fifo and the rcif interrupt flag bit of the pir1 register is set. the top character in the fifo is transferred out of the fifo by reading the rcregx register. 17.1.2.3 receive data polarity the polarity of the receive data can be controlled with the rxdtp bit of the baudconx register. the default state of this bit is ? 0 ? which selects high true receive idle and data bits. setting the rxdtp bit to ? 1 ? will invert the receive data resulting in low true idle and data bits. the rxdtp bit controls receive data polarity only in asynchronous mode. in synchronous mode the rxdtp bit has a different function. note: if the receive fifo is overrun, no additional characters will be received until the overrun condition is cleared. see section 17.1.2.6 ?receive overrun error? for more information on overrun errors. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 275 pic18(l)f2x/45k50 17.1.2.4 receive interrupts the rcif interrupt flag bit of the pir1 register is set whenever the eusart receiver is enabled and there is an unread character in the receive fifo. the rcif interrupt flag bit is read-only, it cannot be set or cleared by software. rcif interrupts are enabled by setting the following bits: ? rcie interrupt enable bit of the pie1 register ? peie/giel peripheral interrupt enable bit of the intcon register ? gie/gieh global interrupt enable bit of the intcon register the rcif interrupt flag bit will be set when there is an unread character in the fifo, regardless of the state of interrupt enable bits. 17.1.2.5 receive framing error each character in the receive fifo buffer has a corresponding framing error status bit. a framing error indicates that a stop bit was not seen at the expected time. the framing error status is accessed via the ferr bit of the rcstax register. the ferr bit represents the status of the top unread character in the receive fifo. therefore, the ferr bit must be read before reading the rcregx. the ferr bit is read-only and only applies to the top unread character in the receive fifo. a framing error (ferr = 1 ) does not preclude reception of additional characters. it is not necessary to clear the ferr bit. reading the next character from the fifo buffer will advance the fifo to the next character and the next corresponding framing error. the ferr bit can be forced clear by clearing the spen bit of the rcstax register which resets the eusart. clearing the cren bit of the rcstax register does not affect the ferr bit. a framing error by itself does not generate an interrupt. 17.1.2.6 receive overrun error the receive fifo buffer can hold two characters. an overrun error will be generated if a third character, in its entirety, is received before the fifo is accessed. when this happens the oerr bit of the rcstax register is set. the characters already in the fifo buffer can be read but no additional characters will be received until the error is cleared. the error must be cleared by either clearing the cren bit of the rcstax register or by resetting the eusart by clearing the spen bit of the rcstax register. 17.1.2.7 receiving 9-bit characters the eusart supports 9-bit character reception. when the rx9 bit of the rcstax register is set, the eusart will shift nine bits into the rsr for each character received. the rx9d bit of the rcstax register is the ninth and most significant data bit of the top unread character in the receive fifo. when reading 9-bit data from the receive fifo buffer, the rx9d data bit must be read before reading the eight least significant bits from the rcregx. 17.1.2.8 address detection a special address detection mode is available for use when multiple receivers share the same transmission line, such as in rs-485 systems. address detection is enabled by setting the adden bit of the rcstax register. address detection requires 9-bit character reception. when address detection is enabled, only characters with the ninth data bit set will be transferred to the receive fifo buffer, thereby setting the rcif interrupt bit. all other characters will be ignored. upon receiving an address character, user software determines if the address matches its own. upon address match, user software must disable address detection by clearing the adden bit before the next stop bit occurs. when user software detects the end of the message, determined by the message protocol used, software places the receiver back into the address detection mode by setting the adden bit. note: if all receive characters in the receive fifo have framing errors, repeated reads of the rcregx will not clear the ferr bit. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 276 ? 2012 microchip technology inc. 17.1.2.9 asynchronous reception setup: 1. initialize the spbrghx:spbrgx register pair and the brgh and brg16 bits to achieve the desired baud rate (see section 17.4 ?eusart baud rate generator (brg)? ). 2. set the rx/dt and tx/ck tris controls to ? 1 ?. 3. enable the serial port by setting the spen bit and the rx/dt pin tris bit. the sync bit must be clear for asynchronous operation. 4. if interrupts are desired, set the rcie interrupt enable bit and set the gie/gieh and peie/giel bits of the intcon register. 5. if 9-bit reception is desired, set the rx9 bit. 6. set the rxdtp if inverted receive polarity is desired. 7. enable reception by setting the cren bit. 8. the rcif interrupt flag bit will be set when a character is transferred from the rsr to the receive buffer. an interrupt will be generated if the rcie interrupt enable bit was also set. 9. read the rcstax register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit. 10. get the received eight least significant data bits from the receive buffer by reading the rcregx register. 11. if an overrun occurred, clear the oerr flag by clearing the cren receiver enable bit. 17.1.2.10 9-bit address detection mode setup this mode would typically be used in rs-485 systems. to set up an asynchronous reception with address detect enable: 1. initialize the spbrghx, spbrgx register pair and the brgh and brg16 bits to achieve the desired baud rate (see section 17.4 ?eusart baud rate generator (brg)? ). 2. set the rx/dt and tx/ck tris controls to ? 1 ?. 3. enable the serial port by setting the spen bit. the sync bit must be clear for asynchronous operation. 4. if interrupts are desired, set the rcie interrupt enable bit and set the gie/gieh and peie/giel bits of the intcon register. 5. enable 9-bit reception by setting the rx9 bit. 6. enable address detection by setting the adden bit. 7. set the rxdtp if inverted receive polarity is desired. 8. enable reception by setting the cren bit. 9. the rcif interrupt flag bit will be set when a character with the ninth bit set is transferred from the rsr to the receive buffer. an interrupt will be generated if the rcie interrupt enable bit was also set. 10. read the rcstax register to get the error flags. the ninth data bit will always be set. 11. get the received eight least significant data bits from the receive buffer by reading the rcregx register. software determines if this is the device?s address. 12. if an overrun occurred, clear the oerr flag by clearing the cren receiver enable bit. 13. if the device has been addressed, clear the adden bit to allow all received data into the receive buffer and generate interrupts. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 277 pic18(l)f2x/45k50 figure 17-5: asynchronous reception start bit bit 7/8 bit 1 bit 0 bit 7/8 bit 0 stop bit start bit start bit bit 7/8 stop bit rx/dt pin reg rcv buffer reg rcv shift read rcv buffer reg rcregx rcif (interrupt flag) oerr bit cren word 1 rcregx word 2 rcregx stop bit note: this timing diagram shows three words appearing on the rx/dt input. the rcregx (receive buffer) is read after the third word, causing the oerr (overrun) bit to be set. rcidl table 17-2: registers associated with asynchronous reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baudcon1 abdovf rcidl rxdtp txckp brg16 ? wue abden 281 intcon gie/gieh peie/giel tmr0ie int0ie iocie tmr0if int0if iocif 120 ipr1 actip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 129 pie1 actie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 126 pir1 actif adif rcif txif sspif ccp1if tmr2if tmr1if 123 pmd0 ?uartmd usbmd actmd ? tmr3md tmr2md tmr1md 64 rcreg1 eusart receive register ? rcsta1 spen rx9 sren cren adden ferr oerr rx9d 280 spbrg1 eusart baud rate generator, low byte ? spbrgh1 eusart baud rate generator, high byte ? trisc trisc7 trisc6 ? ? ? trisc2 trisc1 trisc0 156 txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 279 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used for asynchronous reception. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 278 ? 2012 microchip technology inc. 17.2 clock accuracy with asynchronous operation the factory calibrates the internal oscillator block output (hfintosc). however, the hfintosc frequency may drift as v dd or temperature changes, and this directly affects the asynchronous baud rate. two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. the first (preferred) method uses the osctune register to adjust the hfintosc output. adjusting the value in the osctune register allows for fine resolution changes to the system clock source. see 3.6 ?internal clock modes? for more information. the other method adjusts the value in the baud rate generator. this can be done automatically with the auto-baud detect feature (see section 17.4.1 ?auto- baud detect? ). there may not be fine enough resolution when adjusting the baud rate generator to compensate for a gradual change in the peripheral clock frequency. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 279 pic18(l)f2x/45k50 17.3 register definitions: eusart control register 17-1: txstax: transmit status and control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-1 r/w-0 csrc tx9 txen (1) sync sendb brgh trmt tx9d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 csrc: clock source select bit asynchronous mode : don?t care synchronous mode : 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6 tx9: 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5 txen: transmit enable bit (1) 1 = transmit enabled 0 = transmit disabled bit 4 sync: eusart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3 sendb: send break character bit asynchronous mode : 1 = send sync break on next transmission (cleared by hardware upon completion) 0 = sync break transmission completed synchronous mode : don?t care bit 2 brgh: high baud rate select bit asynchronous mode : 1 = high speed 0 = low speed synchronous mode: unused in this mode bit 1 trmt: transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0 tx9d: ninth bit of transmit data can be address/data bit or a parity bit. note 1: sren/cren overrides txen in sync mode. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 280 ? 2012 microchip technology inc. register 17-2: rcstax: receiv e status and control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-0 spen rx9 sren cren adden ferr oerr rx9d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 spen: serial port enable bit 1 = serial port enabled (configures rx/dt and tx/ck pins as serial port pins) 0 = serial port disabled (held in reset) bit 6 rx9: 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5 sren: single receive enable bit asynchronous mode : don?t care synchronous mode ? master : 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode ? slave don?t care bit 4 cren: continuous receive enable bit asynchronous mode : 1 = enables receiver 0 = disables receiver synchronous mode : 1 = enables continuous receive until enable bit cren is cleared (cren overrides sren) 0 = disables continuous receive bit 3 adden: address detect enable bit asynchronous mode 9-bit (rx9 = 1 ) : 1 = enables address detection, enable interrupt and load the receive buffer when rsr<8> is set 0 = disables address detection, all bytes are received and ninth bit can be used as parity bit asynchronous mode 8-bit (rx9 = 0 ) : don?t care bit 2 ferr: framing error bit 1 = framing error (can be updated by reading rcregx register and receive next valid byte) 0 = no framing error bit 1 oerr: overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0 rx9d: ninth bit of received data this can be address/data bit or a parity bit and must be calculated by user firmware. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 281 pic18(l)f2x/45k50 register 17-3: baudconx: baud rate control register r/w-0 r-1 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 abdovf rcidl rxdtp txckp brg16 ? wue abden bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 abdovf: auto-baud detect overflow bit asynchronous mode : 1 = auto-baud timer overflowed 0 = auto-baud timer did not overflow synchronous mode : don?t care bit 6 rcidl : receive idle flag bit asynchronous mode : 1 = receiver is idle 0 = start bit has been detected and the receiver is active synchronous mode : don?t care bit 5 rxdtp : data/receive polarity select bit asynchronous mode : 1 = receive data (rx) is inverted (active-low) 0 = receive data (rx) is not inverted (active-high) synchronous mode : 1 = data (dt) is inverted (active-low) 0 = data (dt) is not inverted (active-high) bit 4 txckp : clock/transmit polarity select bit asynchronous mode : 1 = idle state for transmit (tx) is low 0 = idle state for transmit (tx) is high synchronous mode : 1 = data changes on the falling edge of the clock and is sampled on the rising edge of the clock 0 = data changes on the rising edge of the clock and is sampled on the falling edge of the clock bit 3 brg16: 16-bit baud rate generator bit 1 = 16-bit baud rate generator is used (spbrghx:spbrgx) 0 = 8-bit baud rate generator is used (spbrgx) bit 2 unimplemented: read as ? 0 ? bit 1 wue: wake-up enable bit asynchronous mode : 1 = receiver is waiting for a falling edge. no character will be received but rcif will be set on the falling edge. wue will automatically clear on the rising edge. 0 = receiver is operating normally synchronous mode : don?t care bit 0 abden : auto-baud detect enable bit asynchronous mode : 1 = auto-baud detect mode is enabled (clears when auto-baud is complete) 0 = auto-baud detect mode is disabled synchronous mode : don?t care www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 282 ? 2012 microchip technology inc. 17.4 eusart baud rate generator (brg) the baud rate generator (brg) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous eusart operation. by default, the brg operates in 8-bit mode. setting the brg16 bit of the baudconx register selects 16-bit mode. the spbrghx:spbrgx register pair determines the period of the free running baud rate timer. in asynchronous mode the multiplier of the baud rate period is determined by both the brgh bit of the txstax register and the brg16 bit of the baudconx register. in synchronous mode, the brgh bit is ignored. table 17-3 contains the formulas for determining the baud rate. example 17-1 provides a sample calculation for determining the baud rate and baud rate error. typical baud rates and error values for various asynchronous modes have been computed for your convenience and are shown in table 17-5 . it may be advantageous to use the high baud rate (brgh = 1 ), or the 16-bit brg (brg16 = 1 ) to reduce the baud rate error. the 16-bit brg mode is used to achieve slow baud rates for fast oscillator frequencies. writing a new value to the spbrghx, spbrgx register pair causes the brg timer to be reset (or cleared). this ensures that the brg does not wait for a timer overflow before outputting the new baud rate. if the system clock is changed during an active receive operation, a receive error or data loss may result. to avoid this problem, check the status of the rcidl bit to make sure that the receive operation is idle before changing the system clock. example 17-1: calculating baud rate error for a device with f osc of 16 mhz, desired baud rate of 9600, asynchronous mode, 8-bit brg: solving for spbrghx:spbrgx: x f osc desired baud rate --------------------------------------------- 64 --------------------------------------------- 1 ? = desired baud rate f osc 64 [spbrghx:spbrgx] 1 + ?? ------------------------------------------------------------------------- - = 16000000 9600 ----------------------- - 64 ----------------------- -1 ? = 25.042 ?? 25 == calculated baud rate 16000000 64 25 1 + ?? -------------------------- - = 9615 = error calc. baud rate desired baud rate ? desired baud rate -------------------------------------------------------------------------------------------- = 9615 9600 ? ?? 9600 ---------------------------------- 0 . 1 6 % == table 17-3: baud rate formulas configuration bits brg/eusart mode baud rate formula sync brg16 brgh 000 8-bit/asynchronous f osc /[64 (n+1)] 001 8-bit/asynchronous f osc /[16 (n+1)] 010 16-bit/asynchronous 011 16-bit/asynchronous f osc /[4 (n+1)] 10x 8-bit/synchronous 11x 16-bit/synchronous legend: x = don?t care, n = value of spbrghx, spbrgx register pair. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 283 pic18(l)f2x/45k50 table 17-4: registers associated with baud rate generator name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baudcon1 abdovf rcidl rxdtp txckp brg16 ? wue abden 281 pmd0 ? uartmd usbmd actmd ? tmr3md tmr2md tmr1md 64 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 280 spbrg1 eusart baud rate generator, low byte ? spbrgh1 eusart baud rate generator, high byte ? pir1 actif adif rcif txif sspif ccp1if tmr2if tmr1if 123 txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 279 legend: ? = unimplemented, read as ? 0 ?. shaded bits are not used by the brg. table 17-5: baud rates for asynchronous modes baud rate sync = 0 , brgh = 0 , brg16 = 0 f osc = 48.000 mhz f osc = 18.432 mhz f osc = 16.000 mhz f osc = 11.0592 mhz actual rate % error spbrxg value (decimal) actual rate % error spbrgx value (decimal) actual rate % error spbrgx value (decimal) actual rate % error spbrgx value (decimal) 300 ? ? ? ? ? ? ? ? ? ? ? ? 1200 ?? ? 1200 0.00 239 1202 0.16 207 1200 0.00 143 2400 ?? ? 2400 0.00 119 2404 0.16 103 2400 0.00 71 9600 9615 0.16 77 9600 0.00 29 9615 0.16 25 9600 0.00 17 10417 10417 0.00 71 10286 -1.26 27 10417 0.00 23 10165 -2.42 16 19.2k 19.23k 0.16 38 19.20k 0.00 14 19.23k 0.16 12 19.20k 0.00 8 57.6k 57.69k 0.16 12 57.60k 0.00 7 ?? ? 57.60k 0.00 2 115.2k ? ? ? ? ? ? ? ? ? ? ? ? baud rate sync = 0 , brgh = 0 , brg16 = 0 f osc = 8.000 mhz f osc = 4.000 mhz f osc = 3.6864 mhz f osc = 1.000 mhz actual rate % error spbrgx value (decimal) actual rate % error spbrgx value (decimal) actual rate % error spbrgx value (decimal) actual rate % error spbrgx value (decimal) 300 ? ? ? 300 0.16 207 300 0.00 191 300 0.16 51 1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 ? ? ? 9600 9615 0.16 12 ? ? ? 9600 0.00 5 ? ? ? 10417 10417 0.00 11 10417 0.00 5 ? ? ? ? ? ? 19.2k ? ? ? ? ? ? 19.20k 0.00 2 ? ? ? 57.6k ? ? ? ? ? ? 57.60k 0.00 0 ? ? ? 115.2k ? ? ? ? ? ? ? ? ? ? ? ? www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 284 ? 2012 microchip technology inc. baud rate sync = 0 , brgh = 1 , brg16 = 0 f osc = 48.000 mhz f osc = 18.432 mhz f osc = 16.000 mhz f osc = 11.0592 mhz actual rate % error spbrgx value (decimal) actual rate % error spbrgx value (decimal) actual rate % error spbrgx value (decimal) actual rate % error spbrgx value (decimal) 300 ?? ? ?? ? ? ? ? ? ? ? 1200 ? ? ? ? ? ? ? ? ? ? ? ? 2400 ? ? ? ? ? ? ?? ? ?? ? 9600 ? ? ? 9600 0.00 119 9615 0.16 103 9600 0.00 71 10417 ? ? ? 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 155 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 57.97k 0.16 51 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11 115.2k 115.39k 0.16 25 115.2k 0.00 9 111.1k -3.55 8 115.2k 0.00 5 baud rate sync = 0 , brgh = 1 , brg16 = 0 f osc = 8.000 mhz f osc = 4.000 mhz f osc = 3.6864 mhz f osc = 1.000 mhz actual rate % error spbrgx value (decimal) actual rate % error spbrgx value (decimal) actual rate % error sxbrgx value (decimal) actual rate % error spbrgx value (decimal) 300 ?? ? ? ? ? ? ? ? 300 0.16 207 1200 ? ? ? 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 ? ? ? 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 ? ? ? 57.6k 55556 -3.55 8 ? ? ? 57.60k 0.00 3 ? ? ? 115.2k ? ? ? ? ? ? 115.2k 0.00 1 ? ? ? baud rate sync = 0 , brgh = 0 , brg16 = 1 f osc = 48.000 mhz f osc = 18.432 mhz f osc = 16.000 mhz f osc = 11.0592 mhz actual rate % error spbrghx: spbrgx (decimal) actual rate % error spbrghx: spbrgx (decimal) actual rate % error spbrghx :spbrgx (decimal) actual rate % error spbrghx: spbrgx (decimal) 300 300.0 0.00 9999 300.0 0.00 3839 300.03 0.01 3332 300.0 0.00 2303 1200 1200 0.00 2499 1200 0.00 959 1200.5 0.04 832 1200 0.00 575 2400 2400 0.00 1249 2400 0.00 479 2398 -0.08 416 2400 0.00 287 9600 9585 -0.16 312 9600 0.00 119 9615 0.16 103 9600 0.00 71 10417 10417 0.00 287 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 155 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 57.69k 0.16 51 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11 115.2k 115.39k 0.16 25 115.2k 0.00 9 111.11k -3.55 8 115.2k 0.00 5 table 17-5: baud rates for asynchronous modes (continued) www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 285 pic18(l)f2x/45k50 baud rate sync = 0 , brgh = 0 , brg16 = 1 f osc = 8.000 mhz f osc = 4.000 mhz f osc = 3.6864 mhz f osc = 1.000 mhz actual rate % error spbrghx: spbrgx (decimal) actual rate % error spbrghx: spbrgx (decimal) actual rate % error spbrghx :spbrgx (decimal) actual rate % error spbrghx: spbrgx (decimal) 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207 1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 ? ? ? 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 ? ? ? 57.6k 55556 -3.55 8 ? ? ? 57.60k 0.00 3 ? ? ? 115.2k ? ? ? ? ? ? 115.2k 0.00 1 ? ? ? baud rate sync = 0 , brgh = 1 , brg16 = 1 or sync = 1 , brg16 = 1 f osc = 48.000 mhz f osc = 18.432 mhz f osc = 16.000 mhz f osc = 11.0592 mhz actual rate % error spbrghx: spbrgx (decimal) actual rate % error spbrghx: spbrgx (decimal) actual rate % error spbrghx :spbrgx (decimal) actual rate % error spbrghx: spbrgx (decimal) 300 300 0.00 39999 300.0 0.00 15359 300.0 0.00 13332 300.0 0.00 9215 1200 1200 0.00 9999 1200 0.00 3839 1200.1 0.01 3332 1200 0.00 2303 2400 2400 0.00 4999 2400 0.00 1919 2399.5 -0.02 1666 2400 0.00 1151 9600 9600 0.00 1249 9600 0.00 479 9592 -0.08 416 9600 0.00 287 10417 10417 0.00 1151 10425 0.08 441 10417 0.00 383 10433 0.16 264 19.2k 19.2k 0.00 624 19.20k 0.00 239 19.23k 0.16 207 19.20k 0.00 143 57.6k 57.69k 0.16 207 57.60k 0.00 79 57.97k 0.64 68 57.60k 0.00 47 115.2k 115.39k 0.16 103 115.2k 0.00 39 114.29k -0.79 34 115.2k 0.00 23 baud rate sync = 0 , brgh = 1 , brg16 = 1 or sync = 1 , brg16 = 1 f osc = 8.000 mhz f osc = 4.000 mhz f osc = 3.6864 mhz f osc = 1.000 mhz actual rate % error spbrghx: spbrgx (decimal) actual rate % error spbrghx: spbrgx (decimal) actual rate % error spbrghx :spbrgx (decimal) actual rate % error spbrghx: spbrgx (decimal) 300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832 1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 10417 10417 0.00 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 ? ? ? 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 ? ? ? table 17-5: baud rates for asynchronous modes (continued) www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 286 ? 2012 microchip technology inc. 17.4.1 auto-baud detect the eusart module supports automatic detection and calibration of the baud rate. in the auto-baud detect (abd) mode, the clock to the brg is reversed. rather than the brg clocking the incoming rx signal, the rx signal is timing the brg. the baud rate generator is used to time the period of a received 55h (ascii ?u?) which is the sync character for the lin bus. the unique feature of this character is that it has five rising edges including the stop bit edge. setting the abden bit of the baudconx register starts the auto-baud calibration sequence ( section 17.4.2 ?auto-baud overflow? ). while the abd sequence takes place, the eusart state machine is held in idle. on the first rising edge of the receive line, after the start bit, the spbrgx begins counting up using the brg counter clock as shown in table 17-6 . the fifth rising edge will occur on the rx/ dt pin at the end of the eighth bit period. at that time, an accumulated value totaling the proper brg period is left in the spbrghx:spbrgx register pair, the abden bit is automatically cleared, and the rcif interrupt flag is set. a read operation on the rcregx needs to be performed to clear the rcif interrupt. rcregx content should be discarded. when calibrating for modes that do not use the spbrghx register the user can verify that the spbrgx register did not overflow by checking for 00h in the spbrghx register. the brg auto-baud clock is determined by the brg16 and brgh bits as shown in table 17-6 . during abd, both the spbrghx and spbrgx registers are used as a 16-bit counter, independent of the brg16 bit setting. while calibrating the baud rate period, the spbrghx and spbrgx registers are clocked at 1/8th the brg base clock rate. the resulting byte measurement is the average bit time when clocked at full speed. figure 17-6: automatic baud rate calibration note 1: if the wue bit is set with the abden bit, auto-baud detection will occur on the byte following the break character (see section 17.4.3 ?auto-wake-up on break? ). 2: it is up to the user to determine that the incoming character baud rate is within the range of the selected brg clock source. some combinations of oscillator frequency and eusart baud rates are not possible. 3: during the auto-baud process, the auto- baud counter starts counting at 1. upon completion of the auto-baud sequence, to achieve maximum accuracy, subtract 1 from the spbrghx:spbrgx register pair. table 17-6: brg counter clock rates brg16 brgh brg base clock brg abd clock 00 f osc /64 f osc /512 01 f osc /16 f osc /128 10 f osc /16 f osc /128 11 f osc /4 f osc /32 note: during the abd sequence, spbrgx and spbrghx registers are both used as a 16-bit counter, independent of brg16 setting. brg value rx/dt pin abden bit rcif bit bit 0 bit 1 (interrupt) read rcregx brg clock start auto cleared set by user xxxxh 0000h edge #1 bit 2 bit 3 edge #2 bit 4 bit 5 edge #3 bit 6 bit 7 edge #4 stop bit edge #5 001ch note 1: the abd sequence requires the eusart module to be configured in asynchronous mode. spbrgx xxh 1ch spbrghx xxh 00h rcidl www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 287 pic18(l)f2x/45k50 17.4.2 auto-baud overflow during the course of automatic baud detection, the abdovf bit of the baudconx register will be set if the baud rate counter overflows before the fifth rising edge is detected on the rx pin. the abdovf bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the spbrghx:spbrgx register pair. after the abdovf has been set, the counter con- tinues to count until the fifth rising edge is detected on the rx/dt pin. upon detecting the fifth rx/dt edge, the hardware will set the rcif interrupt flag and clear the abden bit of the baudconx register. the rcif flag can be subsequently cleared by reading the rcregx. the abdovf flag can be cleared by software directly. to terminate the auto-baud process before the rcif flag is set, clear the abden bit then clear the abdovf bit. the abdovf bit will remain set if the abden bit is not cleared first. 17.4.3 auto-wake-up on break during sleep mode, all clocks to the eusart are suspended. because of this, the baud rate generator is inactive and a proper character reception cannot be performed. the auto-wake-up feature allows the controller to wake-up due to activity on the rx/dt line. this feature is available only in asynchronous mode. the auto-wake-up feature is enabled by setting the wue bit of the baudconx register. once set, the normal receive sequence on rx/dt is disabled, and the eusart remains in an idle state, monitoring for a wake-up event independent of the cpu mode. a wake- up event consists of a high-to-low transition on the rx/ dt line. (this coincides with the start of a sync break or a wake-up signal character for the lin protocol.) the eusart module generates an rcif interrupt coincident with the wake-up event. the interrupt is generated synchronously to the q clocks in normal cpu operating modes ( figure 17-7 ), and asynchronously if the device is in sleep mode ( figure 17-8 ). the interrupt condition is cleared by reading the rcregx register. the wue bit is automatically cleared by the low-to-high transition on the rx line at the end of the break. this signals to the user that the break event is over. at this point, the eusart module is in idle mode waiting to receive the next character. 17.4.3.1 special considerations break character to avoid character errors or character fragments during a wake-up event, the wake-up character must be all zeros. when the wake-up is enabled the function works independent of the low time on the data stream. if the wue bit is set and a valid non-zero character is received, the low time from the start bit to the first rising edge will be interpreted as the wake-up event. the remaining bits in the character will be received as a fragmented character and subsequent characters can result in framing or overrun errors. therefore, the initial character in the transmission must be all ? 0 ?s. this must be 10 or more bit times, 13-bit times recommended for lin bus, or any number of bit times for standard rs-232 devices. oscillator startup time oscillator start-up time must be considered, especially in applications using oscillators with longer start-up intervals (i.e., lp, xt or hs/pll mode). the sync break (or wake-up signal) character must be of sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper initialization of the eusart. wue bit the wake-up event causes a receive interrupt by setting the rcif bit. the wue bit is cleared by hardware by a rising edge on rx/dt. the interrupt condition is then cleared by software by reading the rcregx register and discarding its contents. to ensure that no actual data is lost, check the rcidl bit to verify that a receive operation is not in process before setting the wue bit. if a receive operation is not occurring, the wue bit may then be set just prior to entering the sleep mode. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 288 ? 2012 microchip technology inc. figure 17-7: auto-wake-up bit (wue) timing during normal operation figure 17-8: auto-wake-up bit (wue) timings during sleep q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 wue bit rx/dt line rcif bit set by user auto cleared cleared due to user read of rcregx note 1: the eusart remains in idle while the wue bit is set. q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 wue bit rx/dt line rcif bit set by user auto cleared cleared due to user read of rcregx sleep command executed note 1 note 1: if the wake-up event requires long oscillator warm-up time, the automatic clearing of the wue bit can occur while the stposc signal is still active. this sequence should not depend on the presence of q clocks. 2: the eusart remains in idle while the wue bit is set. sleep ends www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 289 pic18(l)f2x/45k50 17.4.4 break character sequence the eusart module has the capability of sending the special break character sequences that are required by the lin bus standard. a break character consists of a start bit, followed by 12 ? 0 ? bits and a stop bit. to send a break character, set the sendb and txen bits of the txstax register. the break character trans- mission is then initiated by a write to the txregx. the value of data written to txregx will be ignored and all ? 0 ?s will be transmitted. the sendb bit is automatically reset by hardware after the corresponding stop bit is sent. this allows the user to preload the transmit fifo with the next transmit byte following the break character (typically, the sync character in the lin specification). the trmt bit of the txstax register indicates when the transmit operation is active or idle, just as it does during normal transmission. see figure 17-9 for the timing of the break character sequence. 17.4.4.1 break and sync transmit sequence the following sequence will start a message frame header made up of a break, followed by an auto-baud sync byte. this sequence is typical of a lin bus master. 1. configure the eusart for the desired mode. 2. set the txen and sendb bits to enable the break sequence. 3. load the txregx with a dummy character to initiate transmission (the value is ignored). 4. write ?55h? to txregx to load the sync charac- ter into the transmit fifo buffer. 5. after the break has been sent, the sendb bit is reset by hardware and the sync character is then transmitted. when the txregx becomes empty, as indicated by the txif, the next data byte can be written to txregx. 17.4.5 receiving a break character the enhanced eusart module can receive a break character in two ways. the first method to detect a break character uses the ferr bit of the rcstax register and the received data as indicated by rcregx. the baud rate generator is assumed to have been initialized to the expected baud rate. a break character has been received when; ? rcif bit is set ? ferr bit is set ? rcregx = 00h the second method uses the auto-wake-up feature described in section 17.4.3 ?auto-wake-up on break? . by enabling this feature, the eusart will sample the next two transitions on rx/dt, cause an rcif interrupt, and receive the next data byte followed by another interrupt. note that following a break character, the user will typically want to enable the auto-baud detect feature. for both methods, the user can set the abden bit of the baudconx register before placing the eusart in sleep mode. figure 17-9: send break character sequence write to txregx dummy write brg output (shift clock) start bit bit 0 bit 1 bit 11 stop bit break txif bit (transmit interrupt flag) tx/ck (pin) trmt bit (transmit shift reg. empty flag) sendb (send break control bit) sendb sampled here auto cleared www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 290 ? 2012 microchip technology inc. 17.5 eusart synchronous mode synchronous serial communications are typically used in systems with a single master and one or more slaves. the master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. there are two signal lines in synchronous mode: a bidirectional data line and a clock line. slaves use the external clock supplied by the master to shift the serial data into and out of their respective receive and transmit shift registers. since the data line is bidirectional, synchronous operation is half-duplex only. half-duplex refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. the eusart can operate as either a master or slave device. start and stop bits are not used in synchronous transmissions. 17.5.1 synchronous master mode the following bits are used to configure the eusart for synchronous master operation: ? sync = 1 ? csrc = 1 ? sren = 0 (for transmit); sren = 1 (for receive) ? cren = 0 (for transmit); cren = 1 (for receive) ? spen = 1 setting the sync bit of the txstax register configures the device for synchronous operation. setting the csrc bit of the txstax register configures the device as a master. clearing the sren and cren bits of the rcstax register ensures that the device is in the transmit mode, otherwise the device will be configured to receive. setting the spen bit of the rcstax register enables the eusart. if the rx/dt or tx/ck pins are shared with an analog peripheral the analog i/o functions must be disabled by clearing the corresponding ansel bits. the tris bits corresponding to the rx/dt and tx/ ck pins should be set. 17.5.1.1 master clock synchronous data transfers use a separate clock line, which is synchronous with the data. a device configured as a master transmits the clock on the tx/ck line. the tx/ck pin output driver is automatically enabled when the eusart is configured for synchronous transmit or receive operation. serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. one clock cycle is generated for each data bit. only as many clock cycles are generated as there are data bits. 17.5.1.2 clock polarity a clock polarity option is provided for microwire compatibility. clock polarity is selected with the txckp bit of the baudconx register. setting the txckp bit sets the clock idle state as high. when the txckp bit is set, the data changes on the falling edge of each clock and is sampled on the rising edge of each clock. clearing the txckp bit sets the idle state as low. when the txckp bit is cleared, the data changes on the rising edge of each clock and is sampled on the falling edge of each clock. 17.5.1.3 synchronous master transmission data is transferred out of the device on the rx/dt pin. the rx/dt and tx/ck pin output drivers are automat- ically enabled when the eusart is configured for synchronous master transmit operation. a transmission is initiated by writing a character to the txregx register. if the tsr still contains all or part of a previous character the new character data is held in the txregx until the last bit of the previous character has been transmitted. if this is the first character, or the previous character has been completely flushed from the tsr, the data in the txregx is immediately trans- ferred to the tsr. the transmission of the character commences immediately following the transfer of the data to the tsr from the txregx. each data bit changes on the leading edge of the master clock and remains valid until the subsequent leading clock edge. 17.5.1.4 data polarity the polarity of the transmit and receive data can be controlled with the rxdtp bit of the baudconx register. the default state of this bit is ? 0 ? which selects high true transmit and receive data. setting the rxdtp bit to ? 1 ? will invert the data resulting in low true transmit and receive data. note: the tsr register is not mapped in data memory, so it is not available to the user. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 291 pic18(l)f2x/45k50 17.5.1.5 synchronous master transmission setup: 1. initialize the spbrghx, spbrgx register pair and the brgh and brg16 bits to achieve the desired baud rate (see section 17.4 ?eusart baud rate generator (brg)? ). 2. set the rx/dt and tx/ck tris controls to ? 1 ?. 3. enable the synchronous master serial port by setting bits sync, spen and csrc. set the tris bits corresponding to the rx/dt and tx/ ck i/o pins. 4. disable receive mode by clearing bits sren and cren. 5. enable transmit mode by setting the txen bit. 6. if 9-bit transmission is desired, set the tx9 bit. 7. if interrupts are desired, set the txie, gie/gieh and peie/giel interrupt enable bits. 8. if 9-bit transmission is selected, the ninth bit should be loaded in the tx9d bit. 9. start transmission by loading data to the txregx register. figure 17-10: synchronous transmission figure 17-11: synchronous transmis sion (through txen) bit 0 bit 1 bit 7 word 1 bit 2 bit 0 bit 1 bit 7 rx/dt write to txregx reg txif bit (interrupt flag) txen bit ? 1 ? ? 1 ? word 2 trmt bit write word 1 write word 2 note: sync master mode, spbrgx = 0 , continuous transmission of two 8-bit words. pin tx/ck pin tx/ck pin (sckp = 0 ) (sckp = 1 ) rx/dt pin tx/ck pin write to txregx reg txif bit trmt bit bit 0 bit 1 bit 2 bit 6 bit 7 txen bit www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 292 ? 2012 microchip technology inc. table 17-7: registers associated wi th synchronous master transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baudcon1 abdovf rcidl rxdtp txckp brg16 ? wue abden 281 intcon gie/gieh peie/giel tmr0ie int0ie iocie tmr0if int0if iocif 120 ipr1 actip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 129 pie1 actie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 126 pir1 actif adif rcif txif sspif ccp1if tmr2if tmr1if 123 pmd0 ?uartmd usbmd actmd ? tmr3md tmr2md tmr1md 64 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 280 spbrg1 eusart baud rate generator, low byte ? spbrgh1 eusart baud rate generator, high byte ? trisc trisc7 trisc6 ? ? ? trisc2 trisc1 trisc0 156 txreg1 eusart transmit register ? txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 279 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used for synchronous master transmission. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 293 pic18(l)f2x/45k50 17.5.1.6 synchronous master reception data is received at the rx/dt pin. the rx/dt pin output driver must be disabled by setting the corresponding tris bits when the eusart is configured for synchronous master receive operation. in synchronous mode, reception is enabled by setting either the single receive enable bit (sren of the rcstax register) or the continuous receive enable bit (cren of the rcstax register). when sren is set and cren is clear, only as many clock cycles are generated as there are data bits in a single character. the sren bit is automatically cleared at the completion of one character. when cren is set, clocks are continuously generated until cren is cleared. if cren is cleared in the middle of a character the ck clock stops immediately and the partial charac- ter is discarded. if sren and cren are both set, then sren is cleared at the completion of the first character and cren takes precedence. to initiate reception, set either sren or cren. data is sampled at the rx/dt pin on the trailing edge of the tx/ck clock pin and is shifted into the receive shift register (rsr). when a complete character is received into the rsr, the rcif bit is set and the character is automatically transferred to the two character receive fifo. the least significant eight bits of the top character in the receive fifo are available in rcregx. the rcif bit remains set as long as there are un-read characters in the receive fifo. 17.5.1.7 slave clock synchronous data transfers use a separate clock line, which is synchronous with the data. a device configured as a slave receives the clock on the tx/ck line. the tx/ ck pin output driver must be disabled by setting the associated tris bit when the device is configured for synchronous slave transmit or receive operation. serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. one data bit is transferred for each clock cycle. only as many clock cycles should be received as there are data bits. 17.5.1.8 receive overrun error the receive fifo buffer can hold two characters. an overrun error will be generated if a third character, in its entirety, is received before rcregx is read to access the fifo. when this happens the oerr bit of the rcstax register is set. previous data in the fifo will not be overwritten. the two characters in the fifo buffer can be read, however, no additional characters will be received until the error is cleared. the oerr bit can only be cleared by clearing the overrun condition. if the overrun error occurred when the sren bit is set and cren is clear then the error is cleared by reading rcregx. if the overrun occurred when the cren bit is set then the error condition is cleared by either clearing the cren bit of the rcstax register or by clearing the spen bit which resets the eusart. 17.5.1.9 receiving 9-bit characters the eusart supports 9-bit character reception. when the rx9 bit of the rcstax register is set the eusart will shift 9-bits into the rsr for each character received. the rx9d bit of the rcstax register is the ninth, and most significant, data bit of the top unread character in the receive fifo. when reading 9-bit data from the receive fifo buffer, the rx9d data bit must be read before reading the eight least significant bits from the rcregx. 17.5.1.10 synchronous master reception setup: 1. initialize the spbrghx, spbrgx register pair for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. set the rx/dt and tx/ck tris controls to ? 1 ?. 3. enable the synchronous master serial port by setting bits sync, spen and csrc. disable rx/dt and tx/ck output drivers by setting the corresponding tris bits. 4. ensure bits cren and sren are clear. 5. if using interrupts, set the gie/gieh and peie/ giel bits of the intcon register and set rcie. 6. if 9-bit reception is desired, set bit rx9. 7. start reception by setting the sren bit or for continuous reception, set the cren bit. 8. interrupt flag bit rcif will be set when reception of a character is complete. an interrupt will be generated if the enable bit rcie was set. 9. read the rcstax register to get the ninth bit (if enabled) and determine if any error occurred during reception. 10. read the 8-bit received data by reading the rcregx register. 11. if an overrun error occurs, clear the error by either clearing the cren bit of the rcstax register or by clearing the spen bit which resets the eusart. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 294 ? 2012 microchip technology inc. figure 17-12: synchronous reception (master mode, sren) cren bit rx/dt write to bit sren sren bit rcif bit (interrupt) read rcregx ? 0 ? bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 ? 0 ? note: timing diagram demonstrates sync master mode with bit sren = 1 and bit brgh = 0 . tx/ck pin tx/ck pin pin (sckp = 0 ) (sckp = 1 ) table 17-8: registers associated with synchronous master reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baudcon1 abdovf rcidl rxdtp txckp brg16 ? wue abden 281 intcon gie/gieh peie/giel tmr0ie int0ie iocie tmr0if int0if iocif 120 ipr1 actip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 129 pie1 actie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 126 pir1 actif adif rcif txif sspif ccp1if tmr2if tmr1if 123 pmd0 ?uartmd usbmd actmd ? tmr3md tmr2md tmr1md 64 rcreg1 eusart receive register ? rcsta1 spen rx9 sren cren adden ferr oerr rx9d 280 spbrg1 eusart baud rate generator, low byte ? spbrgh1 eusart baud rate generator, high byte ? txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 279 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used for synchronous master reception. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 295 pic18(l)f2x/45k50 17.5.2 synchronous slave mode the following bits are used to configure the eusart for synchronous slave operation: ? sync = 1 ? csrc = 0 ? sren = 0 (for transmit); sren = 1 (for receive) ? cren = 0 (for transmit); cren = 1 (for receive) ? spen = 1 setting the sync bit of the txstax register configures the device for synchronous operation. clearing the csrc bit of the txstax register configures the device as a slave. clearing the sren and cren bits of the rcstax register ensures that the device is in the transmit mode, otherwise the device will be configured to receive. setting the spen bit of the rcstax register enables the eusart. if the rx/dt or tx/ck pins are shared with an analog peripheral the analog i/o functions must be disabled by clearing the corresponding ansel bits. rx/dt and tx/ck pin output drivers must be disabled by setting the corresponding tris bits. 17.5.2.1 eusart synchronous slave transmit the operation of the synchronous master and slave modes are identical (see section 17.5.1.3 ?synchronous master transmission? ) , except in the case of the sleep mode. if two words are written to the txregx and then the sleep instruction is executed, the following will occur: 1. the first character will immediately transfer to the tsr register and transmit. 2. the second word will remain in txregx register. 3. the txif bit will not be set. 4. after the first character has been shifted out of tsr, the txregx register will transfer the second character to the tsr and the txif bit will now be set. 5. if the peie/giel and txie bits are set, the interrupt will wake the device from sleep and execute the next instruction. if the gie/gieh bit is also set, the program will call the interrupt service routine. 17.5.2.2 synchronous slave transmission setup: 1. set the sync and spen bits and clear the csrc bit. 2. set the rx/dt and tx/ck tris controls to ? 1 ?. 3. clear the cren and sren bits. 4. if using interrupts, ensure that the gie/gieh and peie/giel bits of the intcon register are set and set the txie bit. 5. if 9-bit transmission is desired, set the tx9 bit. 6. enable transmission by setting the txen bit. 7. if 9-bit transmission is selected, insert the most significant bit into the tx9d bit. 8. start transmission by writing the least significant eight bits to the txregx register. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 296 ? 2012 microchip technology inc. table 17-9: registers associated with synchronous slave transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baudcon1 abdovf rcidl rxdtp txckp brg16 ? wue abden 281 intcon gie/gieh peie/giel tmr0ie int0ie iocie tmr0if int0if iocif 120 ipr1 actip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 129 pie1 actie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 126 pir1 actif adif rcif txif ssp1f ccp1if tmr2if tmr1if 123 pmd0 ?uartmd usbmd actmd ? tmr3md tmr2md tmr1md 64 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 280 spbrg1 eusart baud rate generator, low byte ? spbrgh1 eusart baud rate generator, high byte ? trisc trisc7 trisc6 ? ? ? trisc2 trisc1 trisc0 156 txreg1 eusart transmit register ? txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 279 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used for synchronous slave transmission. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 297 pic18(l)f2x/45k50 17.5.2.3 eusart synchronous slave reception the operation of the synchronous master and slave modes is identical ( section 17.5.1.6 ?synchronous master reception? ), with the following exceptions: ? sleep ? cren bit is always set, therefore the receiver is never idle ? sren bit, which is a ?don?t care? in slave mode a character may be received while in sleep mode by setting the cren bit prior to entering sleep. once the word is received, the rsr register will transfer the data to the rcregx register. if the rcie enable bit is set, the interrupt generated will wake the device from sleep and execute the next instruction. if the gie/gieh bit is also set, the program will branch to the interrupt vector. 17.5.2.4 synchronous slave reception setup: 1. set the sync and spen bits and clear the csrc bit. 2. set the rx/dt and tx/ck tris controls to ? 1 ?. 3. if using interrupts, ensure that the gie/gieh and peie/giel bits of the intcon register are set and set the rcie bit. 4. if 9-bit reception is desired, set the rx9 bit. 5. set the cren bit to enable reception. 6. the rcif bit will be set when reception is complete. an interrupt will be generated if the rcie bit was set. 7. if 9-bit mode is enabled, retrieve the most significant bit from the rx9d bit of the rcstax register. 8. retrieve the eight least significant bits from the receive fifo by reading the rcregx register. 9. if an overrun error occurs, clear the error by either clearing the cren bit of the rcstax register or by clearing the spen bit which resets the eusart. table 17-10: registers associated with synchronous slave reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baudcon1 abdovf rcidl rxdtp txckp brg16 ? wue abden 281 intcon gie/gieh peie/giel tmr0ie int0ie iocie tmr0if int0if iocif 120 ipr1 actip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 129 pie1 actie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 126 pir1 actif adif rcif txif sspif ccp1if tmr2if tmr1if 123 pmd0 ?uartmd usbmd actmd ? tmr3md tmr2md tmr1md 64 rcreg1 eusart receive register ? rcsta1 spen rx9 sren cren adden ferr oerr rx9d 280 spbrg1 eusart baud rate generator, low byte ? spbrgh1 eusart baud rate generator, high byte ? txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 279 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used for synchronous slave reception. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 298 ? 2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 299 pic18(l)f2x/45k50 18.0 analog-to-digital converter (adc) module the analog-to-digital converter (adc) allows conversion of an analog input signal to a 10-bit binary representation of that signal. this device uses analog inputs, which are multiplexed into a single sample and hold circuit. the output of the sample and hold is connected to the input of the converter. the converter generates a 10-bit binary result via successive approximation and stores the conversion result into the adc result registers (adresl and adresh). the adc voltage reference is software selectable to either v dd or a voltage applied to the external reference pins. the adc can generate an interrupt upon completion of a conversion. this interrupt can be used to wake-up the device from sleep. figure 18-1 shows the block diagram of the adc. figure 18-1: adc block diagram note: additional adc channels an5-an7 and an20-an27 are only available on pic18(l)f45k50 devices. 11111 11110 11101 11100 11011 fvr buf2 dac ctmu temperature diode an27 (1) 00101 00100 an5 (1) an4 00011 00010 an3 an2 00001 00000 an1 an0 5 chs<4:0> 10-bit adc adcmd adon go/done 10 0 = left justify 1 = right justify adfm 10 adresh adresl 00 01 a vdd 10 11 fvr buf2 reserved v ref +/an3 2 pvcfg<1:0> 00 01 a vss 10 11 reserved reserved v ref -/an2 2 nvcfg<1:0> www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 300 ? 2012 microchip technology inc. 18.1 adc configuration when configuring and using the adc the following functions must be considered: ? port configuration ? channel selection ? adc voltage reference selection ? adc conversion clock source ? interrupt control ? results formatting 18.1.1 port configuration the anselx and trisx registers configure the a/d port pins. any port pin needed as an analog input should have its corresponding ansx bit set to disable the digital input buffer and trisx bit set to disable the digital output driver. if the trisx bit is cleared, the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the ansx bits and the tris bits. 18.1.2 channel selection the chs bits of the adcon0 register determine which channel is connected to the sample and hold circuit. when changing channels, a delay is required before starting the next conversion. refer to section 18.2 ?adc operation? for more information. 18.1.3 adc v oltage reference the pvcfg<1:0> and nvcfg<1:0> bits of the adcon1 register provide independent control of the positive and negative voltage references. the positive voltage reference can be: ?v dd ? the fixed voltage reference (fvr buf2) ? an external voltage source (v ref +) the negative voltage reference can be: ?v ss ? an external voltage source (v ref -) 18.1.4 selecting and configuring acquisition time the adcon2 register allows the user to select an acquisition time that occurs each time the go/done bit is set. acquisition time is set with the acqt<2:0> bits of the adcon2 register. acquisition delays cover a range of 2 to 20 t ad . when the go/done bit is set, the a/d module continues to sample the input for the selected acquisition time, then automatically begins a conversion. since the acquisition time is programmed, there is no need to wait for an acquisition time between selecting a channel and setting the go/done bit. manual acquisition is selected when acqt<2:0> = 000 . when the go/done bit is set, sampling is stopped and a conversion begins. the user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the go/done bit. this option is also the default reset state of the acqt<2:0> bits and is compatible with devices that do not offer programmable acquisition times. in either case, when the conversion is completed, the go/done bit is cleared, the adif flag is set and the a/d begins sampling the currently selected channel again. when an acquisition time is programmed, there is no indication of when the acquisition time ends and the conversion begins. note 1: when reading the port register, all pins with their corresponding ansx bit set read as cleared (a low level). however, analog conversion of pins configured as digital inputs (ansx bit cleared and trisx bit set) will be accurately converted. 2: analog levels on any pin with the corre- sponding ansx bit cleared may cause the digital input buffer to consume current out of the device?s specification limits. 3: the pbaden bit in configuration register 3h configures portb pins to reset as analog or digital pins by controlling how the bits in anselb are reset. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 301 pic18(l)f2x/45k50 18.1.5 conversion clock the source of the conversion clock is software selectable via the adcs bits of the adcon2 register. there are seven possible clock options: ?f osc /2 ?f osc /4 ?f osc /8 ?f osc /16 ?f osc /32 ?f osc /64 ?f rc (dedicated internal oscillator) the time to complete one bit conversion is defined as t ad . one full 10-bit conversion requires 11 t ad periods as shown in figure 18-3 . for correct conversion, the appropriate t ad specification must be met. see a/d conversion requirements in table 29-23 for more information. ta b l e 1 8 - 1 gives examples of appropriate adc clock selections. 18.1.6 interrupts the adc module allows for the ability to generate an interrupt upon completion of an analog-to-digital conversion. the adc interrupt enable is the adie bit in the pie1 register and the interrupt priority is the adip bit in the ipr1 register. the adc interrupt flag is the adif bit in the pir1 register. the adif bit must be cleared by software. this interrupt can be generated while the device is operating or while in sleep. if the device is in sleep, the interrupt will wake-up the device. upon waking from sleep, the next instruction following the sleep instruction is always executed. if the user is attempting to wake-up from sleep and resume in-line code execution, the global interrupt must be disabled. if the global interrupt is enabled, execution will switch to the interrupt service routine. note: unless using the f rc , any changes in the system clock frequency will change the adc clock frequency, which may adversely affect the adc result. note: the adif bit is set at the completion of every conversion, regardless of whether or not the adc interrupt is enabled. table 18-1: adc clock period (t ad ) vs. device operating frequencies ad clock period (t ad ) device frequency (f osc ) adc clock source adcs<2:0> 48 mhz 16 mhz 4 mhz 1 mhz f osc /2 000 41.17 ns (2) 125 ns (2) 500 ns (2) 2.0 ? s f osc /4 100 83.3 ns (2) 250 ns (2) 1.0 ? s 4.0 ? s (3) f osc /8 001 166.7 ns (2) 500 ns (2) 2.0 ? s 8.0 ? s (3) f osc /16 101 333.3 ns (2) 1.0 ? s 4.0 ? s (3) 16.0 ? s (3) f osc /32 010 666.7 ns (2) 2.0 ? s 8.0 ? s (3) 32.0 ? s (3) f osc /64 110 1.3 ? s 4.0 ? s (3) 16.0 ? s (3) 64.0 ? s (3) f rc 011 1-4 ? s (1,4) 1-4 ? s (1,4) 1-4 ? s (1,4) 1-4 ? s (1,4) legend: shaded cells are outside the recommended range. note 1: the f rc source has a typical t ad time of 1.7 ? s. 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: when the device frequency is greater than 1 mhz, the f rc clock source is only recommended if the conversion will be performed during sleep. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 302 ? 2012 microchip technology inc. 18.1.7 result formatting the 10-bit a/d conversion result can be supplied in two formats, left justified or right justified. the adfm bit of the adcon2 register controls the output format. figure 18-2 shows the two output formats. figure 18-2: 10-bit a/d conv ersion result format adresh adresl (adfm = 0 )msb lsb bit 7 bit 0 bit 7 bit 0 10-bit a/d result unimplemented: read as ? 0 ? (adfm = 1 ) msb lsb bit 7 bit 0 bit 7 bit 0 unimplemented: read as ? 0 ? 10-bit a/d result www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 303 pic18(l)f2x/45k50 18.2 adc operation 18.2.1 starting a conversion to enable the adc module, the adon bit of the adcon0 register must be set to a ? 1 ?. setting the go/ done bit of the adcon0 register to a ? 1 ? will, depend- ing on the acqt bits of the adcon2 register, either immediately start the analog-to-digital conversion or start an acquisition delay followed by the analog-to- digital conversion. figure 18-3 shows the operation of the a/d converter after the go bit has been set and the acqt<2:0> bits are cleared. a conversion is started after the following instruction to allow entry into sleep mode before the conversion begins. figure 18-4 shows the operation of the a/d converter after the go bit has been set and the acqt<2:0> bits are set to ? 010 ? which selects a 4 t ad acquisition time before the conversion starts. figure 18-3: a/d conversion t ad cycles (a cqt <2:0> = 000 , t acq = 0 ) figure 18-4: a/d conversion t ad cycles (a cqt <2:0> = 010 , t acq = 4 t ad ) note: the go/done bit should not be set in the same instruction that turns on the adc. refer to section 18.2.10 ?a/d conver- sion procedure? . t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 11 set go bit holding capacitor is disconnected from analog input (typically 100 ns) t ad 9 t ad 10 t cy - t ad adresh:adresl is loaded, go bit is cleared, adif bit is set, holding capacitor is connected to analog input. conversion starts b0 b9 b6 b5 b4 b3 b2 b1 b8 b7 on the following cycle: 2 t ad discharge 1 2 3 4 5 6 7 8 11 set go bit (holding capacitor is disconnected from analog input) 9 10 conversion starts 1 2 3 4 (holding capacitor continues acquiring input) t acqt cycles t ad cycles automatic acquisition time b0 b9 b6 b5 b4 b3 b2 b1 b8 b7 adresh:adresl is loaded, go bit is cleared, adif bit is set, holding capacitor is connected to analog input. on the following cycle: 2 t ad discharge www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 304 ? 2012 microchip technology inc. 18.2.2 completion of a conversion when the conversion is complete, the adc module will: ? clear the go/done bit ? set the adif flag bit ? update the adresh:adresl registers with new conversion result 18.2.3 discharge the discharge phase is used to initialize the value of the capacitor array. the array is discharged after every sample. this feature helps to optimize the unity-gain amplifier, as the circuit always needs to charge the capacitor array, rather than charge/discharge based on previous measure values. 18.2.4 terminating a conversion if a conversion must be terminated before completion, the go/done bit can be cleared by software. the adresh:adresl registers will not be updated with the partially complete analog-to-digital conversion sample. instead, the adresh:adresl register pair will retain the value of the previous conversion. 18.2.5 delay between conversions after the a/d conversion is completed or aborted, a 2t ad wait is required before the next acquisition can be started. after this wait, the currently selected channel is reconnected to the charge holding capacitor commencing the next acquisition. 18.2.6 adc operation in power- managed modes the selection of the automatic acquisition time and a/d conversion clock is determined in part by the clock source and frequency while in a power-managed mode. if the a/d is expected to operate while the device is in a power-managed mode, the acqt<2:0> and adcs<2:0> bits in adcon2 should be updated in accordance with the clock source to be used in that mode. after entering the mode, an a/d acquisition or conversion may be started. once started, the device should continue to be clocked by the same clock source until the conversion has been completed. if desired, the device may be placed into the corresponding idle mode during the conversion. if the device clock frequency is less than 1 mhz, the a/d f rc clock source should be selected. 18.2.7 adc operation during sleep the adc module can operate during sleep. this requires the adc clock source to be set to the f rc option. when the f rc clock source is selected, the adc waits one additional instruction before starting the conversion. this allows the sleep instruction to be executed, which can reduce system noise during the conversion. if the adc interrupt is enabled, the device will wake-up from sleep when the conversion completes. if the adc interrupt is disabled, the adc module is turned off after the conversion completes, although the adon bit remains set. when the adc clock source is something other than f rc , a sleep instruction causes the present conversion to be aborted and the adc module is turned off, although the adon bit remains set. 18.2.8 special event trigger two special event triggers are available to start an a/d conversion: ctmu and ccp2. the special event trigger source is selected using the trigsel bit in adcon1. when trigsel = 0 , the ccp2 module is selected as the special event trigger source. to enable the special event trigger in the ccp module, set ccp2m<3:0> = 1011 , in the ccp2con register. when trigsel = 1 , the ctmu module is selected. the ctmu module requires that the cttrig bit in ctmuconh is set to enable the special event trigger. in addition to the trigsel bit, the following steps are required to start an a/d conversion: ? the a/d module must be enabled (adon = 1 ) ? the appropriate analog input channel selected ? the minimum acquisition period set one of these ways: - timing provided by the user - selection made of an appropriate t acq time with these conditions met, the trigger sets the go/done bit and the a/d acquisition starts. if the a/d module is not enabled (adon = 0 ), the module ignores the special event trigger. 18.2.9 peripheral module disable when a peripheral module is not used or inactive, the module can be disabled by setting the module disable bit in the pmd registers. this will reduce power consumption to an absolute minimum. setting the pmd bits holds the module in reset and disconnects the module?s clock source. the module disable bit for the adc module is adcmd in the pmd1 register. see section 4.0 ?power-managed modes? for more information. note: a device reset forces all registers to their reset state. thus, the adc module is turned off and any pending conversion is terminated. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 305 pic18(l)f2x/45k50 18.2.10 a/d conversion procedure this is an example procedure for using the adc to perform an analog-to-digital conversion: 1. configure port: ? disable pin output driver (see tris register) ? configure pin as analog 2. configure the adc module: ? select adc conversion clock ? configure voltage reference ? select adc input channel ? select result format ? select acquisition delay ? turn on adc module 3. configure adc interrupt (optional): ? clear adc interrupt flag ? enable adc interrupt ? enable peripheral interrupt ? enable global interrupt (1) 4. wait the required acquisition time (2) . 5. start conversion by setting the go/done bit. 6. wait for adc conversion to complete by one of the following: ? polling the go/done bit ? waiting for the adc interrupt (interrupts enabled) 7. read adc result 8. clear the adc interrupt flag (required if interrupt is enabled). example 18-1: a/d conversion note 1: the global interrupt can be disabled if the user is attempting to wake-up from sleep and resume in-line code execution. 2: software delay required if acqt bits are set to zero delay. see section 18.4 ?a/d acquisition requirements? . ;this code block configures the adc ;for polling, vdd and vss as reference, frc clock and an0 input. ; ;conversion start & polling for completion ; are included. ; movlw b?10101111? ;right justify, frc, movwf adcon2 ; & 12 tad acq time movlw b?00000000? ;adc ref = vdd,vss movwf adcon1 ; bsf trisa,0 ;set ra0 to input bsf ansel,0 ;set ra0 to analog movlw b?00000001? ;an0, adc on movwf adcon0 ; bsf adcon0,go ;start conversion adcpoll: btfsc adcon0,go ;is conversion done? bra adcpoll ;no, test again ; result is complete - store 2 msbits in ; resulthi and 8 lsbits in resultlo movff adresh,resulthi movff adresl,resultlo www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 306 ? 2012 microchip technology inc. 18.3 register definitions: adc control note: analog pin control is determined by the anselx registers (see register 11-2 ) register 18-1: adcon0: a/ d control register 0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? chs<4:0> go/done adon bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6-2 chs<4:0>: analog channel select bits 00000 = an0 00001 = an1 00010 = an2 00011 = an3 00100 = an4 00101 = an5 (1) 00110 = an6 (1) 00111 = an7 (1) 01000 = an8 01001 = an9 01010 = an10 01011 = an11 01100 = an12 01101 = an13 01110 = an14 01111 = an15 10000 = an16 10001 = an17 10010 = an18 10011 = an19 10100 = an20 (1) 10101 = an21 (1) 10110 = an22 (1) 10111 = an23 (1) 11000 = an24 (1) 11001 = an25 (1) 11010 = an26 (1) 11011 = an27 (1) 11100 = temperature diode 11101 = ctmu 11110 = dac 11111 = fvr buf2 (1.024v/2.048v/4.096v fixed voltage reference) (2) bit 1 go/done : a/d conversion status bit 1 = a/d conversion cycle in progress. setti ng this bit starts an a/d conversion cycle. this bit is automatically cleared by hardware when the a/d conversion has completed. 0 = a/d conversion completed/not in progress bit 0 adon: adc enable bit 1 = adc is enabled 0 = adc is disabled and consumes no operating current note 1: available on pic18(l)f45k50 devices only. 2: allow greater than 15 ? s acquisition time when measuring the fixed voltage reference. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 307 pic18(l)f2x/45k50 register 18-2: adcon1: a/ d control register 1 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 trigsel ? ? ? pvcfg<1:0> nvcfg<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 trigsel : special trigger select bit 1 = selects the special trigger from ctmu 0 = selects the special trigger from ccp2 bit 6-4 unimplemented: read as ? 0 ? bit 3-2 pvcfg<1:0>: positive voltage reference configuration bits 00 = a/d v ref + connected to internal signal, av dd 01 = a/d v ref + connected to external pin, v ref + 10 = a/d v ref + connected to internal signal, fvr buf2 11 = reserved bit 1-0 nvcfg<1:0>: negative voltage reference configuration bits 00 = a/d v ref - connected to internal signal, av ss 01 = a/d v ref - connected to external pin, v ref - 10 = reserved 11 = reserved www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 308 ? 2012 microchip technology inc. register 18-3: adcon2: a/ d control register 2 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adfm ? acqt<2:0> adcs<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 adfm: a/d conversion result format select bit 1 = right justified 0 = left justified bit 6 unimplemented: read as ? 0 ? bit 5-3 acqt<2:0>: a/d acquisition time select bits. acquisition time is the duration that the a/d charge holding capacitor remains connected to a/d channel from the instant the go/done bit is set until conversions begins. 000 = 0 (1) 001 = 2 t ad 010 = 4 t ad 011 = 6 t ad 100 = 8 t ad 101 = 12 t ad 110 = 16 t ad 111 = 20 t ad bit 2-0 adcs<2:0>: a/d conversion clock select bits 000 = f osc /2 001 = f osc /8 010 = f osc /32 011 = f rc (1) (clock derived from a dedicated internal oscillator = 600 khz nominal) 100 = f osc /4 101 = f osc /16 110 = f osc /64 111 = f rc (1) (clock derived from a dedicated internal oscillator = 600 khz nominal) note 1: when the a/d clock source is selected as f rc then the start of conversion is delayed by one instruction cycle after the go/done bit is set to allow the sleep instruction to be executed. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 309 pic18(l)f2x/45k50 register 18-4: adresh: adc result register high (adresh) adfm = 0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x adres<9:2> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 adres<9:2> : adc result register bits upper eight bits of 10-bit conversion result register 18-5: adresl: adc result register low (adresl) adfm = 0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x adres<1:0> r r r r r r bit 7 bit 0 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 adres<1:0> : adc result register bits lower two bits of 10-bit conversion result bit 5-0 reserved : do not use. register 18-6: adresh: adc result register high (adresh) adfm = 1 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r r r r r r adres<9:8> bit 7 bit 0 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-2 reserved : do not use. bit 1-0 adres<9:8> : adc result register bits upper two bits of 10-bit conversion result register 18-7: adresl: adc result register low (adresl) adfm = 1 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x adres<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 adres<7:0> : adc result register bits lower eight bits of 10-bit conversion result www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 310 ? 2012 microchip technology inc. 18.4 a/d acquisition requirements for the adc to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 18-5 . the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ), see figure 18-5 . the maximum recommended impedance for analog sources is 10 k ? . as the source impedance is decreased, the acquisition time may be decreased. after the analog input channel is selected (or changed), an a/d acquisition must be done before the conversion can be started. to calculate the minimum acquisition time, equation 18-1 may be used. this equation assumes that 1/2 lsb error is used (1024 steps for the adc). the 1/2 lsb error is the maximum error allowed for the adc to meet its specified resolution. equation 18-1: acquisition time example t acq amplifier settling time hold capacitor charging time temperature coefficient ++ = t amp t c t coff ++ = 5 s t c temperature - 25c ?? 0.05s/c ?? ?? ++ = t c c hold r ic r ss r s ++ ?? ln(1/2047) ? = 13.5pf 1k ? 700 ? 10k ? ++ ?? ? ln(0.0004885) = 1.20 = s t acq 5 s 1.20s 50c- 25c ?? 0.05 ? s/ c ?? ?? ++ = 7.45 s = v applied 1e tc ? rc --------- ? ?? ?? ?? v applied 1 1 2047 ----------- - ? ?? ?? = v applied 1 1 2047 ----------- - ? ?? ?? v chold = v applied 1e t c ? rc --------- - ? ?? ?? ?? v chold = ;[1] v chold charged to within 1/2 lsb ;[2] v chold charge response to v applied ;combining [1] and [2] the value for t c can be approximated with the following equations: solving for t c : therefore: temperature 50c and external impedance of 10k ? 3.0 v v dd = assumptions: note 1: the reference voltage (v ref ) has no effect on the equation, since it cancels itself out. 2: the charge holding capacitor (c hold ) is discharged after each conversion. 3: the maximum recommended impedance for analog sources is 10 k ? . this is required to meet the pin leakage specification. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 311 pic18(l)f2x/45k50 figure 18-5: analog input model figure 18-6: adc transfer function c pin va rs anx 5 pf v dd i leakage (1) r ic ? 1k sampling switch ss rss c hold = 13.5 pf v ss /v ref - 2.5v rss (k ? ) 2.0v 1.5v .1 1 10 v dd legend: c pin i leakage r ic ss c hold = input capacitance = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance various junctions discharge switch 3.0v 3.5v 100 note 1: see section 29.0 ?electrical characteristics? . 3ffh 3feh adc output code 3fdh 3fch 004h 003h 002h 001h 000h full-scale 3fbh 1/2 lsb ideal v ss /v ref - zero-scale transition v dd /v ref + transition 1/2 lsb ideal full-scale range analog input voltage www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 312 ? 2012 microchip technology inc. table 18-3: configuration registers associated with the adc module table 18-2: registers associ ated with a/d operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page adcon0 ? chs<4:0> go/d one adon 306 adcon1 trigsel ? ? ? pvcfg<1:0> nvcfg<1:0> 307 adcon2 adfm ? acqt<2:0> adcs<2:0> 308 adresh a/d result, high byte 309 adresl a/d result, low byte 309 ansela ? ?ansa5 ? ansa3 ansa2 ansa1 ansa0 154 anselb ? ? ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 155 anselc ansc7 ansc6 ? ? ? ansc2 ? ? 155 anseld (1) ansd7 ansd6 ansd5 ansd4 ansd3 ansd2 ansd1 ansd0 155 ansele (1) ? ? ? ? ? anse2 anse1 anse0 156 ctmuconh ctmuen ? ctmusidl tgen edgen edgseqen idissen cttrig 335 intcon gie/gieh peie/giel tmr0ie int0ie iocie tmr0if int0if iocif 120 ipr1 actip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 129 pie1 actie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 126 pir1 actif adif rcif txif sspif ccp1if tmr2if tmr1if 123 pmd1 ? msspmd ctmumd cmp2md cmp1md adcmd ccp2md ccp1md 65 trisa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 156 trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 156 trisc trisc7 trisc6 ? ? ?trisc2 trisc1 trisc0 156 trisd (1) trisd7 trisd6 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 156 trise wpue3 ? ? ? ? trise2 (1) trise1 (1) trise0 (1) 156 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used by this module. note 1: available on pic18(l)f45k50 devices. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page config3h mclre sdomx ? t3cmx ? ? pbaden ccp2mx 391 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used by the adc module. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 313 pic18(l)f2x/45k50 19.0 comparator module comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. the comparators are very useful mixed signal building blocks because they provide analog functionality independent of the program execution. the analog comparator module includes the following features: ? independent comparator control ? programmable input selection ? comparator output is available internally/externally ? programmable output polarity ? interrupt-on-change ? wake-up from sleep ? programmable speed/power optimization ?pwm shutdown ? programmable and fixed voltage reference 19.1 comparator overview a single comparator is shown in figure 19-1 along with the relationship between the analog input levels and the digital output. when the analog voltage at v in + is less than the analog voltage at v in -, the output of the comparator is a digital low level. when the analog voltage at v in + is greater than the analog voltage at v in -, the output of the comparator is a digital high level. figure 19-1: single comparator ? + v in + v in - output output v in + v in - note: the black areas of the output of the comparator represents the uncertainty due to input offsets and response time. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 314 ? 2012 microchip technology inc. figure 19-2: comparator c1/c2 simplified block diagram note 1: when c1on = 0 , the c1 comparator will produce a ? 0 ? output to the xor gate. 2: q1 and q3 are phases of the four-phase system clock (f osc ). 3: q1 is held high during sleep mode. 4: synchronized comparator output should not be used to gate timer1 in conjunction with synchronized t1cki. cx cxpol to pwm logic 0 1 2 3 cxon (1) cxch<1:0> 2 0 1 cxr cm2con1 (mcxout) to interrupts cxv in - cxv in + c12in0- c12in1- c12in2- c12in3- cxin+ dq en q1 (2),(3) dq en cl read or write reset + - 0 1 dac output c x rsel fvr buf1 cxsp c x v ref cxoe c xout timer1 clock dq sync_c xout to cmxcon0 (cxout) (cxif) of cmxcon0 q3 (2) 0 1 cxsync async_c x out tris bit - to sr latch - to txg mux (4) www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 315 pic18(l)f2x/45k50 19.2 comparator control each comparator has a separate control and configuration register: cm1con0 for comparator c1 and cm2con0 for comparator c2. in addition, comparator c2 has a second control register, cm2con1, for controlling the interaction with timer1 and simultaneous reading of both comparator outputs. the cm1con0 and cm2con0 registers (see register 19-1 ) contain the control and status bits for the following: ? enable ? input selection ? reference selection ?output selection ? output polarity ? speed selection 19.2.1 comparator enable setting the cxon bit of the cmxcon0 register enables the comparator for operation. clearing the cxon bit disables the comparator resulting in minimum current consumption. 19.2.2 comparator input selection the cxch<1:0> bits of the cmxcon0 register direct one of four analog input pins to the comparator inverting input. 19.2.3 comparator reference selection setting the cxr bit of the cmxcon0 register directs an internal voltage reference or an analog input pin to the non-inverting input of the comparator. see section 22.0 ?fixed voltage reference (fvr)? for more information on the internal voltage reference module. 19.2.4 comparator output selection the output of the comparator can be monitored by reading either the cxout bit of the cmxcon0 register or the mcxout bit of the cm2con1 register. in order to make the output available for an external connection, the following conditions must be true: ? cxoe bit of the cmxcon0 register must be set ? corresponding tris bit must be cleared ? cxon bit of the cmxcon0 register must be set 19.2.5 comparator output polarity inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. the polarity of the comparator output can be inverted by setting the cxpol bit of the cmxcon0 register. clearing the cxpol bit results in a non-inverted output. table 19-1 shows the output state versus input conditions, including polarity control. 19.2.6 comparator speed selection the trade-off between speed or power can be optimized during program execution with the cxsp control bit. the default state for this bit is ? 1 ? which selects the normal speed mode. device power consumption can be optimized at the cost of slower comparator propagation delay by clearing the cxsp bit to ? 0 ?. 19.3 comparator response time the comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. this period is referred to as the response time. the response time of the comparator differs from the settling time of the voltage reference. therefore, both of these times must be considered when determining the total response time to a comparator input change. see the comparator and voltage reference specifications in section 29.0 ?electrical characteristics? for more details. note: to use cxin+ and c12inx- pins as analog inputs, the appropriate bits must be set in the ansel register and the corresponding tris bits must also be set to disable the output drivers. note 1: the cxoe bit overrides the port data latch. setting the cxon has no impact on the port override. 2: the internal output of the comparator is latched with each instruction cycle. unless otherwise specified, external outputs are not latched. table 19-1: comparator output state vs. input conditions input condition cxpol cxout cxv in - > cxv in + 00 cxv in - < cxv in + 01 cxv in - > cxv in + 11 cxv in - < cxv in + 10 www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 316 ? 2012 microchip technology inc. 19.4 comparator interrupt operation the comparator interrupt flag will be set whenever there is a change in the output value of the comparator. changes are recognized by means of a mismatch circuit which consists of two latches and an exclusive- or gate (see figure 19-2 ). the first latch is updated with the comparator output value, when the cmxcon0 register is read or written. the value is latched on the third cycle of the system clock, also known as q3. this first latch retains the comparator value until another read or write of the cmxcon0 register occurs or a reset takes place. the second latch is updated with the comparator output value on every first cycle of the system clock, also known as q1. when the output value of the comparator changes, the second latch is updated and the output values of both latches no longer match one another, resulting in a mismatch condition. the latch outputs are fed directly into the inputs of an exclusive-or gate. this mismatch condition is detected by the exclusive-or gate and sent to the interrupt circuitry. the mismatch condition will persist until the first latch value is updated by performing a read of the cmxcon0 register or the comparator output returns to the previous state. when the mismatch condition occurs, the comparator interrupt flag is set. the interrupt flag is triggered by the edge of the changing value coming from the exclusive- or gate. this means that the interrupt flag can be reset once it is triggered without the additional step of read- ing or writing the cmxcon0 register to clear the mis- match latches. when the mismatch registers are cleared, an interrupt will occur upon the comparator?s return to the previous state, otherwise no interrupt will be generated. software will need to maintain information about the status of the comparator output, as read from the cmxcon0 register, or cm2con1 register, to determine the actual change that has occurred. see figures 19-3 and 19-4 . the cxif bit of the pir2 register is the comparator interrupt flag. this bit must be reset by software by clearing it to ? 0 ?. since it is also possible to write a ? 1 ? to this register, an interrupt can be generated. in mid-range compatibility mode the cxie bit of the pie2 register and the peie/giel and gie/gieh bits of the intcon register must all be set to enable compar- ator interrupts. if any of these bits are cleared, the inter- rupt is not enabled, although the cxif bit of the pir2 register will still be set if an interrupt condition occurs. 19.4.1 presetting the mismatch latches the comparator mismatch latches can be preset to the desired state before the comparators are enabled. when the comparator is off the cxpol bit controls the cxout level. set the cxpol bit to the desired cxout non-interrupt level while the cxon bit is cleared. then, configure the desired cxpol level in the same instruc- tion that the cxon bit is set. since all register writes are performed as a read-modify-write, the mismatch latches will be cleared during the instruction read phase and the actual configuration of the cxon and cxpol bits will be occur in the final write phase. figure 19-3: comparator interrupt timing w/o cmxcon0 read figure 19-4: comparator interrupt timing with cmxcon0 read note 1: a write operation to the cmxcon0 register will also clear the mismatch condition because all writes include a read operation at the beginning of the write cycle. 2: comparator interrupts will operate correctly regardless of the state of cxoe. note 1: if a change in the cmxcon0 register (cxout) should occur when a read oper- ation is being executed (start of the q2 cycle), then the cxif interrupt flag of the pir2 register may not get set. 2: when either comparator is first enabled, bias circuitry in the comparator module may cause an invalid output from the comparator until the bias circuitry is stable. allow about 1 ? s for bias settling then clear the mismatch condition and interrupt flags before enabling comparator interrupts. q1 q3 cxin+ cxin set cxif (edge) cxif t rt reset by software q1 q3 cxin+ cxout set cxif (edge) cxif t rt reset by software cleared by cmxcon0 read www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 317 pic18(l)f2x/45k50 19.5 operation during sleep the comparator, if enabled before entering sleep mode, remains active during sleep. the additional current consumed by the comparator is shown separately in section 29.0 ?electrical characteristics? . if the comparator is not used to wake the device, power consumption can be minimized while in sleep mode by turning off the comparator. each comparator is turned off by clearing the cxon bit of the cmxcon0 register. a change to the comparator output can wake-up the device from sleep. to enable the comparator to wake the device from sleep, the cxie bit of the pie2 register and the peie/giel bit of the intcon register must be set. the instruction following the sleep instruction always executes following a wake from sleep. if the gie/gieh bit of the intcon register is also set, the device will then execute the interrupt service routine. 19.6 effects of a reset a device reset forces the cmxcon0 and cm2con1 registers to their reset states. this forces both comparators and the voltage references to their off states.comparator control registers. 19.7 analog input connection considerations a simplified circuit for an analog input is shown in figure 19-5 . since the analog input pins share their connection with a digital input, they have reverse biased esd protection diodes to v dd and v ss . the analog input, therefore, must be between v ss and v dd . if the input voltage deviates from this range by more than 0.6v in either direction, one of the diodes is forward biased and a latch-up may occur. a maximum source impedance of 10 k ? is recommended for the analog sources. also, any external component connected to an analog input pin, such as a capacitor or a zener diode, should have very little leakage current to minimize inaccuracies introduced. figure 19-5: analog input model note 1: when reading a port register, all pins configured as analog inputs will read as a ? 0 ?. pins configured as digital inputs will convert as an analog input, according to the input specification. 2: analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified. v a rs < 10k c pin 5 pf v dd v t ? 0.6v v t ? 0.6v r ic i leakage (1) vss a in legend: c pin = input capacitance i leakage = leakage current at the pin due to various junctions r ic = interconnect resistance r s = source impedance v a = analog voltage v t = threshold voltage note 1: see section 29.0 ?electrical characteristics? . to comparator www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 318 ? 2012 microchip technology inc. 19.8 additional comparator features there are four additional comparator features: ? simultaneous read of comparator outputs ? internal reference selection ? hysteresis selection ? output synchronization 19.8.1 simultaneous comparator output read the mc1out and mc2out bits of the cm2con1 register are mirror copies of both comparator outputs. the ability to read both outputs simultaneously from a single register eliminates the timing skew of reading separate registers. 19.8.2 internal reference selection there are two internal voltage references available to the non-inverting input of each comparator. one of these is the fixed voltage reference (fvr) and the other is the variable digital-to-analog converter (dac). the cxrsel bit of the cm2con1 register determines which of these references is routed to the comparator voltage reference output (c x v ref ). further routing to the comparator is accomplished by the cxr bit of the cmxcon0 register. see section 22.0 ?fixed voltage reference (fvr)? and figure 19-2 for more detail. 19.8.3 synchronizing comparator output to timer1 the comparator cx output can be synchronized with timer1 by setting the cxsync bit of the cm2con1 register. when enabled, the cx output is latched on the falling edge of the timer1 source clock. to prevent a race condition when gating timer1 clock with the comparator output, timer1 increments on the rising edge of its clock source, and the falling edge latches the comparator output. see the comparator block diagram ( figure 19-2 ) and the timer1 block diagram ( figure 13-1 ) for more information. note 1: obtaining the status of c1out or c2out by reading cm2con1 does not affect the comparator interrupt mismatch registers. note 1: the comparator synchronized output should not be used to gate the external timer1 clock when the timer1 synchronizer is enabled. 2: the timer1 prescale should be set to 1:1 when synchronizing the comparator output as unexpected results may occur with other prescale values. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 319 pic18(l)f2x/45k50 19.9 register definitions: comparator control register 19-1: cmxcon0: comp arator x control register r/w-0 r-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-0 r/w-0 cxon cxout cxoe cxpol cxsp cxr cxch<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 cxon: comparator cx enable bit 1 = comparator cx is enabled 0 = comparator cx is disabled bit 6 cxout: comparator cx output bit if cxpol = 1 (inverted polarity): cxout = 0 when cxv in + > cxv in - cxout = 1 when cxv in + < cxv in - if cxpol = 0 (non-inverted polarity): cxout = 1 when cxv in + > cxv in - cxout = 0 when cxv in + < cxv in - bit 5 cxoe: comparator cx output enable bit 1 = cxout is present on the cxout pin (1) 0 = cxout is internal only bit 4 cxpol: comparator cx output polarity select bit 1 = cxout logic is inverted 0 = cxout logic is not inverted bit 3 cxsp: comparator cx speed/power select bit 1 = cx operates in normal power, higher speed mode 0 = cx operates in low-power, low-speed mode bit 2 cxr: comparator cx reference select bit (non-inverting input) 1 = cxv in + connects to c x v ref output 0 = cxv in + connects to c12in+ pin bit 1-0 cxch<1:0>: comparator cx channel select bit 00 = c12in0- pin of cx connects to cxv in - 01 = c12in1- pin of cx connects to c x v in - 10 = c12in2- pin of cx connects to cxv in - 11 = c12in3- pin of cx connects to cxv in - note 1: comparator output requires the following three conditions: cxoe = 1 , cxon = 1 and corresponding port tris bit = 0 . www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 320 ? 2012 microchip technology inc. register 19-2: cm2con1: compa rator 1 and 2 control register r-0 r-0 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 mc1out mc2out c1rsel c2rsel ? ? c1sync c2sync bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 mc1out: mirror copy of c1out bit bit 6 mc2out: mirror copy of c2out bit bit 5 c1rsel: comparator c1 reference select bit 1 = fvr buf1 routed to c1v ref input 0 = dac routed to c1v ref input bit 4 c2rsel: comparator c2 reference select bit 1 = fvr buf1 routed to c2v ref input 0 = dac routed to c2v ref input bit 3-2 reserved: maintain these bits clear bit 1 c1sync: c1 output synchronous mode bit 1 = c1 output is synchronized to rising edge of tmr1 clock (t1clk) 0 = c1 output is asynchronous bit 0 c2sync: c2 output synchronous mode bit 1 = c2 output is synchronized to rising edge of tmr1 clock (t1clk) 0 = c2 output is asynchronous www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 321 pic18(l)f2x/45k50 table 19-2: registers associated with comparator module name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ansela ? ? ansa5 ? ansa3 ansa2 ansa1 ansa0 154 anselb ? ? ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 155 cm2con1 mc1out mc2out c1rsel c2rsel c1hys c2hys c1sync c2sync 320 cm1con0 c1on c1out c1oe c1pol c1sp c1r c1ch<1:0> 319 cm2con0 c2on c2out c2oe c2pol c2sp c2r c2ch<1:0> 319 vrefcon1 dacen daclps dacoe ? dacpss<1:0> ? dacnss 349 vrefcon2 ? ? ? dacr<4:0> 350 vrefcon0 fvren fvrst fvrs<1:0> ? ? ? ? 346 intcon gie/gieh peie/giel tmr0ie int0ie iocie tmr0if int0if iocif 120 ipr2 oscfip c1ip c2ip eeip bclip hlvdip tmr3ip ccp2ip 130 pie2 oscfie c1ie c2ie eeie bclie hlvdie tmr3ie ccp2ie 127 pir2 oscfif c1if c2if eeif bclif hlvdif tmr3if ccp2if 124 pmd1 ? msspmd ctmumd cmp2md cmp1md adcmd ccp2md ccp1md 65 trisa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 156 trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 156 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used by the comparator module. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 322 ? 2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 323 pic18(l)f2x/45k50 20.0 charge time measurement unit (ctmu) the charge time measurement unit (ctmu) is a flexible analog module that provides accurate differential time measurement between pulse sources, as well as asynchronous pulse generation. by working with other on-chip analog modules, the ctmu can be used to precisely measure time, measure capacitance, measure relative changes in capacitance or generate output pulses with a specific time delay. the ctmu is ideal for interfacing with capacitive-based sensors. the module includes the following key features: ? up to 28 (1) channels available for capacitive or time measurement input ? on-chip precision current source ? four-edge input trigger sources ? polarity control for each edge source ? control of edge sequence ? control of response to edges ? high precision time measurement ? time delay of external or internal signal asynchronous to system clock ? accurate current source suitable for capacitive measurement the ctmu works in conjunction with the a/d converter to provide up to 28 (1) channels for time or charge measurement, depending on the specific device and the number of a/d channels available. when config- ured for time delay, the ctmu is connected to the c12in1- input of comparator 2. the level-sensitive input edge sources can be selected from four sources: two external input pins (cted1/cted2) or the eccp1/ ccp2 special event triggers. figure 20-1 provides a block diagram of the ctmu. figure 20-1: ctmu block diagram note 1: pic18(l)f2xk50 devices have up to 17 channels available. cted1 cted2 current source edge control logic ctmuconh/ctmuconl pulse generator ccp2 eccp1 current control itrim<5:0> irng<1:0> ctmuicon ctmu control logic edgen edgseqen edg1selx edg1pol edg2selx edg2pol edg1stat edg2stat tgen idissen ctpls comparator 2 output cttrig comparator c1/c2 input a/d converter a/d special event trigger www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 324 ? 2012 microchip technology inc. 20.1 ctmu operation the ctmu works by using a fixed current source to charge a circuit. the type of circuit depends on the type of measurement being made. in the case of charge measurement, the current is fixed and the amount of time the current is applied to the circuit is fixed. the amount of voltage read by the a/d is then a measure- ment of the capacitance of the circuit. in the case of time measurement, the current, as well as the capaci- tance of the circuit, is fixed. in this case, the voltage read by the a/d is then representative of the amount of time elapsed from the time the current source starts and stops charging the circuit. if the ctmu is being used as a time delay, both capaci- tance and current source are fixed, as well as the voltage supplied to the comparator circuit. the delay of a signal is determined by the amount of time it takes the voltage to charge to the comparator threshold voltage. 20.1.1 theory of operation the operation of the ctmu is based on the following equation for charge: more simply, the amount of charge measured in coulombs in a circuit is defined as current in amperes ( i ) multiplied by the amount of time in seconds that the current flows ( t ). charge is also defined as the capacitance in farads ( c ) multiplied by the voltage of the circuit ( v ). it follows that: the ctmu module provides a constant, known current source. the a/d converter is used to measure ( v ) in the equation, leaving two unknowns: capacitance ( c ) and time ( t ). the above equation can be used to calcu- late capacitance or time, by either the relationship using the known fixed capacitance of the circuit: or by: using a fixed time that the current source is applied to the circuit. 20.1.2 current source at the heart of the ctmu is a precision current source, designed to provide a constant reference for measure- ments. the level of current is user selectable across three ranges or a total of two orders of magnitude, with the ability to trim the output in 2% increments (nominal). the current range is selected by the irng<1:0> bits (ctmuicon<1:0>), with a value of ? 01 ? representing the lowest range. current trim is provided by the itrim<5:0> bits (ctmuicon<7:2>). these six bits allow trimming of the current source in steps of approximately 2% per step. note that half of the range adjusts the current source positively and the other half reduces the current source. a value of ? 000000 ? is the neutral position (no change). a value of ? 100001 ? is the maximum negative adjustment (approximately -62%) and ? 011111 ? is the maximum positive adjustment (approximately +62%). 20.1.3 edge selection and control ctmu measurements are controlled by edge events occurring on the module?s two input channels. each channel, referred to as edge 1 and edge 2, can be con- figured to receive input pulses from one of the edge input pins (cted1 and cted2), timer1 or output compare module 1. the input channels are level- sensitive, responding to the instantaneous level on the channel rather than a transition between levels. the inputs are selected using the edg1sel and edg2sel bit pairs (ctmuconl<3:2> and <6:5>). in addition to source, each channel can be configured for event polarity using the edge2pol and edge1pol bits (ctmuconl<7,4>). the input channels can also be filtered for an edge event sequence (edge 1 occur- ring before edge 2) by setting the edgseqen bit (ctmuconh<2>). i = c ? dv dt it ? cv . ? = tcv ? ?? i ? = cit ? ?? v ? = www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 325 pic18(l)f2x/45k50 20.1.4 edge status the ctmuconl register also contains two status bits: edg2stat and edg1stat (ctmuconl<1:0>). their primary function is to show if an edge response has occurred on the corresponding channel. the ctmu automatically sets a particular bit when an edge response is detected on its channel. the level-sensitive nature of the input channels also means that the status bits become set immediately if the channel?s configura- tion is changed and is the same as the channel?s current state. the module uses the edge status bits to control the cur- rent source output to external analog modules (such as the a/d converter). current is only supplied to external modules when only one (but not both) of the status bits is set, and shuts current off when both bits are either set or cleared. this allows the ctmu to measure cur- rent only during the interval between edges. after both status bits are set, it is necessary to clear them before another measurement is taken. both bits should be cleared simultaneously, if possible, to avoid re-enabling the ctmu current source. in addition to being set by the ctmu hardware, the edge status bits can also be set by software. this is also the user?s application to manually enable or disable the current source. setting either one (but not both) of the bits enables the current source. setting or clearing both bits at once disables the source. 20.1.5 interrupts the ctmu sets its interrupt flag (pir3<3>) whenever the current source is enabled, then disabled. an interrupt is generated only if the corresponding interrupt enable bit (pie3<3>) is also set. if edge sequencing is not enabled (i.e., edge 1 must occur before edge 2), it is necessary to monitor the edge status bits and determine which edge occurred last and caused the interrupt. 20.2 ctmu module initialization the following sequence is a general guideline used to initialize the ctmu module: 1. select the current source range using the irng bits (ctmuicon<1:0>). 2. adjust the current source trim using the itrim bits (ctmuicon<7:2>). 3. configure the edge input sources for edge 1 and edge 2 by setting the edg1sel and edg2sel bits (ctmuconl<3:2 and 6:5>). 4. configure the input polarities for the edge inputs using the edg1pol and edg2pol bits (ctmuconl<4,7>). the default configuration is for negative edge polarity (high-to-low transitions). 5. enable edge sequencing using the edgseqen bit (ctmuconh<2>). by default, edge sequencing is disabled. 6. select the operating mode (measurement or time delay) with the tgen bit. the default mode is time/capacitance measurement. 7. discharge the connected circuit by setting the idissen bit (ctmuconh<1>); after waiting a sufficient time for the circuit to discharge, clear idissen. 8. disable the module by clearing the ctmuen bit (ctmuconh<7>). 9. enable the module by setting the ctmuen bit. 10. clear the edge status bits: edg2stat and edg1stat (ctmuconl<1:0>). 11. enable both edge inputs by setting the edgen bit (ctmuconh<3>). depending on the type of measurement or pulse generation being performed, one or more additional modules may also need to be initialized and configured with the ctmu module: ? edge source generation: in addition to the external edge input pins, both timer1 and the output compare/pwm1 module can be used as edge sources for the ctmu. ? capacitance or time measurement: the ctmu module uses the a/d converter to measure the voltage across a capacitor that is connected to one of the analog input channels. ? pulse generation: when generating system clock independent output pulses, the ctmu module uses comparator 2 and the associated comparator voltage reference. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 326 ? 2012 microchip technology inc. 20.3 calibrating the ctmu module the ctmu requires calibration for precise measurements of capacitance and time, as well as for accurate time delay. if the application only requires measurement of a relative change in capacitance or time, calibration is usually not necessary. an example of this type of application would include a capacitive touch switch, in which the touch circuit has a baseline capacitance, and the added capacitance of the human body changes the overall capacitance of a circuit. if actual capacitance or time measurement is required, two hardware calibrations must take place: the current source needs calibration to set it to a precise current, and the circuit being measured needs calibration to measure and/or nullify all other capacitance other than that to be measured. 20.3.1 current source calibration the current source on the ctmu module is trimable. therefore, for precise measurements, it is possible to measure and adjust this current source by placing a high precision resistor, r cal , onto an unused analog channel. an example circuit is shown in figure 20-2 . the current source measurement is performed using the following steps: 1. initialize the a/d converter. 2. initialize the ctmu. 3. enable the current source by setting edg1stat (ctmuconl<0>). 4. issue settling time delay. 5. perform a/d conversion. 6. calculate the current source current using i=v/r cal , where r cal is a high precision resistance and v is measured by performing an a/d conversion. the ctmu current source may be trimmed with the trim bits in ctmuicon using an iterative process to get an exact desired current. alternatively, the nominal value without adjustment may be used; it may be stored by the software for use in all subsequent capacitive or time measurements. to calculate the value for r cal , the nominal current must be chosen, and then the resistance can be calculated. for example, if the a/d converter reference voltage is 3.3v, use 70% of full scale, or 2.31v as the desired approximate voltage to be read by the a/d converter. if the range of the ctmu current source is selected to be 0.55 ? a, the resistor value needed is cal- culated as r cal = 2.31v/0.55 ? a , for a value of 4.2 m ? . similarly, if the current source is chosen to be 5.5 ? a, r cal would be 420,000 ? , and 42,000 ? if the current source is set to 55 ? a. figure 20-2: ctmu current source calibration circuit a value of 70% of full-scale voltage is chosen to make sure that the a/d converter was in a range that is well above the noise floor. keep in mind that if an exact cur- rent is chosen, that is to incorporate the trimming bits from ctmuicon, the resistor value of r cal may need to be adjusted accordingly. r cal may also be adjusted to allow for available resistor values. r cal should be of the highest precision available, keeping in mind the amount of precision needed for the circuit that the ctmu will be used to measure. a recommended minimum would be 0.1% tolerance. the following examples show one typical method for performing a ctmu current calibration. example 20-1 demonstrates how to initialize the a/d converter and the ctmu; this routine is typical for applications using both modules. example 20-2 demonstrates one method for the actual calibration routine. pic18(l)fxxk50 device a/d converter ctmu anx r cal current source mux a/d www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 327 pic18(l)f2x/45k50 example 20-1: setup for ct mu calibration routines #include "p18cxxx.h" /**************************************************************************/ /*set up ctmu *****************************************************************/ /**************************************************************************/ void setup(void) { //ctmuconh/1 - ctmu control registers ctmuconh = 0x00; //make sure ctmu is disabled ctmuconl = 0x90; //ctmu continues to run when emulator is stopped,ctmu continues //to run in idle mode,time generation mode disabled, edges are blocked //no edge sequence order, analog current source not grounded, trigger //output disabled, edge2 polarity = positive level, edge2 source = //source 0, edge1 polarity = positive level, edge1 source = source 0, //ctmuicon - ctmu current control register ctmuicon = 0x01; //0.55ua, nominal - no adjustment /**************************************************************************/ //set up ad converter; /**************************************************************************/ trisa=0x04; //set channel 2 as an input // configure an2 as an analog channel anselabits.ansa2=1; trisabits.trisa2=1; // adcon2 adcon2bits.adfm=1; // results format 1= right justified adcon2bits.acqt=1; // acquition time 7 = 20tad 2 = 4tad 1=2tad adcon2bits.adcs=2; // clock conversion bits 6= fosc/64 2=fosc/32 // adcon1 adcon1bits.pvcfg0 =0; // vref+ = avdd adcon1bits.nvcfg1 =0; // vref- = avss // adcon0 adcon0bits.chs=2; // select adc channel adcon0bits.adon=1; // turn on adc } www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 328 ? 2012 microchip technology inc. example 20-2: current calibration routine #include "p18cxxx.h" #define count 500 //@ 8mhz = 125us. #define delay for(i=0;i pic18(l)f2x/45k50 ds30684a-page 330 ? 2012 microchip technology inc. example 20-3: capacitance calibration routine #include "p18cxxx.h" #define count 25 //@ 8mhz intfrc = 62.5 us. #define etime count*2.5 //time in us #define delay for(i=0;i pic18(l)f2x/45k50 ds30684a-page 332 ? 2012 microchip technology inc. example 20-4: routine fo r capacitive touch switch #include "p18cxxx.h" #define count 500 //@ 8mhz = 125us. #define delay for(i=0;i ? 2012 microchip technology inc. ds30684a-page 333 pic18(l)f2x/45k50 20.5 measuring time with the ctmu module time can be precisely measured after the ratio ( c/i ) is measured from the current and capacitance calibration step by following these steps: 1. initialize the a/d converter and the ctmu. 2. set edg1stat. 3. set edg2stat. 4. perform an a/d conversion. 5. calculate the time between edges as t = (c/i) * v , where i is calculated in the current calibration step ( section 20.3.1 ?current source calibration? ), c is calculated in the capacitance calibration step ( section 20.3.2 ?capacitance calibration? ) and v is measured by performing the a/d conversion. it is assumed that the time measured is small enough that the capacitance, c offset , provides a valid voltage to the a/d converter. for the smallest time measure- ment, always set the a/d channel select register (ad1chs) to an unused a/d channel; the correspond- ing pin for which is not connected to any circuit board trace. this minimizes added stray capacitance, keep- ing the total circuit capacitance close to that of the a/d converter itself (4-5 pf). to measure longer time intervals, an external capacitor may be connected to an a/d channel and this channel selected when making a time measurement. figure 20-3: typical connections and internal configuration for time measurement a/d converter ctmu cted1 cted2 an x output pulse edg1 edg2 c ad r pr current source pic18(l)fxxk22 device www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 334 ? 2012 microchip technology inc. 20.6 creating a delay with the ctmu module a unique feature on board the ctmu module is its ability to generate system clock independent output pulses based on an external capacitor value. this is accomplished using the internal comparator voltage reference module, comparator 2 input pin and an external capacitor. the pulse is output onto the ctpls pin. to enable this mode, set the tgen bit. see figure 20-4 for an example circuit. c pulse is chosen by the user to determine the output pulse width on ctpls. the pulse width is calculated by t =( c pulse / i )* v , where i is known from the current source measurement step ( section 20.3.1 ?current source calibration? ) and v is the internal reference voltage (cv ref ). an example use of this feature is for interfacing with variable capacitive-based sensors, such as a humidity sensor. as the humidity varies, the pulse width output on ctpls will vary. the ctpls output pin can be con- nected to an input capture pin and the varying pulse width is measured to determine the humidity in the application. follow these steps to use this feature: 1. initialize comparator 2. 2. initialize the comparator voltage reference. 3. initialize the ctmu and enable time delay generation by setting the tgen bit. 4. set edg1stat. 5. when c pulse charges to the value of the voltage reference trip point, an output pulse is generated on ctpls. figure 20-4: typical co nnections and internal co nfiguration for pulse delay generation 20.7 operation during sleep/idle modes 20.7.1 sleep mode when the device enters any sleep mode, the ctmu module current source is always disabled. if the ctmu is performing an operation that depends on the current source when sleep mode is invoked, the operation may not terminate correctly. capacitance and time measurements may return erroneous values. 20.7.2 idle mode the behavior of the ctmu in idle mode is determined by the ctmusidl bit (ctmuconh<5>). if ctmusidl is cleared, the module will continue to operate in idle mode. if ctmusidl is set, the module?s current source is disabled when the device enters idle mode. if the module is performing an operation when idle mode is invoked, in this case, the results will be similar to those with sleep mode. 20.8 ctmu peripheral module disable (pmd) when this peripheral is not used, the peripheral module disable bit can be set to disconnect all clock sources to the module, reducing power consumption to an absolute minimum. see section 4.6 ?selective peripheral module control? . c2 cv ref ctpls pic18(l)fxxk22 device current source comparator ctmu cted1 c12in1- c pulse edg1 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 335 pic18(l)f2x/45k50 20.9 effects of a reset on ctmu upon reset, all registers of the ctmu are cleared. this leaves the ctmu module disabled, its current source is turned off and all configuration options return to their default settings. the module needs to be re-initialized following any reset. if the ctmu is in the process of taking a measurement at the time of reset, the measurement will be lost. a partial charge may exist on the circuit that was being measured, and should be properly discharged before the ctmu makes subsequent attempts to make a measurement. the circuit is discharged by setting and then clearing the idissen bit (ctmuconh<1>) while the a/d converter is connected to the appropriate channel. 20.10 registers there are three control registers for the ctmu: ? ctmuconh ? ctmuconl ? ctmuicon the ctmuconh and ctmuconl registers ( register 20-1 and register 20-2 ) contain control bits for configuring the ctmu module edge source selec- tion, edge source polarity selection, edge sequencing, a/d trigger, analog circuit capacitor discharge and enables. the ctmuicon register ( register 20-3 ) has bits for selecting the current source range and current source trim. 20.11 register definitions: ctmu control register 20-1: ctmuconh: ct mu control register 0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 ctmuen ? ctmusidl tgen edgen edgseqen idissen cttrig bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 ctmuen: ctmu enable bit 1 = module is enabled 0 = module is disabled bit 6 unimplemented: read as ? 0 ? bit 5 ctmusidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 4 tgen: time generation enable bit 1 = enables edge delay generation 0 = disables edge delay generation bit 3 edgen: edge enable bit 1 = edges are not blocked 0 = edges are blocked bit 2 edgseqen: edge sequence enable bit 1 = edge 1 event must occur before edge 2 event can occur 0 = no edge sequence is needed bit 1 idissen: analog current source control bit 1 = analog current source output is grounded 0 = analog current source output is not grounded bit 0 cttrig: ctmu special event trigger control bit 1 = ctmu special event trigger is enabled 0 = ctmu special event trigger is disabled www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 336 ? 2012 microchip technology inc. register 20-2: ctmuconl: ct mu control register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 edg2pol edg2sel<1:0> edg1pol ed g1sel<1:0> edg2stat edg1stat bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 edg2pol: edge 2 polarity select bit 1 = edge 2 programmed for a positive edge response 0 = edge 2 programmed for a negative edge response bit 6-5 edg2sel<1:0>: edge 2 source select bits 11 = cted1 pin 10 = cted2 pin 01 = eccp1 special event trigger 00 = ccp2 special event trigger bit 4 edg1pol: edge 1 polarity select bit 1 = edge 1 programmed for a positive edge response 0 = edge 1 programmed for a negative edge response bit 3-2 edg1sel<1:0>: edge 1 source select bits 11 = cted1 pin 10 = cted2 pin 01 = eccp1 special event trigger 00 = ccp2 special event trigger bit 1 edg2stat: edge 2 status bit 1 = edge 2 event has occurred 0 = edge 2 event has not occurred bit 0 edg1stat: edge 1 status bit 1 = edge 1 event has occurred 0 = edge 1 event has not occurred www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 337 pic18(l)f2x/45k50 register 20-3: ctmuicon: ctmu current control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 itrim<5:0> irng<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-2 itrim<5:0>: current source trim bits 011111 = maximum positive change from nominal current 011110 . . . 000001 = minimum positive change from nominal current 000000 = nominal current output specified by irng<1:0> 111111 = minimum negative change from nominal current . . . 100010 100001 = maximum negative change from nominal current bit 1-0 irng<1:0>: current source range select bits (see tab l e 2 9- 4 ) 11 = 100 ? base current 10 = 10 ? base current 01 = base current level 00 = current source disabled table 20-1: registers associated with ctmu module name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ctmuconh ctmuen ? ctmusidl tgen edgen edgseqen idissen cttrig 335 ctmuconl edg2pol edg2sel<1:0> edg1pol edg1sel<1:0> edg2stat edg1stat 336 ctmuicon itrim<5:0> irng<1:0> 337 ipr3 ? ? ? ? ctmuip usbip tmr3gip tmr1gip 131 pie3 ? ? ? ? ctmuie usbie tmr3gie tmr1gie 128 pir3 ? ? ? ? ctmuif usbif tmr3gif tmr1gif 125 pmd1 ? msspmd ctmumd cmp2md cmp1md adcmd ccp2md ccp1md 65 legend: ? = unimplemented, read as ? 0 ?. shaded bits are not used during ctmu operation. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 338 ? 2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 339 pic18(l)f2x/45k50 21.0 sr latch the module consists of a single sr latch with multiple set and reset inputs as well as separate latch outputs. the sr latch module includes the following features: ? programmable input selection ? sr latch output is available internally/externally ? selectable q and q output ? firmware set and reset the sr latch can be used in a variety of analog applications, including oscillator circuits, one-shot circuit, hysteretic controllers, and analog timing applications. 21.1 latch operation the latch is a set-reset latch that does not depend on a clock source. each of the set and reset inputs are active-high. the latch can be set or reset by: ? software control (srps and srpr bits) ? comparator c1 output (sync_c1out) ? comparator c2 output (sync_c2out) ?sri pin ? programmable clock (divsrclk) the srps and the srpr bits of the srcon0 register may be used to set or reset the sr latch, respectively. the latch is reset-dominant. therefore, if both set and reset inputs are high, the latch will go to the reset state. both the srps and srpr bits are self resetting which means that a single write to either of the bits is all that is necessary to complete a latch set or reset operation. the output from comparator c1 or c2 can be used as the set or reset inputs of the sr latch. the output of either comparator can be synchronized to the timer1 clock source. see section 19.0 ?comparator module? and section 13.0 ?timer1/3 module with gate control? for more information. an external source on the sri pin can be used as the set or reset inputs of the sr latch. an internal clock source, divsrclk, is available and it can periodically set or reset the sr latch. the srclk<2:0> bits in the srcon0 register are used to select the clock source period. the srscke and srrcke bits of the srcon1 register enable the clock source to set or reset the sr latch, respectively. 21.2 latch output the srqen and srnqen bits of the srcon0 register control the q and q latch outputs. both of the sr latch outputs may be directly output to i/o pins at the same time. control is determined by the state of bits srqen and srnqen in the srcon0 register. the applicable tris bit of the corresponding port must be cleared to enable the port pin output driver. 21.3 divsrclk clock generation the divsrclk clock signal is generated from the peripheral clock which is pre-scaled by a value determined by the srclk<2:0> bits. see figure 21-1 and table 21-1 for additional detail. 21.4 effects of a reset upon any device reset, the sr latch is not initialized, and the srq and srnq outputs are unknown. the user?s firmware is responsible to initialize the latch output before enabling it to the output pins. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 340 ? 2012 microchip technology inc. figure 21-1: divsrclk block diagram figure 21-2: sr latch simplified block diagram 3 srclk<2:0> peripheral clock divsrclk programmable srclk divider 1:4 to 1:512 tosc 4 - 5 1 2 c y c l e s . . . srclk<2:0> = "001" 1:8 t0+4 t0 t0+8 t0+12 srps s r q q note 1: if r = 1 and s = 1 simultaneously, q = 0 , q = 1 2: pulse generator causes a pulse width of 2 t osc clock cycles. 3: name denotes the connection point at the comparator output. pulse gen ( 2 ) sr latch (1) srqen srspe srsc2e srscke divsrclk sync_c2out (3) srsc1e sync_c1out (3) srpr pulse gen ( 2 ) srrpe srrc2e srrcke divsrclk sync_c2out (3) srrc1e sync_c1out (3) srlen srnqen srlen srq srnq sri sri www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 341 pic18(l)f2x/45k50 table 21-1: divsrclk frequency table srclk<2:0> divider f osc = 20 mhz f osc = 16 mhz f osc = 8 mhz f osc = 4 mhz f osc = 1 mhz 111 512 25.6 ? s32 ? s64 ? s 128 ? s 512 ? s 110 256 12.8 ? s16 ? s32 ? s64 ? s 256 ? s 101 128 6.4 ? s8 ? s16 ? s32 ? s 128 ? s 100 64 3.2 ? s4 ? s8 ? s16 ? s64 ? s 011 32 1.6 ? s2 ? s4 ? s8 ? s32 ? s 010 16 0.8 ? s1 ? s2 ? s4 ? s16 ? s 001 80.4 ? s0.5 ? s1 ? s2 ? s8 ? s 000 40.2 ? s0.25 ? s0.5 ? s1 ? s4 ? s www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 342 ? 2012 microchip technology inc. 21.5 register definitions: sr latch control register 21-1: srcon0: sr latch control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 srlen srclk<2:0> srqen srnqen srps srpr bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented c = clearable only bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 srlen: sr latch enable bit (1) 1 = sr latch is enabled 0 = sr latch is disabled bit 6-4 srclk<2:0>: sr latch clock divider bits 000 = generates a 2 t osc wide pulse on divsrclk every 4 peripheral clock cycles 001 = generates a 2 t osc wide pulse on divsrclk every 8 peripheral clock cycles 010 = generates a 2 t osc wide pulse on divsrclk every 16 peripheral clock cycles 011 = generates a 2 t osc wide pulse on divsrclk every 32 peripheral clock cycles 100 = generates a 2 t osc wide pulse on divsrclk every 64 peripheral clock cycles 101 = generates a 2 t osc wide pulse on divsrclk every 128 peripheral clock cycles 110 = generates a 2 t osc wide pulse on divsrclk every 256 peripheral clock cycles 111 = generates a 2 t osc wide pulse on divsrclk every 512 peripheral clock cycles bit 3 srqen: sr latch q output enable bit 1 = q is present on the srq pin 0 = q is internal only bit 2 srnqen: sr latch q output enable bit 1 =q is present on the srnq pin 0 =q is internal only bit 1 srps: pulse set input of the sr latch bit (2) 1 = pulse set input for 2 t osc clock cycles 0 = no effect on set input bit 0 srpr: pulse reset input of the sr latch bit (2) 1 = pulse reset input for 2 t osc clock cycles 0 = no effect on reset input note 1: changing the srclk bits while the sr latch is enabled may cause false triggers to the set and reset inputs of the latch. 2: set only, always reads back ? 0 ?. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 343 pic18(l)f2x/45k50 register 21-2: srcon1: sr latch control register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 srspe srscke srsc2e srsc1e srrpe srrcke srrc2e srrc1e bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented c = clearable only bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 srspe: sr latch peripheral set enable bit 1 = sri pin status sets sr latch 0 = sri pin status has no effect on sr latch bit 6 srscke: sr latch set clock enable bit 1 = set input of sr latch is pulsed with divsrclk 0 = set input of sr latch is not pulsed with divsrclk bit 5 srsc2e: sr latch c2 set enable bit 1 = c2 comparator output sets sr latch 0 = c2 comparator output has no effect on sr latch bit 4 srsc1e: sr latch c1 set enable bit 1 = c1 comparator output sets sr latch 0 = c1 comparator output has no effect on sr latch bit 3 srrpe: sr latch peripheral reset enable bit 1 = sri pin resets sr latch 0 = sri pin has no effect on sr latch bit 2 srrcke: sr latch reset clock enable bit 1 = reset input of sr latch is pulsed with divsrclk 0 = reset input of sr latch is not pulsed with divsrclk bit 1 srrc2e: sr latch c2 reset enable bit 1 = c2 comparator output resets sr latch 0 = c2 comparator output has no effect on sr latch bit 0 srrc1e: sr latch c1 reset enable bit 1 = c1 comparator output resets sr latch 0 = c1 comparator output has no effect on sr latch table 21-2: registers associated with the sr latch name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page srcon0 srlen srclk<2:0> srqen srnqen srps srpr 342 srcon1 srspe srscke srsc2e srsc1e srrpe srrcke srrc2e srrc1e 343 trisa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 156 trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 156 wpub wpub7 wpub6 wpub5 wpub4 wpub3 wpub2 wpub1 wpub0 157 legend: shaded bits are not used with this module. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 344 ? 2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 345 pic18(l)f2x/45k50 22.0 fixed voltage reference (fvr) the fixed voltage reference, or fvr, is a stable voltage reference, independent of v dd , with 1.024v, 2.048v or 4.096v selectable output levels. the output of the fvr can be configured to supply a reference voltage to the following: ? adc input channel ? adc positive reference ? comparator positive input ? digital-to-analog converter (dac) the fvr can be enabled by setting the fvren bit of the vrefcon0 register. 22.1 independent gain amplifiers the output of the fvr supplied to the adc, comparators and dac is routed through an independent programmable gain amplifier. the amplifier can be configured to amplify the 1.024v reference voltage by 1x, 2x or 4x, to produce the three possible voltage levels. the fvrs<1:0> bits of the vrefcon0 register are used to enable and configure the gain amplifier settings for the reference supplied to the dac and comparator modules. when the adc module is configured to use the fvr output, (fvr buf2) the reference is buffered through an additional unity gain amplifier. this buffer is disabled if the adc is not configured to use the fvr. for specific use of the fvr, refer to the specific module sections: section 18.0 ?analog-to-digital converter (adc) module? , section 23.0 ?digital-to- analog converter (dac) module? and section 19.0 ?comparator module? . 22.2 fvr stabilization period when the fixed voltage reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. once the circuits stabilize and are ready for use, the fvrst bit of the vrefcon0 register will be set. see table 29-3 for the minimum delay requirement. figure 22-1: voltage reference block diagram fvrs<1:0> x 1 x 1 x 2 x 4 2 fvr buf2 (to adc module) fvr buf1 (to comparators, dac) + _ fvren fvrst 1.024v fixed reference www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 346 ? 2012 microchip technology inc. 22.3 register definitions: fvr control register 22-1: vrefcon0: fixed vo ltage reference control register r/w-0 r/w-0 r/w-0 r/w-1 u-0 u-0 u-0 u-0 fvren fvrst fvrs<1:0> ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 fvren: fixed voltage reference enable bit 0 = fixed voltage reference is disabled 1 = fixed voltage reference is enabled bit 6 fvrst: fixed voltage reference ready flag bit 0 = fixed voltage reference output is not ready or not enabled 1 = fixed voltage reference output is ready for use bit 5-4 fvrs<1:0>: fixed voltage reference selection bits 00 = fixed voltage reference peripheral output is off 01 = fixed voltage reference peripheral output is 1x (1.024v) 10 = fixed voltage reference peripheral output is 2x (2.048v) (1) 11 = fixed voltage reference peripheral output is 4x (4.096v) (1) bit 3-2 reserved: read as ? 0 ?. maintain these bits clear. bit 1-0 unimplemented: read as ? 0 ?. note 1: fixed voltage reference output cannot exceed v dd . table 22-1: summary of registers asso ciated with fixed voltage reference name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page vrefcon0 fvren fvrst fvrs<1:0> ? ? ? ? 346 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used by the fvr module. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 347 pic18(l)f2x/45k50 23.0 digital-to-analog converter (dac) module the digital-to-analog converter supplies a variable voltage reference, ratiometric with the input source, with 32 selectable output levels. the input of the dac can be connected to: ?external v ref pins ?v dd supply voltage ? fvr (fixed voltage reference) the output of the dac can be configured to supply a reference voltage to the following: ? comparator positive input ? adc input channel ?dacout pin the digital-to-analog converter (dac) can be enabled by setting the dacen bit of the vrefcon1 register. 23.1 output voltage selection the dac has 32 voltage level ranges. the 32 levels are set with the dacr<4:0> bits of the vrefcon2 register. the dac output voltage is determined by the following equations: equation 23-1: dac output voltage 23.2 ratiometric output level the dac output value is derived using a resistor ladder with each end of the ladder tied to a positive and negative voltage reference input source. if the voltage of either input source fluctuates, a similar fluctuation will result in the dac output value. the value of the individual resistors within the ladder can be found in section 29.0 ?electrical characteristics? . 23.3 low-power voltage state in order for the dac module to consume the least amount of power, one of the two voltage reference input sources to the resistor ladder must be disconnected. either the positive voltage source, (v src +), or the negative voltage source, (v src -) can be disabled. the negative voltage source is disabled by setting the daclps bit in the vrefcon1 register. clearing the daclps bit in the vrefcon1 register disables the positive voltage source. 23.4 output clamped to positive voltage source the dac output voltage can be set to v src + with the least amount of power consumption by performing the following: ? clearing the dacen bit in the vrefcon1 register. ? setting the daclps bit in the vrefcon1 register. ? configuring the dacpss bits to the proper positive source. ? configuring the dacrx bits to ? 11111 ? in the vrefcon2 register. this is also the method used to output the voltage level from the fvr to an output pin. see section 23.6 ?dac voltage reference output? for more information. 23.5 output clamped to negative voltage source the dac output voltage can be set to v src - with the least amount of power consumption by performing the following: ? clearing the dacen bit in the vrefcon1 register. ? clearing the daclps bit in the vrefcon1 register. ? configuring the dacpss bits to the proper negative source. ? configuring the dacrx bits to ? 00000 ? in the vrefcon2 register. this allows the comparator to detect a zero-crossing while not consuming additional current through the dac module. 23.6 dac voltage reference output the dac can be output to the dacout pin by setting the dacoe bit of the vrefcon1 register to ? 1 ?. selecting the dac reference voltage for output on the dacout pin automatically overrides the digital output buffer and digital input threshold detector functions of that pin. reading the dacout pin when it has been configured for dac reference voltage output will always return a ? 0 ?. due to the limited current drive capability, a buffer must be used on the dac voltage reference output for external connections to dacout. figure 23-2 shows an example buffering technique. v out v src +v src - ? ?? dacr<4:0> 2 5 ------------------------------ - ? ?? ?? = + v src - v src + = v dd , v ref + or fvr1 v src - = v ss or v ref - www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 348 ? 2012 microchip technology inc. figure 23-1: digital-to-analog co nverter block diagram figure 23-2: voltage reference ou tput buffer example 32-to-1 mux dacr<4:0> r v ref - dacnss r r r r r r 32 dac output dacout 5 (to comparators and adc modules) dacoe v dd v ref + dacpss<1:0> 2 dacen steps digital-to-analog converter (dac) fvr buf1 r v src - v src + v ss daclps 11111 11110 00001 00000 1 0 reserved 11 10 01 00 dacout buffered dac output + ? dac module voltage reference output impedance r pic ? mcu www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 349 pic18(l)f2x/45k50 23.7 operation during sleep when the device wakes up from sleep through an interrupt or a watchdog timer time-out, the contents of the vrefcon1 register are not affected. to minimize current consumption in sleep mode, the voltage reference should be disabled. 23.8 effects of a reset a device reset affects the following: ? dac is disabled ? dac output voltage is removed from the dacout pin ? the dacr<4:0> range select bits are cleared 23.9 register definitions: dac control register 23-1: vrefcon1: voltage reference control register 0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 u-0 r/w-0 dacen daclps dacoe ? dacpss<1:0> ? dacnss bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 dacen: dac enable bit 1 = dac is enabled 0 = dac is disabled bit 6 daclps: dac low-power voltage source select bit 1 = dac positive reference source selected 0 = dac negative reference source selected bit 5 dacoe: dac voltage output enable bit 1 = dac voltage level is also an output on the dacout pin 0 = dac voltage level is disconnected from the dacout pin bit 4 unimplemented: read as ? 0 ? bit 3-2 dacpss<1:0>: dac positive source select bits 00 =v dd 01 =v ref + 10 = fvr buf1 output 11 = reserved, do not use bit 1 unimplemented: read as ? 0 ? bit 0 dacnss: dac negative source select bits 1 =v ref - 0 =v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 350 ? 2012 microchip technology inc. register 23-2: vrefcon2: voltage reference control register 1 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? dacr<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-5 unimplemented: read as ? 0 ? bit 4-0 dacr<4:0>: dac voltage output select bits v out = ((v src +) - (v src -))*(dacr<4:0>/(2 5 )) + v src - table 23-1: registers asso ciated with dac module name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page vrefcon1 dacen daclps dacoe ? dacpss<1:0> ? dacnss 349 vrefcon2 ? ? ? dacr<4:0> 350 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are not used by the dac module. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 351 pic18(l)f2x/45k50 24.0 universal serial bus (usb) this section describes the details of the usb peripheral. because of the very specific nature of the module, knowledge of usb is expected. some high-level usb information is provided in section 3.14 ?oscillator settings for usb? only for application design reference. designers are encouraged to refer to the official specification published by the usb implementers forum (usb-if) for the latest information. 24.1 overview of the usb peripheral pic18f2x/45k50 devices contain a full-speed and low-speed compatible usb serial interface engine (sie) that allows fast communication between any usb host and the pic ? microcontroller. the sie can be interfaced directly to the usb by utilizing the internal transceiver. some special hardware features have been included to improve performance. dual access port memory in the device?s data memory space (usb ram) has been supplied to share direct memory access between the microcontroller core and the sie. buffer descriptors are also provided, allowing users to freely program end- point memory usage within the usb ram space. figure 24-1 presents a general overview of the usb peripheral and its features. figure 24-1: usb peripheral and options 1kbyte usb ram usb sie usb control and transceiver p p d+ d- internal pull-ups external 3.3v supply fsen upuen usb clock from the oscillator module optional external pull-ups (1) (low (full pic18(l)f2xk50/pic18(l)f45k50 family usb bus fs speed) speed) note 1: the internal pull-up resistors should be disabled (upuen = 0 ) if external pull-up resistors are used. 2: pic18f2x/45k50 devices only. configuration v usb 3 v 3 3.3v ldo regulator (2) uoe utrdis www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 352 ? 2012 microchip technology inc. 24.2 usb status and control the operation of the usb module is configured and managed through three control registers. in addition, a total of 14 registers are used to manage the actual usb transactions. the registers are: ? usb control register (ucon) ? usb configuration register (ucfg) ? usb transfer status register (ustat) ? usb device address register (uaddr) ? frame number registers (ufrmh:ufrml) ? endpoint enable registers 0 through 7 (uepn) 24.2.1 usb control register (ucon) the usb control register ( register 24-1 ) contains bits needed to control the module behavior during transfers. the register contains bits that control the following: ? main usb peripheral enable ? ping-pong buffer pointer reset ? control of the suspend mode ? packet transfer disable in addition, the usb control register contains a status bit, se0 (ucon<5>), which is used to indicate the occurrence of a single-ended zero on the bus. when the usb module is enabled, this bit should be moni- tored to determine whether the differential data lines have come out of a single-ended zero condition. this helps to differentiate the initial power-up state from the usb reset signal. the overall operation of the usb module is controlled by the usben bit (ucon<3>). setting this bit activates the module and resets all of the ppbi bits in the buffer descriptor table to ? 0 ?. this bit also activates the inter- nal pull-up resistors, if they are enabled. thus, this bit can be used as a soft attach/detach to the usb. although all status and control bits are ignored when this bit is clear, the module needs to be fully preconfig- ured prior to setting this bit. this bit cannot be set until the usb module is supplied with an active clock source. if the pll is being used, it should be enabled at least two milliseconds (enough time for the pll to lock) before attempting to set the usben bit. note: when disabling the usb module, make sure the suspnd bit (ucon<1>) is clear prior to clearing the usben bit. clearing the usben bit, when the module is in the suspended state, may prevent the module from fully powering down. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 353 pic18(l)f2x/45k50 register 24-1: ucon: usb control register u-0 r/w-0 r-x r/c-0 r/w-0 r/w-0 r/w-0 u-0 ? ppbrst se0 pktdis usben (1) resume suspnd ? bit 7 bit 0 legend: c = clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6 ppbrst: ping-pong buffers reset bit 1 = reset all ping-pong buffer pointers to the even buffer descriptor (bd) banks 0 = ping-pong buffer pointers not being reset bit 5 se0: live single-ended zero flag bit 1 = single-ended zero active on the usb bus 0 = no single-ended zero detected bit 4 pktdis: packet transfer disable bit 1 = sie token and packet processing disabled, automatically set when a setup token is received 0 = sie token and packet processing enabled bit 3 usben: usb module enable bit (1) 1 = usb module and supporting circuitry enabled (device attached) 0 = usb module and supporting circuitry disabled (device detached) bit 2 resume: resume signaling enable bit 1 = resume signaling activated 0 = resume signaling disabled bit 1 suspnd: suspend usb bit 1 = usb module and supporting circuitry in power conserve mode, sie clock inactive 0 = usb module and supporting circuitry in normal operation, sie clock clocked at the configured rate bit 0 unimplemented : read as ? 0 ? note 1: this bit cannot be set if the usb module does not have an appropriate clock source. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 354 ? 2012 microchip technology inc. the ppbrst bit (ucon<6>) controls the reset status when double-buffering mode (ping-pong buffering) is used. when the ppbrst bit is set, all ping-pong buf- fer pointers are set to the even buffers. ppbrst has to be cleared by firmware. this bit is ignored in buffer- ing modes not using ping-pong buffering. the pktdis bit (ucon<4>) is a flag indicating that the sie has disabled packet transmission and reception. this bit is set by the sie when a setup token is received to allow setup processing. this bit cannot be set by the microcontroller, only cleared; clearing it allows the sie to continue transmission and/or reception. any pending events within the buffer descriptor table will still be available, indicated within the ustat register?s fifo buffer. the resume bit (ucon<2>) allows the peripheral to perform a remote wake-up by executing resume signaling. to generate a valid remote wake-up, firmware must set resume for 10 ms and then clear the bit. for more information on ?resume signaling?, see the ?universal serial bus specification revision 2.0? . the suspnd bit (ucon<1>) places the module and supporting circuitry in a low-power mode. the input clock to the sie is also disabled. this bit should be set by the software in response to an idleif interrupt. it should be reset by the microcontroller firmware after an actvif interrupt is observed. when this bit is active, the device remains attached to the bus but the trans- ceiver outputs remain idle. the voltage on the v usb 3 v 3 pin may vary depending on the value of this bit. setting this bit before a idleif request will result in unpredict- able bus behavior. 24.2.2 usb configuration register (ucfg) prior to communicating over usb, the module?s associated internal and/or external hardware must be configured. most of the configuration is performed with the ucfg register ( register 24-2 ).the ucfg register contains most of the bits that control the system level behavior of the usb module. these include: ? bus speed (full speed versus low speed) ? on-chip pull-up resistor enable ? ping-pong buffer usage the uteye bit, ucfg<7>, enables eye pattern gener- ation, which aids in module testing, debugging and usb certifications. 24.2.2.1 internal transceiver the usb peripheral has a built-in, usb 2.0, full-speed and low-speed capable transceiver, internally con- nected to the sie. this feature is useful for low-cost, single chip applications. enabling the usb module (usben = 1 ) will also enable the internal transceiver. the fsen bit (ucfg<2>) controls the transceiver speed; setting the bit enables full-speed operation. the on-chip usb pull-up resistors are controlled by the upuen bit (ucfg<4>). they can only be selected when the on-chip transceiver is enabled. the internal usb transceiver obtains power from the v usb 3 v 3 pin. in order to meet usb signalling level specifications, v usb 3 v 3 must be supplied with a voltage source between 3.0v and 3.6v. the best electrical signal quality is obtained when a 3.3v supply is used and locally bypassed with a high quality ceramic capacitor. the capacitor should be placed as close as possible to the v usb 3 v 3 and v ss pins found on the same edge of the package (i.e., route ground of the capacitor to v ss pin 20 on 20-lead pdip, soic, ssop and qfn packaged parts). the d+ and d- signal lines can be routed directly to their respective pins on the usb connector or cable (for hard-wired applications). no additional resistors, capacitors, or magnetic components are required as the d+ and d- drivers have controlled slew rate and output impedance intended to match with the characteristic impedance of the usb cable. in order to meet the usb specifications, the traces should be less than 30 cm long. ideally, these traces should be designed to have a characteristic impedance matching that of the usb cable. note: while in suspend mode, a typical bus-powered usb device is limited to 2.5 ma of current. this is the complete current which may be drawn by the pic device and its supporting circuitry. care should be taken to assure minimum current draw when the device enters suspend mode. note: the usb speed, transceiver and pull-up should only be configured during the mod- ule setup phase. it is not recommended to switch these settings while the module is enabled. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 355 pic18(l)f2x/45k50 register 24-2: ucfg: usb config uration register (banked f39h) r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 uteye uoemon ? upuen (1,2) utrdis (1,3) fsen (1) ppb<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 uteye: usb eye pattern test enable bit 1 = eye pattern test is enabled 0 = eye pattern test is disabled bit 6 uoemon: usb oe monitor enable bit 1 =uoe signal is active, indicating intervals during which the d+/d- lines are driving 0 =uoe signal is inactive bit 5 unimplemented: read as ? 0 ? bit 4 upuen: usb on-chip pull-up enable bit (1,2) 1 = on-chip pull-up is enabled (pull-up on d+ with fsen = 1 or d- with fsen = 0 ) 0 = on-chip pull-up is disabled bit 3 utrdis: on-chip transceiver disable bit (1,3) 1 = on-chip transceiver is disabled 0 = on-chip transceiver is active bit 2 fsen: full-speed enable bit (1) 1 = full-speed device: controls transceiver edge rates; requires input clock at 48 mhz 0 = low-speed device: controls transceiver edge rates; requires input clock at 6 mhz bit 1-0 ppb<1:0>: ping-pong buffers configuration bits 11 = even/odd ping-pong buffers are enabled for endpoints 1 to 15 10 = even/odd ping-pong buffers are enabled for all endpoints 01 = even/odd ping-pong buffer are enabled for out endpoint 0 00 = even/odd ping-pong buffers are disabled note 1: the upuen, utrdis and fsen bits should never be changed while the usb module is enabled. these values must be preconfigured prior to enabling the module. 2: this bit is only valid when the on-chip transceiver is active (utrdis = 0 ); otherwise, it is ignored. 3: if utrdis is set, the uoe signal will be active, independent of the uoemon bit setting. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 356 ? 2012 microchip technology inc. 24.2.2.2 internal pull-up resistors the pic18f2x/45k50 devices have built-in pull-up resistors designed to meet the requirements for low-speed and full-speed usb. the upuen bit (ucfg<4>) enables the internal pull-ups. figure 24-1 shows the pull-ups and their control. 24.2.2.3 external pull-up resistors external pull-up may also be used. the v usb 3 v 3 pin may be used to pull up d+ or d-. the pull-up resistor must be 1.5 k ? (5%) as required by the usb specifications. figure 24-2 shows an example. figure 24-2: external circuitry 24.2.2.4 ping-pong buffer configuration the usage of ping-pong buffers is configured using the ppb<1:0> bits. refer to section 24.4.4 ?ping-pong buffering? for a complete explanation of the ping-pong buffers. 24.2.2.5 eye pattern test enable an automatic eye pattern test can be generated by the module when the ucfg<7> bit is set. the eye pattern output will be observable based on module settings, meaning that the user is first responsible for configuring the sie clock settings, pull-up resistor and transceiver mode. in addition, the module has to be enabled. once uteye is set, the module emulates a switch from a receive to transmit state and will start transmitting a j-k-j-k bit sequence (k-j-k-j for full speed). the sequence will be repeated indefinitely while the eye pattern test mode is enabled. note that this bit should never be set while the module is connected to an actual usb system. this test mode is intended for board verification to aid with usb certi- fication tests. it is intended to show a system developer the noise integrity of the usb signals which can be affected by board traces, impedance mismatches and proximity to other system components. it does not properly test the transition from a receive to a transmit state. although the eye pattern is not meant to replace the more complex usb certification test, it should aid during first order system debugging. note: the official usb specifications require that usb devices must never source any current onto the +5v v bus line of the usb cable. additionally, usb devices must never source any current on the d+ and d- data lines whenever the +5v v bus line is less than 1.17v. in order to meet this requirement, applications which are not purely bus powered should monitor the v bus line and avoid turning on the usb module and the d+ or d- pull-up resistor until v bus is greater than 1.17v. v bus can be connected to a resistive divider and monitored by an analog capable pin. pic ? microcontroller host controller/hub v usb d+ d- note: the above setting shows a typical connection for a full-speed configuration using an on-chip regulator and an external pull-up resistor. 1.5 k ? www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 357 pic18(l)f2x/45k50 24.2.3 usb status register (ustat) the usb status register reports the transaction status within the sie. when the sie issues a usb transfer complete interrupt, ustat should be read to determine the status of the transfer. ustat contains the transfer endpoint number, direction and ping-pong buffer pointer value (if used). the ustat register is actually a read window into a four-byte status fifo, maintained by the sie. it allows the microcontroller to process one transfer while the sie processes additional endpoints ( figure 24-3 ). when the sie completes using a buffer for reading or writing data, it updates the ustat register. if another usb transfer is performed before a transaction complete interrupt is serviced, the sie will store the status of the next transfer into the status fifo. clearing the transfer complete flag bit, trnif, causes the sie to advance the fifo. if the next data in the fifo holding register is valid, the sie will reassert the interrupt within 6 t cy of clearing trnif. if no additional data is present, trnif will remain clear; ustat data will no longer be reliable. figure 24-3: ustat fifo note: the data in the usb status register is valid two sie clocks after the trnif inter- rupt flag is asserted. in low-speed operation with the system clock operating at 48 mhz, a delay may be required between receiving the trnif interrupt and processing the data in the ustat register. note: if an endpoint request is received while the ustat fifo is full, the sie will automatically issue a nak back to the host. data bus ustat from sie 4-byte fifo for ustat clearing trnif advances fifo register 24-3: ustat: usb status register (access f64h) u-0 r-x r-x r-x r-x r-x r-x u-0 ? endp<3:0> dir ppbi (1) ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6-3 endp<3:0>: encoded number of last endpoint activity bits (represents the number of the bdt updated by the last usb transfer) 1111 = endpoint 15 1110 = endpoint 14 . . . 0001 = endpoint 1 0000 = endpoint 0 bit 2 dir: last bd direction indicator bit 1 = the last transaction was an in token 0 = the last transaction was an out or setup token bit 1 ppbi: ping-pong bd pointer indicator bit (1) 1 = the last transaction was to the odd bd bank 0 = the last transaction was to the even bd bank bit 0 unimplemented: read as ? 0 ? note 1: this bit is only valid for endpoints with available even and odd bd registers. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 358 ? 2012 microchip technology inc. 24.2.4 usb endpoint control each of the 16 possible bidirectional endpoints has its own independent control register, uepn (where ?n? rep- resents the endpoint number). each register has an identical complement of control bits. the prototype is shown in register 24-4 . the ephshk bit (uepn<4>) controls handshaking for the endpoint; setting this bit enables usb handshaking. typically, this bit is always set except when using isochronous endpoints. the epcondis bit (uepn<3>) is used to enable or disable usb control operations (setup) through the endpoint. clearing this bit enables setup transac- tions. note that the corresponding epinen and epouten bits must be set to enable in and out transactions. for endpoint 0, this bit should always be cleared since the usb specifications identify endpoint 0 as the default control endpoint. the epouten bit (uepn<2>) is used to enable or dis- able usb out transactions from the host. setting this bit enables out transactions. similarly, the epinen bit (uepn<1>) enables or disables usb in transactions from the host. the epstall bit (uepn<0>) is used to indicate a stall condition for the endpoint. if a stall is issued on a particular endpoint, the epstall bit for that end- point pair will be set by the sie. this bit remains set until it is cleared through firmware, or until the sie is reset. register 24-4: uepn: usb endpoint n co ntrol register (uep0 through uep15) u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ephshk epcondis epouten epinen epstall (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-5 unimplemented: read as ? 0 ? bit 4 ephshk: endpoint handshake enable bit 1 = endpoint handshake enabled 0 = endpoint handshake disabled (typically used for isochronous endpoints) bit 3 epcondis: bidirectional endpoint control bit if epouten = 1 and epinen = 1 : 1 = disable endpoint n from control transfers; only in and out transfers allowed 0 = enable endpoint n for control (setup) transfers; in and out transfers also allowed bit 2 epouten: endpoint output enable bit 1 = endpoint n output enabled 0 = endpoint n output disabled bit 1 epinen: endpoint input enable bit 1 = endpoint n input enabled 0 = endpoint n input disabled bit 0 epstall: endpoint stall enable bit (1) 1 = endpoint n is stalled 0 = endpoint n is not stalled note 1: valid only if endpoint n is enabled; otherwise, the bit is ignored. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 359 pic18(l)f2x/45k50 24.2.5 usb address register (uaddr) the usb address register contains the unique usb address that the peripheral will decode when active. uaddr is reset to 00h when a usb reset is received, indicated by urstif, or when a reset is received from the microcontroller. the usb address must be written by the microcontroller during the usb setup phase (enumeration) as part of the microchip usb firmware support. 24.2.6 usb frame number registers (ufrmh:ufrml) the frame number registers contain the 11-bit frame number. the low-order byte is contained in ufrml, while the three high-order bits are contained in ufrmh. the register pair is updated with the current frame number whenever a sof token is received. for the microcontroller, these registers are read-only. the frame number registers are primarily used for isochronous transfers. the contents of the ufrmh and ufrml registers are only valid when the 48 mhz sie clock is active (i.e., contents are inaccurate when suspnd (ucon<1>) bit = 1 ). 24.3 usb ram usb data moves between the microcontroller core and the sie through a memory space known as the usb ram. this is a special dual access memory that is mapped into the normal data memory space in banks 4 through 7 (400h to 7ffh) for a total of 1024 bytes ( figure 24-4 ). bank 4 (400h through 4ffh) is used specifically for endpoint buffer control. depending on the type of buffering being used, all but eight bytes of bank 4 may also be available for use as usb buffer space. although usb ram is available to the microcontroller as data memory, the sections that are being accessed by the sie should not be accessed by the microcontroller. a semaphore mechanism is used to determine the access to a particular buffer at any given time. this is discussed in section 24.4.1.1 ?buffer ownership? . figure 24-4: implementation of usb ram in data memory space 400h 7ffh buffer descriptors, usb data or user data sfrs 3ffh 000h f60h fffh banks 4 to 7 (usb ram) f5fh f53h f52h 800h banks 8 to 14 user data unused banks 15 usb data or user data 4ffh 500h www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 360 ? 2012 microchip technology inc. 24.4 buffer descriptors and the buffer descriptor table the registers in bank 4 are used specifically for end- point buffer control in a structure known as the buffer descriptor table (bdt). this provides a flexible method for users to construct and control endpoint buffers of various lengths and configuration. the bdt is composed of buffer descriptors (bd) which are used to define and control the actual buffers in the usb ram space. each bd, in turn, consists of four registers, where n represents one of the 64 possible bds (range of 0 to 63): ? bdnstat: bd status register ? bdncnt: bd byte count register ? bdnadrl: bd address low register ? bdnadrh: bd address high register bds always occur as a four-byte block in the sequence: bdnstat:bdncnt:bdnadrl:bdnadrh. the address of bdnstat is always an offset of (4n ? 1) (in hexa- decimal) from 400h, with n being the buffer descriptor number. depending on the buffering configuration used ( section 24.4.4 ?ping-pong buffering? ), there are up to 32, 33 or 64 sets of buffer descriptors. at a minimum, the bdt must be at least eight bytes long. this is because the usb specification mandates that every device must have endpoint 0, with both input and out- put for initial setup. depending on the endpoint and buffering configuration, the bdt can be as long as 256 bytes. although they can be thought of as special function registers, the buffer descriptor status and address registers are not hardware mapped, as conventional microcontroller sfrs in bank 15 are. if the endpoint cor- responding to a particular bd is not enabled, its registers are not used. instead of appearing as unimplemented addresses, however, they appear as available ram. only when an endpoint is enabled by setting the uepn<1> bit does the memory at those addresses become functional as bd registers. as with any address in the data memory space, the bd registers have an indeterminate value on any device reset. figure 24-5 provides an example of a bd for a 64-byte buffer, starting at 500h. a particular set of bd registers is only valid if the corresponding endpoint has been enabled using the uepn register. all bd registers are available in usb ram. the bd for each endpoint should be set up prior to enabling the endpoint. 24.4.1 bd status and configuration buffer descriptors not only define the size of an end- point buffer, but also determine its configuration and control. most of the configuration is done with the bd status register, bdnstat. each bd has its own unique and correspondingly numbered bdnstat register. figure 24-5: example of a buffer descriptor unlike other control registers, the bit configuration for the bdnstat register is context sensitive. there are two distinct configurations, depending on whether the microcontroller or the usb module is modifying the bd and buffer at a particular time. only three bit definitions are shared between the two. 24.4.1.1 buffer ownership because the buffers and their bds are shared between the cpu and the usb module, a simple semaphore mechanism is used to distinguish which is allowed to update the bd and associated buffers in memory. this is done by using the uown bit (bdnstat<7>) as a semaphore to distinguish which is allowed to update the bd and associated buffers in memory. uown is the only bit that is shared between the two configurations of bdnstat. when uown is clear, the bd entry is ?owned? by the microcontroller core. when the uown bit is set, the bd entry and the buffer memory are ?owned? by the usb peripheral. the core should not modify the bd or its corresponding data buffer during this time. note that the microcontroller core can still read bdnstat while the sie owns the buffer and vice versa. the buffer descriptors have a different meaning based on the source of the register update. prior to placing ownership with the usb peripheral, the user can configure the basic operation of the peripheral through the bdnstat bits. during this time, the byte count and buffer location registers can also be set. when uown is set, the user can no longer depend on the values that were written to the bds. from this point, the sie updates the bds as necessary, overwriting the original bd values. the bdnstat register is updated by the sie with the token pid and the transfer count, bdncnt, is updated. 400h usb data buffer buffer bd0stat bd0cnt bd0adrl bd0adrh 401h 402h 403h 500h 53fh descriptor note: memory regions are not to scale. 40h 00h 05h starting size of block (xxh) registers address contents address www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 361 pic18(l)f2x/45k50 the bdnstat byte of the bdt should always be the last byte updated when preparing to arm an endpoint. the sie will clear the uown bit when a transaction has completed. no hardware mechanism exists to block access when the uown bit is set. thus, unexpected behavior can occur if the microcontroller attempts to modify memory when the sie owns it. similarly, reading such memory may produce inaccurate data until the usb peripheral returns ownership to the microcontroller. 24.4.1.2 bdnstat register (cpu mode) when uown = 0 , the microcontroller core owns the bd. at this point, the other seven bits of the register take on control functions. the data toggle sync enable bit, dtsen (bdnstat<3>), controls data toggle parity checking. setting dtsen enables data toggle synchronization by the sie. when enabled, it checks the data packet?s par- ity against the value of dts (bdnstat<6>). if a packet arrives with an incorrect synchronization, the data will essentially be ignored. it will not be written to the usb ram and the usb transfer complete interrupt flag will not be set. the sie will send an ack token back to the host to acknowledge receipt, however. the effects of the dtsen bit on the sie are summarized in table 24-1 . the buffer stall bit, bstall (bdnstat<2>), provides support for control transfers, usually one-time stalls on endpoint 0. it also provides support for the set_feature/clear_feature commands speci- fied in chapter 9 of the usb specification; typically, continuous stalls to any endpoint other than the default control endpoint. the bstall bit enables buffer stalls. setting bstall causes the sie to return a stall token to the host if a received token would use the bd in that location. the epstall bit in the corresponding uepn control regis- ter is set and a stall interrupt is generated when a stall is issued to the host. the uown bit remains set and the bds are not changed unless a setup token is received. in this case, the stall condition is cleared and the ownership of the bd is returned to the microcontroller core. the bd<9:8> bits (bdnstat<1:0>) store the two most significant digits of the sie byte count; the lower eight digits are stored in the corresponding bdncnt register. see section 24.4.2 ?bd byte count? for more information. table 24-1: effect of dtsen bit on odd/even (data0/data1) packet reception out packet from host bdnstat settings device response after receiving packet dtsen dts handshake uown trnif bdnstat and ustat status data0 10 ack 01 updated data1 10 ack 10 not updated data0 11 ack 10 not updated data1 11 ack 01 updated either 0x ack 01 updated either, with error xx nak 10 not updated legend: x = don?t care www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 362 ? 2012 microchip technology inc. register 24-5: bdnstat: buffer descriptor n status register (bd0stat through bd63stat), cpu mode (banked 4xxh) r/w-x r/w-x u-0 u-0 r/w-x r/w-x r/w-x r/w-x uown (1) dts (2) ? (3) ? (3) dtsen bstall bc9 bc8 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 uown: usb own bit (1) 0 = the microcontroller core owns the bd and its corresponding buffer bit 6 dts: data toggle synchronization bit (2) 1 = data 1 packet 0 = data 0 packet bit 5-4 unimplemented: these bits should always be programmed to ? 0 ? (3) . bit 3 dtsen: data toggle synchronization enable bit 1 = data toggle synchronization is enabled; data packets with incorrect sync value will be ignored except for a setup transaction, which is accepted even if the data toggle bits do not match 0 = no data toggle synchronization is performed bit 2 bstall: buffer stall enable bit 1 = buffer stall enabled; stall handshake issued if a token is received that would use the bd in the given location (uown bit remains set, bd value is unchanged) 0 = buffer stall disabled bit 1-0 bc<9:8>: byte count 9 and 8 bits the byte count bits represent the number of bytes that will be transmitted for an in token or received during an out token. together with bc<7:0>, the valid byte counts are 0-1023. note 1: this bit must be initialized by the user to the desired value prior to enabling the usb module. 2: this bit is ignored unless dtsen = 1 . 3: if these bits are set, usb communication may not work. hence, these bits should always be maintained as ? 0 ?. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 363 pic18(l)f2x/45k50 24.4.1.3 bdnstat register (sie mode) when the bd and its buffer are owned by the sie, most of the bits in bdnstat take on a different meaning. the configuration is shown in register 24-6 . once the uown bit is set, any data or control settings previously written there by the user will be overwritten with data from the sie. the bdnstat register is updated by the sie with the token packet identifier (pid) which is stored in bdnstat<5:3>. the transfer count in the correspond- ing bdncnt register is updated. values that overflow the 8-bit register carry over to the two most significant digits of the count, stored in bdnstat<1:0>. 24.4.2 bd byte count the byte count represents the total number of bytes that will be transmitted during an in transfer. after an in transfer, the sie will return the number of bytes sent to the host. for an out transfer, the byte count represents the maximum number of bytes that can be received and stored in usb ram. after an out transfer, the sie will return the actual number of bytes received. if the number of bytes received exceeds the corresponding byte count, the data packet will be rejected and a nak handshake will be generated. when this happens, the byte count will not be updated. the 10-bit byte count is distributed over two registers. the lower eight bits of the count reside in the bdncnt register. the upper two bits reside in bdnstat<1:0>. this represents a valid byte range of 0 to 1023. 24.4.3 bd address validation the bd address register pair contains the starting ram address location for the corresponding endpoint buffer. no mechanism is available in hardware to validate the bd address. if the value of the bd address does not point to an address in the usb ram, or if it points to an address within another endpoint?s buffer, data is likely to be lost or overwritten. similarly, overlapping a receive buffer (out endpoint) with a bd location in use can yield unexpected results. when developing usb applications, the user may want to consider the inclusion of software-based address validation in their code. register 24-6: bdnstat: buffer descriptor n status register (bd0stat through bd63stat), sie mode (data returned by the side to the mcu) r/w-x u-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x uown ? pid3 pid2 pid1 pid0 bc9 bc8 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 uown: usb own bit 1 = the sie owns the bd and its corresponding buffer bit 6 reserved: not written by the sie bit 5-2 pid<3:0>: packet identifier bits the received token pid value of the last transfer (in, out or setup transactions only). bit 1-0 bc<9:8>: byte count 9 and 8 bits these bits are updated by the sie to reflect the actual number of bytes received on an out transfer and the actual number of bytes transmitted on an in transfer. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 364 ? 2012 microchip technology inc. 24.4.4 ping-pong buffering an endpoint is defined to have a ping-pong buffer when it has two sets of bd entries: one set for an even transfer and one set for an odd transfer. this allows the cpu to process one bd while the sie is processing the other bd. double-buffering bds in this way allows for maximum throughput to/from the usb. the usb module supports four modes of operation: ? no ping-pong support ? ping-pong buffer support for out endpoint 0 only ? ping-pong buffer support for all endpoints ? ping-pong buffer support for all other endpoints except endpoint 0 the ping-pong buffer settings are configured using the ppb<1:0> bits in the ucfg register. the usb module keeps track of the ping-pong pointer individually for each endpoint. all pointers are initially reset to the even bd when the module is enabled. after the completion of a transaction (uown cleared by the sie), the pointer is toggled to the odd bd. after the completion of the next transaction, the pointer is toggled back to the even bd and so on. the even/odd status of the last transaction is stored in the ppbi bit of the ustat register. the user can reset all ping-pong pointers to even using the ppbrst bit. figure 24-6 shows the four different modes of operation and how usb ram is filled with the bds. bds have a fixed relationship to a particular endpoint, depending on the buffering configuration. the mapping of bds to endpoints is detailed in tab l e 2 4- 2 . this relationship also means that gaps may occur in the bdt if endpoints are not enabled contiguously. this theoretically means that the bds for disabled endpoints could be used as buffer space. in practice, users should avoid using such spaces in the bdt unless a method of validating bd addresses is implemented. figure 24-6: buffer descriptor t able mapping for buffering modes ep1 in even ep1 out even ep1 out odd ep1 in odd descriptor descriptor descriptor descriptor ep1 in ep15 in ep1 out ep0 out ppb<1:0> = 00 ep0 in ep1 in no ping-pong ep15 in ep0 in ep0 out even ppb<1:0> = 01 ep0 out odd ep1 out ping-pong buffer ep15 in odd ep0 in even ep0 out even ppb<1:0> = 10 ep0 out odd ep0 in odd ping-pong buffers descriptor descriptor descriptor descriptor descriptor descriptor descriptor descriptor descriptor descriptor descriptor descriptor 400h 4ffh 4ffh 4ffh 400h 400h 47fh 483h available as data ram available as data ram maximum memory used: 128 bytes maximum bds: 32 (bd0 to bd31) maximum memory used: 132 bytes maximum bds: 33 (bd0 to bd32) maximum memory used: 256 bytes maximum bds: 64 (bd0 to bd63) note: memory area is not shown to scale. descriptor descriptor descriptor descriptor buffers on ep0 out on all eps ep1 in even ep1 out even ep1 out odd ep1 in odd descriptor descriptor descriptor descriptor ep15 in odd ep0 out ppb<1:0> = 11 ep0 in ping-pong buffers descriptor descriptor descriptor 4ffh 400h maximum memory used: 248 bytes maximum bds: 62 (bd0 to bd61) on all other eps except ep0 available as data ram 4f7h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 365 pic18(l)f2x/45k50 table 24-2: assignment of buffer descriptors for the different buffering modes endpoint bds assigned to endpoint mode 0 (no ping-pong) mode 1 (ping-pong on ep0 out) mode 2 (ping-pong on all eps) mode 3 (ping-pong on all other eps, except ep0) out in out in out in out in 0 0 1 0 (e), 1 (o) 2 0 (e), 1 (o) 2 (e), 3 (o) 0 1 1 2 3 3 4 4 (e), 5 (o) 6 (e), 7 (o) 2 (e), 3 (o) 4 (e), 5 (o) 2 4 5 5 6 8 (e), 9 (o) 10 (e), 11 (o) 6 (e), 7 (o) 8 (e), 9 (o) 3 6 7 7 8 12 (e), 13 (o) 14 (e), 15 (o) 10 (e), 11 (o) 12 (e), 13 (o) 4 8 9 9 10 16 (e), 17 (o) 18 (e), 19 (o) 14 (e), 15 (o) 16 (e), 17 (o) 5 10 11 11 12 20 (e), 21 (o) 22 (e), 23 (o) 18 (e), 19 (o) 20 (e), 21 (o) 6 12 13 13 14 24 (e), 25 (o) 26 (e), 27 (o) 22 (e), 23 (o) 24 (e), 25 (o) 7 14 15 15 16 28 (e), 29 (o) 30 (e), 31 (o) 26 (e), 27 (o) 28 (e), 29 (o) 8 16 17 17 18 32 (e), 33 (o) 34 (e), 35 (o) 30 (e), 31 (o) 32 (e), 33 (o) 9 18 19 19 20 36 (e), 37 (o) 38 (e), 39 (o) 34 (e), 35 (o) 36 (e), 37 (o) 10 20 21 21 22 40 (e), 41 (o) 42 (e), 43 (o) 38 (e), 39 (o) 40 (e), 41 (o) 11 22 23 23 24 44 (e), 45 (o) 46 (e), 47 (o) 42 (e), 43 (o) 44 (e), 45 (o) 12 24 25 25 26 48 (e), 49 (o) 50 (e), 51 (o) 46 (e), 47 (o) 48 (e), 49 (o) 13 26 27 27 28 52 (e), 53 (o) 54 (e), 55 (o) 50 (e), 51 (o) 52 (e), 53 (o) 14 28 29 29 30 56 (e), 57 (o) 58 (e), 59 (o) 54 (e), 55 (o) 56 (e), 57 (o) 15 30 31 31 32 60 (e), 61 (o) 62 (e), 63 (o) 58 (e), 59 (o) 60 (e), 61 (o) legend: (e) = even transaction buffer, (o) = odd transaction buffer table 24-3: summary of usb buffer descriptor table registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bdnstat (1) uown dts (4) pid3 (2) pid2 (2) pid1 (2) dtsen (3) pid0 (2) bstall (3) bc9 bc8 bdncnt (1) byte count bdnadrl (1) buffer address low bdnadrh (1) buffer address high note 1: for buffer descriptor registers, n may have a value of 0 to 63. for the sake of brevity, all 64 registers are shown as one generic prototype. all registers have indeterminate reset values ( xxxx xxxx ). 2: bits 5 through 2 of the bdnstat register are used by the sie to return pid<3:0> values once the register is turned over to the sie (uown bit is set). once the registers have been under sie control, the values written for dtsen and bstall are no longer valid. 3: prior to turning the buffer descriptor over to the sie (uown bit is cleared), bits 5 through 2 of the bdnstat register are used to configure the dtsen and bstall settings. 4: this bit is ignored unless dtsen = 1 . www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 366 ? 2012 microchip technology inc. 24.5 usb interrupts the usb module can generate multiple interrupt con- ditions. to accommodate all of these interrupt sources, the module is provided with its own interrupt logic structure, similar to that of the microcontroller. usb interrupts are enabled with one set of control registers and trapped with a separate set of flag registers. all sources are funneled into a single usb interrupt request, usbif (pir3<2>), in the microcontroller?s interrupt logic. figure 24-7 shows the interrupt logic for the usb module. there are two layers of interrupt registers in the usb module. the top level consists of overall usb status interrupts; these are enabled and flagged in the uie and uir registers, respectively. the second level consists of usb error conditions, which are enabled and flagged in the ueir and ueie registers. an interrupt condition in any of these triggers a usb error interrupt flag (uerrif) in the top level. interrupts may be used to trap routine events in a usb transaction. figure 24-8 shows some common events within a usb frame and their corresponding interrupts. figure 24-7: usb interrupt logic funnel figure 24-8: example of a usb transaction and interrupt events btsef btsee btoef btoee dfn8ef dfn8ee crc16ef crc16ee crc5ef crc5ee pidef pidee sofif sofie trnif trnie idleif idleie stallif stallie actvif actvie urstif urstie uerrif uerrie usbif second level usb interrupts (usb error conditions) ueir (flag) and ueie (enable) registers top level usb interrupts (usb status interrupts) uir (flag) and uie (enable) registers usb reset sof reset setup data status sof setup token data ack out token empty data ack start-of-frame (sof) in token data ack sofif urstif 1 ms frame differential data from host from host to h o s t from host to host from host from host from host to h o s t transaction control transfer (1) transaction complete note 1: the control transfer shown here is only an example showing events that can occur for every transaction. typical control transfe rs will spread across multiple frames. set trnif set trnif set trnif www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 367 pic18(l)f2x/45k50 24.5.1 usb interrupt status register (uir) the usb interrupt status register ( register 24-7 ) contains the flag bits for each of the usb status interrupt sources. each of these sources has a corresponding interrupt enable bit in the uie register. all of the usb status flags are ored together to generate the usbif interrupt flag for the microcontroller?s interrupt funnel. once an interrupt bit has been set by the sie, it must be cleared by software by writing a ? 0 ?. the flag bits can also be set in software which can aid in firmware debugging. when the usb module is in the low-power suspend mode (ucon<1> = 1 ), the sie does not get clocked. when in this state, the sie cannot process packets and, therefore, cannot detect new interrupt conditions other than the activity detect interrupt, actvif. the actvif bit is typically used by usb firmware to detect when the microcontroller should bring the usb module out of the low-power suspend mode (ucon<1> = 0 ). register 24-7: uir: usb interrupt status register u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r/w-0 ? sofif stallif idleif (1) trnif (2) actvif (3) uerrif (4) urstif bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6 sofif: start-of-frame token interrupt bit 1 = a start-of-frame token received by the sie 0 = no start-of-frame token received by the sie bit 5 stallif: a stall handshake interrupt bit 1 = a stall handshake was sent by the sie 0 = a stall handshake has not been sent bit 4 idleif: idle detect interrupt bit (1) 1 = idle condition detected (constant idle state of 3 ms or more) 0 = no idle condition detected bit 3 trnif: transaction complete interrupt bit (2) 1 = processing of pending transaction is complete; read ustat register for endpoint information 0 = processing of pending transaction is not complete or no transaction is pending bit 2 actvif: bus activity detect interrupt bit (3) 1 = activity on the d+/d- lines was detected 0 = no activity detected on the d+/d- lines bit 1 uerrif: usb error condition interrupt bit (4) 1 = an unmasked error condition has occurred 0 = no unmasked error condition has occurred bit 0 urstif: usb reset interrupt bit 1 = valid usb reset occurred; 00h is loaded into uaddr register 0 = no usb reset has occurred note 1: once an idle state is detected, the user may want to place the usb module in suspend mode. 2: clearing this bit will cause the ustat fifo to advance (valid only for in, out and setup tokens). 3: this bit is typically unmasked only following the detection of a uidle interrupt event. 4: only error conditions enabled through the ueie register will set this bit. this bit is a status bit only and cannot be set or cleared by the user. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 368 ? 2012 microchip technology inc. 24.5.1.1 bus activity detect interrupt bit (actvif) the actvif bit cannot be cleared immediately after the usb module wakes up from suspend or while the usb module is suspended. a few clock cycles are required to synchronize the internal hardware state machine before the actvif bit can be cleared by firmware. clearing the actvif bit before the internal hardware is synchronized may not have an effect on the value of actvif. additionally, if the usb module uses the clock from the 48 mhz pll source, then after clearing the suspnd bit, the usb module may not be immediately operational while waiting for the 48 mhz pll to lock. the application code should clear the actvif flag as shown in example 24-1 . only one actvif interrupt is generated when resuming from the usb bus idle condition. if user firmware clears the actvif bit, the bit will not immediately become set again, even when there is continuous bus traffic. bus traffic must cease long enough to generate another idleif condition before another actvif interrupt can be generated. example 24-1: clearing actvif bit (uir<2>) assembly: bcf ucon, suspnd loop: btfss uir, actvif bra done bcf uir, actvif bra loop done: c: uconbits.suspnd = 0 ; while (uirbits.actvif) { uirbits.actvif = 0 ; } www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 369 pic18(l)f2x/45k50 24.5.2 usb interrupt enable register (uie) the usb interrupt enable register ( register 24-8 ) contains the enable bits for the usb status interrupt sources. setting any of these bits will enable the respective interrupt source in the uir register. the values in this register only affect the propagation of an interrupt condition to the microcontroller?s interrupt logic. the flag bits are still set by their interrupt conditions, allowing them to be polled and serviced without actually generating an interrupt. register 24-8: uie: usb interrupt enable register u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? sofie stallie idleie trnie actvie uerrie urstie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6 sofie: start-of-frame token interrupt enable bit 1 = start-of-frame token interrupt enabled 0 = start-of-frame token interrupt disabled bit 5 stallie: stall handshake interrupt enable bit 1 = stall interrupt enabled 0 = stall interrupt disabled bit 4 idleie: idle detect interrupt enable bit 1 = idle detect interrupt enabled 0 = idle detect interrupt disabled bit 3 trnie: transaction complete interrupt enable bit 1 = transaction interrupt enabled 0 = transaction interrupt disabled bit 2 actvie: bus activity detect interrupt enable bit 1 = bus activity detect interrupt enabled 0 = bus activity detect interrupt disabled bit 1 uerrie: usb error interrupt enable bit 1 = usb error interrupt enabled 0 = usb error interrupt disabled bit 0 urstie: usb reset interrupt enable bit 1 = usb reset interrupt enabled 0 = usb reset interrupt disabled www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 370 ? 2012 microchip technology inc. 24.5.3 usb error interrupt status register (ueir) the usb error interrupt status register ( register 24-9 ) contains the flag bits for each of the error sources within the usb peripheral. each of these sources is controlled by a corresponding interrupt enable bit in the ueie register. all of the usb error flags are ored together to generate the usb error interrupt flag (uerrif) at the top level of the interrupt logic. each error bit is set as soon as the error condition is detected. thus, the interrupt will typically not correspond with the end of a token being processed. once an interrupt bit has been set by the sie, it must be cleared by software by writing a ? 0 ?. register 24-9: ueir: usb erro r interrupt status register r/c-0 u-0 u-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 btsef ? ? btoef dfn8ef crc16ef crc5ef pidef bit 7 bit 0 legend: r = readable bit c = clearable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 btsef: bit stuff error flag bit 1 = a bit stuff error has been detected 0 = no bit stuff error bit 6-5 unimplemented: read as ? 0 ? bit 4 btoef: bus turnaround time-out error flag bit 1 = bus turnaround time-out has occurred (more than 16 bit times of idle from previous eop elapsed) 0 = no bus turnaround time-out bit 3 dfn8ef: data field size error flag bit 1 = the data field was not an integral number of bytes 0 = the data field was an integral number of bytes bit 2 crc16ef: crc16 failure flag bit 1 = the crc16 failed 0 = the crc16 passed bit 1 crc5ef: crc5 host error flag bit 1 = the token packet was rejected due to a crc5 error 0 = the token packet was accepted bit 0 pidef: pid check failure flag bit 1 = pid check failed 0 = pid check passed www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 371 pic18(l)f2x/45k50 24.5.4 usb error interrupt enable register (ueie) the usb error interrupt enable register ( register 24-10 ) contains the enable bits for each of the usb error interrupt sources. setting any of these bits will enable the respective error interrupt source in the ueir register to propagate into the uerr bit at the top level of the interrupt logic. as with the uie register, the enable bits only affect the propagation of an interrupt condition to the micro- controller?s interrupt logic. the flag bits are still set by their interrupt conditions, allowing them to be polled and serviced without actually generating an interrupt. register 24-10: ueie: usb error interrupt enable register r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 btsee ? ? btoee dfn8ee crc16ee crc5ee pidee bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 btsee: bit stuff error interrupt enable bit 1 = bit stuff error interrupt enabled 0 = bit stuff error interrupt disabled bit 6-5 unimplemented: read as ? 0 ? bit 4 btoee: bus turnaround time-out error interrupt enable bit 1 = bus turnaround time-out error interrupt enabled 0 = bus turnaround time-out error interrupt disabled bit 3 dfn8ee: data field size error interrupt enable bit 1 = data field size error interrupt enabled 0 = data field size error interrupt disabled bit 2 crc16ee: crc16 failure interrupt enable bit 1 = crc16 failure interrupt enabled 0 = crc16 failure interrupt disabled bit 1 crc5ee: crc5 host error interrupt enable bit 1 = crc5 host error interrupt enabled 0 = crc5 host error interrupt disabled bit 0 pidee: pid check failure interrupt enable bit 1 = pid check failure interrupt enabled 0 = pid check failure interrupt disabled www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 372 ? 2012 microchip technology inc. 24.6 usb power modes many usb applications will likely have several different sets of power requirements and configuration. the most common power modes encountered are bus power only, self-power only and dual power with self-power dominance. the most common cases are presented here. also provided is a means of estimating the current consumption of the usb transceiver. 24.6.1 bus power only in bus power only mode, all power for the application is drawn from the usb ( figure 24-9 ). this is effectively the simplest power method for the device. in order to meet the inrush current requirements of the usb 2.0 specifications, the total effective capacitance appearing across v bus and ground must be no more than 10 f. if not, some kind of inrush liming is required. for more details, see section 7.2.4 of the usb 2.0 specification. according to the usb 2.0 specification, all usb devices must also support a low-power suspend mode. in the usb suspend mode, devices must consume no more than 2.5 ma from the 5v v bus line of the usb cable. the host signals the usb device to enter the suspend mode by stopping all usb traffic to that device for more than 3 ms. this condition will cause the idleif bit in the uir register to become set. during the usb suspend mode, the d+ or d- pull-up resistor must remain active, which will consume some of the allowed suspend current: 2.5 ma budget. figure 24-9: bus power only 24.6.2 self-power only in self-power only mode, the usb application provides its own power, with very little power being pulled from the usb. figure 24-10 shows an example. in order to meet compliance specifications, the usb module (and the d+ or d- pull-up resistor) should not be enabled until the host actively drives v bus high. the application should never source any current onto the 5v v bus pin of the usb cable. figure 24-10: self-power only v dd v usb v ss v bus v dd v usb v ss v self www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 373 pic18(l)f2x/45k50 24.6.3 dual power with self-power dominance some applications may require a dual power option. this allows the application to use internal power pri- marily, but switch to power from the usb when no inter- nal power is available. figure 24-11 shows a simple dual power with self-power dominance mode exam- ple, which automatically switches between self-power only and usb bus power only modes. dual power devices must also meet all of the special requirements for inrush current and suspend mode current and must not enable the usb module until v bus is driven high. see section 24.6.1 ?bus power only? and section 24.6.2 ?self-power only? for descriptions of those requirements. additionally, dual power devices must never source current onto the 5v v bus pin of the usb cable. figure 24-11: dual power example 24.6.4 usb transceiver current consumption the usb transceiver consumes a variable amount of current depending on the characteristic impedance of the usb cable, the length of the cable, the v usb 3 v 3 supply voltage and the actual data patterns moving across the usb cable. longer cables have larger capacitances and consume more total energy when switching output states. data patterns that consist of ?in? traffic consume far more current than ?out? traffic. in traffic requires the pic ? device to drive the usb cable, whereas out traffic requires that the host drive the usb cable. the data that is sent across the usb cable is nrzi encoded. in the nrzi encoding scheme, ? 0 ? bits cause a toggling of the output state of the transceiver (either from a ?j? state to a ?k? state, or vise versa). with the exception of the effects of bit-stuffing, nrzi encoded ? 1 ? bits do not cause the output state of the transceiver to change. therefore, in traffic consisting of data bits of value, ? 0 ?, cause the most current consumption, as the transceiver must charge/discharge the usb cable in order to change states. more details about nrzi encoding and bit-stuffing can be found in the usb 2.0 specification?s section 7.1, although knowledge of such details is not required to make usb applications using the pic18f2x/45k50 of microcontrollers. among other things, the sie handles bit-stuffing/unstuffing, nrzi encoding/decoding and crc generation/checking in hardware. the total transceiver current consumption will be application-specific. however, to help estimate how much current actually may be required in full-speed applications, equation 24-1 can be used. example 24-2 shows how this equation can be used for a theoretical application. note: users should keep in mind the limits for devices drawing power from the usb. according to usb specification 2.0, this cannot exceed 100 ma per low-power device or 500 ma per high-power device. v dd v usb v ss v bus v self ~5v ~5v 100 k ? www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 374 ? 2012 microchip technology inc. equation 24-1: estimating usb t ransceiver current consumption example 24-2: calculating usb transceiver current ? i xcvr = + i pullup (60 ma ? v usb 3 v 3 ? p zero ? p in ? l cable ) (3.3v ? 5m) legend: v usb : voltage applied to the v usb 3 v 3 pin in volts. (should be 3.0v to 3.6v.) p zero : percentage (in decimal) of the in traffic bits sent by the pic ? device that are a value of ? 0 ?. p in : percentage (in decimal) of total bus bandwidth that is used for in traffic. l cable : length (in meters) of the usb cable. the usb 2. 0 specification requires that full-speed applications use cables no longer than 5m. i pullup : current which the nominal, 1.5 k ? pull-up resistor (when enabled) must supply to the usb cable. on the host or hub end of the usb cable, 15 k ? nominal resistors (14.25 k ? to 24.8 k ? ) are present which pull both the d+ and d- lines to ground. during bus id le conditions (such as between packets or during usb suspend mode), this results in up to 218 ? a of quiescent current drawn at 3.3v. i pullup is also dependant on bus traffic conditions and can be as high as 2.2 ma when the usb bandwidth is fully utilized (either in or out traffic) for data that drives the lines to the ?k? state most of the time. for this example, the following assumptions are made about the application: ? 3.3v will be applied to v usb 3 v 3 and v dd , with the core voltage regulator enabled. ? this is a full-speed application that uses one interrupt in endpoint that can send one packet of 64 bytes every 1 ms, with no restrictions on the values of the bytes being sent. the application may or may not have addi- tional traffic on out endpoints. ? a regular usb ?b? or ?mini-b? connector will be used on the application circuit board. in this case, p zero = 100% = 1, because there should be no restriction on the value of the data moving through the in endpoint. all 64 kbps of data could potentially be bytes of value, 00h. since ? 0 ? bits cause toggling of the output state of the transceiver, they cause the usb transceiver to consume extra current charging/discharging the cable. in this case, 100% of the data bits sent can be of value ? 0 ?. this should be considered the ?max? value, as normal data will consist of a fair mix of ones and zeros. this application uses 64 kbps for in traffic out of the total bus bandwidth of 1.5 mbps (12 mbps), therefore: since a regular ?b? or ?mini-b? connector is used in this application, the end user may plug in any type of cable up to the maximum allowed 5 m length. therefore, we use the worst-case length: l cable = 5 meters assume i pullup = 2.2 ma. the actual value of i pullup will likely be closer to 218 ? a, but allow for the worst-case. usb bandwidth is shared between all the devices which are plugged into the root port (via hubs). if the application is plugged into a usb 1.1 hub that has other devices plugged into it, your device may see host to device traffic on the bus, even if it is not addressed to your device. since any traffic, regardless of source, can increase the i pullup current above the base 218 ? a, it is safest to allow for the worst-case of 2.2 ma. therefore: the calculated value should be considered an approximation and additional guardband or application-specific prod- uct testing is recommended. the transceiver current is ?in addition to? the rest of the current consumed by the pic18f2x/45k50 device that is needed to run the core, drive the other i/o lines, power the various modules, etc. pin = 64 kbps 1.5 mbps = 4.3% = 0.043 i xcvr = + 2.2 ma = 4.8 ma (60 ma ? 3.3v ? 1 ? 0.043 ? 5m) (3.3v ? 5m) www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 375 pic18(l)f2x/45k50 24.7 oscillator the usb module has specific clock requirements. for full-speed operation, the clock source must be 48 mhz. even so, the microcontroller core and other peripherals are not required to run at that clock speed. available clocking options are described in detail in section 3.14 ?oscillator settings for usb? . 24.8 interrupt-on-change for d+/d- pins the pic18(l)f2x/45k50 has interrupt-on-change functionality on both d+ and d- data pins. this feature allows the device to detect voltage level changes when first connected to a usb host/hub. the usb host/hub has 15k pull-down resistors on the d+ and d- pins. when the pic18(l)f2x/45k50 attaches to the bus the d+ and d- pins can detect voltage changes. external resistors are needed for each pin to maintain a high state on the pins when detached. the usb module must be disabled (usben = 0 ) for the interrupt-on-change to function. enabling the usb module (usben = 1 ) will automatically disable the interrupt-on-change for d+ and d- pins. refer to section 11.3.2 ?interrupt-on-change? and section 11.4.2 ?interrupt-on-change? for more details. 24.9 usb firmware and drivers microchip provides a number of application-specific resources, such as usb firmware and driver support. refer to www.microchip.com for the latest firmware and driver support. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 376 ? 2012 microchip technology inc. table 24-4: registers associat ed with usb module operation (1) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie/gieh peie/giel tmr0ie int0ie iocie tmr0if int0if iocif 120 ipr3 ? ? ? ? ctmuip usbip tmr3gip tmr1gip 131 pir3 ? ? ? ? ctmuif usbif tmr3gif tmr1gif 125 pie3 ? ? ? ? ctmuie usbie tmr3gie tmr1gie 128 ucon ? ppbrst se0 pktdis usben resume suspnd ? 353 ucfg uteye uoemon ? upuen utrdis fsen ppb<1:0>1 355 ustat ? endp<3:0> dir ppbi ? 357 uaddr ? addr<6:0> 359 ufrml frm<7:0> 352 ufrmh ? ? ? ? ? frm<10:8> 352 uir ? sofif stallif idleif trnif actvif uerrif urstif 367 uie ? sofie stallie idleie trnie actvie uerrie urstie 369 ueir btsef ? ? btoef dfn8ef crc16ef crc5ef pidef 370 ueie btsee ? ? btoee dfn8ee crc16ee crc5ee pidee 371 uep0 ? ? ? ephshk epcondis epouten epinen epstall 358 uep1 ? ? ? ephshk epcondis epouten epinen epstall 358 uep2 ? ? ? ephshk epcondis epouten epinen epstall 358 uep3 ? ? ? ephshk epcondis epouten epinen epstall 358 uep4 ? ? ? ephshk epcondis epouten epinen epstall 358 uep5 ? ? ? ephshk epcondis epouten epinen epstall 358 uep6 ? ? ? ephshk epcondis epouten epinen epstall 358 uep7 ? ? ? ephshk epcondis epouten epinen epstall 358 uep8 ? ? ? ephshk epcondis epouten epinen epstall 358 uep9 ? ? ? ephshk epcondis epouten epinen epstall 358 uep10 ? ? ? ephshk epcondis epouten epinen epstall 358 uep11 ? ? ? ephshk epcondis epouten epinen epstall 358 uep12 ? ? ? ephshk epcondis epouten epinen epstall 358 uep13 ? ? ? ephshk epcondis epouten epinen epstall 358 uep14 ? ? ? ephshk epcondis epouten epinen epstall 358 uep15 ? ? ? ephshk epcondis epouten epinen epstall 358 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the usb module. note 1: this table includes only those hardware mapped sfrs locate d in bank 15 of the data memory space. the buffer descriptor registers, which are mapped into bank 4 and are not true sfrs, are listed separately in table 24-3 . www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 377 pic18(l)f2x/45k50 24.10 overview of usb this section presents some of the basic usb concepts and useful information necessary to design a usb device. although much information is provided in this section, there is a plethora of information provided within the usb specifications and class specifications. thus, the reader is encouraged to refer to the usb specifications for more information (www.usb.org). if you are very familiar with the details of usb, then this section serves as a basic, high-level refresher of usb. 24.10.1 layered framework usb device functionality is structured into a layered framework graphically shown in figure 24-12 . each level is associated with a functional level within the device. the highest layer, other than the device, is the configuration. a device may have multiple configura- tions. for example, a particular device may have multiple power requirements based on self-power only or bus power only modes. for each configuration, there may be multiple interfaces. each interface could support a particular mode of that configuration. below the interface is the endpoint(s). data is directly moved at this level. there can be as many as 16 bidirectional endpoints. endpoint 0 is always a control endpoint and by default, when the device is on the bus, endpoint 0 must be available to configure the device. 24.10.2 frames information communicated on the bus is grouped into 1 ms time slots, referred to as frames. each frame can contain many transactions to various devices and endpoints. figure 24-8 shows an example of a transaction within a frame. 24.10.3 transfers there are four transfer types defined in the usb specification. ? isochronous: this type provides a transfer method for large amounts of data (up to 1023 bytes) with timely delivery ensured; however, the data integrity is not ensured. this is good for streaming applications where small data loss is not critical, such as audio. ? bulk: this type of transfer method allows for large amounts of data to be transferred with ensured data integrity; however, the delivery timeliness is not ensured. ? interrupt: this type of transfer provides for ensured timely delivery for small blocks of data, plus data integrity is ensured. ? control: this type provides for device setup control. while full-speed devices support all transfer types, low-speed devices are limited to interrupt and control transfers only. 24.10.4 power power is available from the universal serial bus. the usb specification defines the bus power requirements. devices may either be self-powered or bus powered. self-powered devices draw power from an external source, while bus powered devices use power supplied from the bus. figure 24-12: usb layers device configuration interface endpoint interface endpoint endpoint endpoint endpoint to other configurations (if any) to other interfaces (if any) www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 378 ? 2012 microchip technology inc. the usb specification limits the power taken from the bus. each device is ensured 100 ma at approximately 5v (one unit load). additional power may be requested, up to a maximum of 500 ma. note that power above one unit load is a request and the host or hub is not obligated to provide the extra current. thus, a device capable of consuming more than one unit load must be able to maintain a low-power configuration of a one unit load or less, if necessary. the usb specification also defines a suspend mode. in this situation, current must be limited to 500 ? a, averaged over 1 second. a device must enter a suspend state after 3 ms of inactivity (i.e., no sof tokens for 3 ms). a device entering suspend mode must drop current consumption within 10 ms after suspend. likewise, when signaling a wake-up, the device must signal a wake-up within 10 ms of drawing current above the suspend limit. 24.10.5 enumeration when the device is initially attached to the bus, the host enters an enumeration process in an attempt to identify the device. essentially, the host interrogates the device, gathering information such as power consumption, data rates and sizes, protocol and other descriptive information; descriptors contain this information. a typical enumeration process would be as follows: 1. usb reset: reset the device. thus, the device is not configured and does not have an address (address 0). 2. get device descriptor: the host requests a small portion of the device descriptor. 3. usb reset: reset the device again. 4. set address: the host assigns an address to the device. 5. get device descriptor: the host retrieves the device descriptor, gathering info such as manufacturer, type of device, maximum control packet size. 6. get configuration descriptors. 7. get any other descriptors. 8. set a configuration. the exact enumeration process depends on the host. 24.10.6 descriptors there are eight different standard descriptor types of which five are most important for this device. 24.10.6.1 device descriptor the device descriptor provides general information, such as manufacturer, product number, serial number, the class of the device and the number of configurations. there is only one device descriptor. 24.10.6.2 configuration descriptor the configuration descriptor provides information on the power requirements of the device and how many different interfaces are supported when in this configu- ration. there may be more than one configuration for a device (i.e., low-power and high-power configurations). 24.10.6.3 interface descriptor the interface descriptor details the number of end- points used in this interface, as well as the class of the interface. there may be more than one interface for a configuration. 24.10.6.4 endpoint descriptor the endpoint descriptor identifies the transfer type ( section 24.10.3 ?transfers? ) and direction, as well as some other specifics for the endpoint. there may be many endpoints in a device and endpoints may be shared in different configurations. 24.10.6.5 string descriptor many of the previous descriptors reference one or more string descriptors. string descriptors provide human readable information about the layer ( section 24.10.1 ?layered framework? ) they describe. often these strings show up in the host to help the user identify the device. string descriptors are generally optional to save memory and are encoded in a unicode format. 24.10.7 bus speed each usb device must indicate its bus presence and speed to the host. this is accomplished through a 1.5 k ? resistor which is connected to the bus at the time of the attachment event. depending on the speed of the device, the resistor either pulls up the d+ or d- line to 3.3v. for a low-speed device, the pull-up resistor is connected to the d- line. for a full-speed device, the pull-up resistor is connected to the d+ line. 24.10.8 class specifications and drivers usb specifications include class specifications which operating system vendors optionally support. examples of classes include audio, mass storage, communications and human interface (hid). in most cases, a driver is required at the host side to ?talk? to the usb device. in custom applications, a driver may need to be developed. fortunately, drivers are available for most common host systems for the most common classes of devices. thus, these drivers can be reused. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 379 pic18(l)f2x/45k50 25.0 high/low-voltage detect (hlvd) the pic18(l)f2x/45k50 devices have a high/low- voltage detect module (hlvd). this is a programmable circuit that sets both a device voltage trip point and the direction of change from that point. if the device experiences an excursion past the trip point in that direction, an interrupt flag is set. if the interrupt is enabled, the program execution branches to the interrupt vector address and the software responds to the interrupt. the high/low-voltage detect control register ( register 25-1 ) completely controls the operation of the hlvd module. this allows the circuitry to be ?turned off? by the user under software control, which minimizes the current consumption for the device. the module?s block diagram is shown in figure 25-1 . 25.1 register ? hlvd control register 25-1: hlvdcon: high/low-v oltage detect control register r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-1 vdirmag bgvst irvst hlvden hlvdl<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 vdirmag: voltage direction magnitude select bit 1 = event occurs when voltage equals or exceeds trip point (hlvdl<3:0>) 0 = event occurs when voltage equals or falls below trip point (hlvdl<3:0>) bit 6 bgvst: band gap reference voltages stable status flag bit 1 = internal band gap voltage references are stable 0 = internal band gap voltage reference is not stable bit 5 irvst: internal reference voltage stable flag bit 1 = indicates that the voltage detect logic will generate the interrupt flag at the specified voltage range 0 = indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage range and the hlvd interrupt should not be enabled bit 4 hlvden: high/low-voltage detect power enable bit 1 = hlvd enabled 0 = hlvd disabled bit 3-0 hlvdl<3:0>: voltage detection level bits (1) 1111 = external analog input is used (input comes from the hlvdin pin) 1110 = maximum setting . . . 0000 = minimum setting note 1: see table 29-5 for specifications. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 380 ? 2012 microchip technology inc. the module is enabled by setting the hlvden bit (hlvdcon<4>). each time the hlvd module is enabled, the circuitry requires some time to stabilize. the irvst bit (hlvdcon<5>) is a read-only bit used to indicate when the circuit is stable. the module can only generate an interrupt after the circuit is stable and irvst is set. the vdirmag bit (hlvdcon<7>) determines the overall operation of the module. when vdirmag is cleared, the module monitors for drops in v dd below a predetermined set point. when the bit is set, the module monitors for rises in v dd above the set point. 25.2 operation when the hlvd module is enabled, a comparator uses an internally generated reference voltage as the set point. the set point is compared with the trip point, where each node in the resistor divider represents a trip point voltage. the ?trip point? voltage is the voltage level at which the device detects a high or low-voltage event, depending on the configuration of the module. when the supply voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to the internal reference voltage generated by the voltage reference module. the comparator then generates an interrupt signal by setting the hlvdif bit. the trip point voltage is software programmable to any of 16 values. the trip point is selected by programming the hlvdl<3:0> bits (hlvdcon<3:0>). the hlvd module has an additional feature that allows the user to supply the trip voltage to the module from an external source. this mode is enabled when bits, hlvdl<3:0>, are set to ? 1111 ?. in this state, the comparator input is multiplexed from the external input pin, hlvdin. this gives users the flexibility of configur- ing the high/low-voltage detect interrupt to occur at any voltage in the valid operating range. figure 25-1: hlvd mo dule block diagram (with external input) set v dd 16-to-1 mux hlvden hlvdcon hlvdl<3:0> register hlvdin v dd externally generated trip point hlvdif hlvden boren internal voltage reference vdirmag 1.024v typical www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 381 pic18(l)f2x/45k50 25.3 hlvd setup to set up the hlvd module: 1. select the desired hlvd trip point by writing the value to the hlvdl<3:0> bits. 2. set the vdirmag bit to detect high voltage (vdirmag = 1 ) or low voltage (vdirmag = 0 ). 3. enable the hlvd module by setting the hlvden bit. 4. clear the hlvd interrupt flag (pir2<2>), which may have been set from a previous interrupt. 5. if interrupts are desired, enable the hlvd interrupt by setting the hlvdie and gie/gieh bits (pie2<2> and intcon<7>, respectively). an interrupt will not be generated until the irvst bit is set. 25.4 current consumption when the module is enabled, the hlvd comparator and voltage divider are enabled and consume static current. the total current consumption, when enabled, is specified in section 29.0 ?electrical characteris- tics? . depending on the application, the hlvd module does not need to operate constantly. to reduce current requirements, the hlvd circuitry may only need to be enabled for short periods where the voltage is checked. after such a check, the module could be disabled. 25.5 hlvd start-up time the internal reference voltage of the hlvd module, specified in section 29.0 ?electrical characteristics? , may be used by other internal circuitry, such as the programmable brown-out reset. if the hlvd or other circuits using the voltage reference are disabled to lower the device?s current consumption, the reference voltage circuit will require time to become stable before a low or high-voltage condition can be reliably detected. this start-up time, t irvst , is an interval that is independent of device clock speed. the hlvd interrupt flag is not enabled until t irvst has expired and a stable reference voltage is reached. for this reason, brief excursions beyond the set point may not be detected during this interval (see figure 25-2 or figure 25-3 ). figure 25-2: low-voltage detect operation (vdirmag = 0 ) note: before changing any module settings (v dirmag , hlvdl<3:0>), first disable the module (hlvden = 0 ), make the changes and re-enable the module. this prevents the generation of false hlvd events. v hlvd v dd hlvdif v hlvd v dd enable hlvd t irvst hlvdif may not be set enable hlvd hlvdif hlvdif cleared in software hlvdif cleared in software hlvdif cleared in software, case 1: case 2: hlvdif remains set since hlvd condition still exists t irvst internal reference is stable internal reference is stable irvst irvst www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 382 ? 2012 microchip technology inc. figure 25-3: high-voltage detect operation (vdirmag = 1 ) 25.6 applications in many applications, it is desirable to detect a drop below, or rise above, a particular voltage threshold. for example, the hlvd module could be periodically enabled to detect universal serial bus (usb) attach or detach. this assumes the device is powered by a lower voltage source than the usb when detached. an attach would indicate a high-voltage detect from, for example, 3.3v to 5v (the voltage on usb) and vice versa for a detach. this feature could save a design a few extra components and an attach signal (input pin). for general battery applications, figure 25-4 shows a possible voltage curve. over time, the device voltage decreases. when the device voltage reaches voltage v a , the hlvd logic generates an interrupt at time, t a . the interrupt could cause the execution of an isr, which would allow the application to perform ?house- keeping tasks? and a controlled shutdown before the device voltage exits the valid operating range at t b . this would give the application a time window, represented by the difference between t a and t b , to safely exit. figure 25-4: typical low-voltage detect application v hlvd v dd hlvdif v hlvd v dd enable hlvd t irvst hlvdif may not be set enable hlvd hlvdif hlvdif cleared in software hlvdif cleared in software hlvdif cleared in software, case 1: case 2: hlvdif remains set since hlvd condition still exists t irvst irvst internal reference is stable internal reference is stable irvst time voltage v a v b t a t b v a = hlvd trip point v b = minimum valid device operating voltage legend: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 383 pic18(l)f2x/45k50 25.7 operation during sleep when enabled, the hlvd circuitry continues to operate during sleep. if the device voltage crosses the trip point, the hlvdif bit will be set and the device will wake-up from sleep. device execution will continue from the interrupt vector address if interrupts have been globally enabled. 25.8 effects of a reset a device reset forces all registers to their reset state. this forces the hlvd module to be turned off. table 25-1: registers associated wi th high/low-voltage detect module name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page hlvdcon vdirmag bgvst irvst hlvden hlvdl<3:0> 379 intcon gie/gieh peie/giel tmr0ie int0ie iocie tmr0if int0if iocif 120 ipr2 oscfip c1ip c2ip eeip bclip hlvdip tmr3ip ccp2ip 130 pie2 oscfie c1ie c2ie eeie bclie hlvdie tmr3ie ccp2ie 127 pir2 oscfif c1if c2if eeif bclif hlvdif tmr3if ccp2if 124 trisa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 156 legend: ? = unimplemented locations, read as ? 0 ?. shaded bits are unused by the hlvd module. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 384 ? 2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 385 pic18(l)f2x/45k50 26.0 special features of the cpu pic18(l)f2x/45k50 devices include several features intended to maximize reliability and minimize cost through elimination of external components. these are: ? oscillator selection ? resets: - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) ? interrupts ? watchdog timer (wdt) ? code protection ? id locations ? in-circuit serial programming? the oscillator can be configured for the application depending on frequency, power, accuracy and cost. all of the options are discussed in detail in section 3.0 ?oscillator module (with fail-safe clock monitor)? . a complete discussion of device resets and interrupts is available in previous sections of this data sheet. in addition to their power-up and oscillator start-up timers provided for resets, pic18(l)f2x/45k50 devices have a watchdog timer, which is either permanently enabled via the configuration bits or software controlled (if configured as disabled). the inclusion of an internal rc oscillator also provides the additional benefits of a fail-safe clock monitor (fscm) and two-speed start-up. fscm provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure. two- speed start-up enables code to be executed almost immediately on start-up, while the primary clock source completes its start-up delays. all of these features are enabled and configured by setting the appropriate configuration register bits. 26.1 configuration bits the configuration bits can be programmed (read as ? 0 ?) or left unprogrammed (read as ? 1 ?) to select various device configurations. these bits are mapped starting at program memory location 300000h. the user will note that address 300000h is beyond the user program memory space. in fact, it belongs to the configuration memory space (300000h-3fffffh), which can only be accessed using table reads and table writes. programming the configuration registers is done in a manner similar to programming the flash memory. the wr bit in the eecon1 register starts a self-timed write to the configuration register. in normal operation mode, a tblwt instruction with the tblptr pointing to the configuration register sets up the address and the data for the configuration register write. setting the wr bit starts a long write to the configuration register. the configuration registers are written a byte at a time. to write or erase a configuration cell, a tblwt instruction can write a ? 1 ? or a ? 0 ? into the cell. for additional details on flash programming, refer to section 7.6 ?writing to flash program memory? . www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 386 ? 2012 microchip technology inc. table 26-1: configuration bits and device ids address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default/ unprogrammed value 300000h config1l ? ? ls48mhz cpudiv<1:0> ? cfgpllen pllsel 0000 0000 300001h config1h ieso fcmen pclken ? fosc<3:0> 0010 0101 300002h config2l ? lpbor ? borv<1:0> boren<1:0> pwrten 0101 1111 300003h config2h ? ? wdtps<3:0> wdten<1:0> 0011 1111 300004h config3l ? ? ? ? ? ? ? ? 0000 0000 300005h config3h mclre sdomx ?t3cmx ? ? pbaden ccp2mx 1101 0011 300006h config4l debug xinst icprt (5) ? ?lvp (1) ? strven 1010 0101 300007h config4h ? ? ? ? ? ? ? ? 1111 1111 300008h config5l ? ? ? ?cp3 (2) cp2 (2) cp1 cp0 0000 1111 300009h config5h cpd cpb ? ? ? ? ? ? 1100 0000 30000ah config6l ? ? ? ?wrt3 (2) wrt2 (2) wrt1 wrt0 0000 1111 30000bh config6h wrtd wrtb wrtc (3) ? ? ? ? ? 1110 0000 30000ch config7l ? ? ? ?ebtr3 (2) ebtr2 (2) ebtr1 ebtr0 0000 1111 30000dh config7h ?ebtrb ? ? ? ? ? ? 0100 0000 3ffffeh devid1 (4) dev<2:0> rev<4:0> qqqq qqqq 3fffffh devid2 (4) dev<10:3> 0101 1100 legend: ? = unimplemented, q = value depends on conditi on. shaded bits are unimplemented, read as ? 0 ?. note 1: can only be changed when in high voltage programming mode. 2: available on pic18(l)f45k50 and pic18(l)f25k50 devices only. 3: in user mode, this bit is read-only and cannot be self-programmed. 4: see register 26-13 and register 26-14 for devid values. devid registers are read-only and cannot be programmed by the user. 5: available only on 44-pin tqfp package devices. program this bit clear on all other devices. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 387 pic18(l)f2x/45k50 26.2 register definitions: configuration word register 26-1: config1l: co nfiguration register 1 low u-0 u-0 r/p-0 r/p-0 r/p-0 u-0 r/p-0 r/p-0 ? ? ls48mhz cpudiv<1:0> ? cfgpllen pllsel bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5 ls48mhz: usb low-speed clock selection bit selects the clock source for low-speed usb operation 1 = system clock is expected at 48 mhz, fs/ls usb clock divide-by is set to 8 0 = system clock is expected at 24 mhz, fs/ls usb clock divide-by is set to 4 bit 4-3 cpudiv<1:0>: cpu system clock selection bits 11 = cpu system clock divided by 6 10 = cpu system clock divided by 3 01 = cpu system clock divided by 2 00 = no cpu system clock divide bit 2 unimplemented: read as ? 0 ? bit 1 cfgpllen: pll enable bit (1) 1 = oscillator multiplied by 3 or 4, depending on the pllsel bit 0 = oscillator used directly bit 0 pllsel: pll multiplier selection bit 1 = output frequency is 3x the input frequency 0 = output frequency is 4x the input frequency note 1: see table 3-1 for conditions under which the cfgpllen fuse is available. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 388 ? 2012 microchip technology inc. register 26-2: config1h: co nfiguration register 1 high r/p-0 r/p-0 r/p-1 u-0 r/p-0 r/p-1 r/p-0 r/p-1 ieso fcmen pclken ? fosc<3:0> bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed x = bit is unknown bit 7 ieso (1) : internal/external oscillator switchover bit 1 = oscillator switchover mode enabled 0 = oscillator switchover mode disabled bit 6 fcmen (1) : fail-safe clock monitor enable bit 1 = fail-safe clock monitor enabled 0 = fail-safe clock monitor disabled bit 5 pclken: primary clock enable bit 1 = primary clock is always enabled 0 = primary clock can be disabled by software bit 4 unimplemented: read as ? 0 ? bit 3-0 fosc<3:0>: oscillator selection bits 1111 = reserved 1110 = reserved 1101 = ec oscillator (low power, <4 mhz) 1100 = ec oscillator, clko function on osc2 (low power, <4 mhz) 1011 = ec oscillator (medium power, 4 mhz - 16 mhz) 1010 = ec oscillator, clko function on osc2 (medium power, 4 mhz - 16 mhz) 1001 = internal oscillator block, clko function on osc2 1000 = internal oscillator block 0111 = external rc oscillator 0110 = external rc oscillator, clko function on osc2 0101 = ec oscillator (high power, 16 mhz - 48 mhz) 0100 = ec oscillator, clko function on osc2 (high power, 16 mhz - 48 mhz) 0011 = hs oscillator (medium power, 4 mhz - 16 mhz) 0010 = hs oscillator (high power, 16 mhz - 25 mhz) 0001 = xt oscillator 0000 = lp oscillator note 1: when fosc<3:0> is configured for hs, xt, or lp oscillator and fcmen bit is set, then the ieso bit should also be set to prevent a false failed clock indication and to enable automatic clock switch over from the internal oscillator block to the external oscillator when the ost times out. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 389 pic18(l)f2x/45k50 register 26-3: config2l: co nfiguration register 2 low u-0 r/p-1 u-0 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 ? lpbor ? borv<1:0> (1) boren<1:0> (2) pwrten (2) bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed x = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6 lpbor : low-power brown-out reset enable bits 1 = low-power brown-out reset disabled 0 = low-power brown-out reset enabled bit 5 unimplemented: read as ? 0 ? bit 4-3 borv<1:0>: brown-out reset voltage bits (1) 11 = v bor set to 1.9v nominal 10 = v bor set to 2.2v nominal 01 = v bor set to 2.5v nominal 00 = v bor set to 2.85v nominal bit 2-1 boren<1:0>: brown-out reset enable bits (2) 11 = brown-out reset enabled in hardware only (sboren is disabled) 10 = brown-out reset enabled in hardware only and disabled in sleep mode (sboren is disabled) 01 = brown-out reset enabled and controlled by software (sboren is enabled) 00 = brown-out reset disabled in hardware and software bit 0 pwrten : power-up timer enable bit (2) 1 = pwrt disabled 0 = pwrt enabled note 1: see section 29.1 ?dc characteristics: supply voltage, pic18(l)f2x/45k50? for specifications. 2: the power-up timer is decoupled from brown-out reset, allowing these features to be independently controlled. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 390 ? 2012 microchip technology inc. register 26-4: config2h: co nfiguration register 2 high u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 ? ? wdtps<3:0> wdten<1:0> bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5-2 wdtps<3:0>: watchdog timer postscale select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 bit 1-0 wdten<1:0>: watchdog timer enable bits 11 = wdt enabled in hardware; swdten bit disabled 10 = wdt controlled by the swdten bit 01 = wdt enabled when device is active, disabled when device is in sleep; swdten bit disabled 00 = wdt disabled in hardware; swdten bit disabled www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 391 pic18(l)f2x/45k50 register 26-5: config3h: co nfiguration register 3 high r/p-1 r/p-1 u-0 r/p-1 u-0 u-0 r/p-1 r/p-1 mclre sdomx ? t3cmx ? ? pbaden ccp2mx bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed x = bit is unknown bit 7 mclre: mclr pin enable bit 1 = mclr pin enabled; re3 input pin disabled 0 = re3 input pin enabled; mclr disabled bit 6 sdomx: sdo output mux bit 1 = sdo is on rb3 0 = sdo is on rc7 bit 5 unimplemented: read as ? 0 ? bit 4 t3cmx: timer3 clock input mux bit 1 = t3cki is on rc0 0 = t3cki is on rb5 bit 3-2 unimplemented: read as ? 0 ? bit 1 pbaden: portb a/d enable bit 1 = anselb<5:0> resets to 1 , portb<5:0> pins are configured as analog inputs on reset 0 = anselb<5:0> resets to 0 , portb<4:0> pins are configured as digital i/o on reset bit 0 ccp2mx: ccp2 mux bit 1 = ccp2 input/output is multiplexed with rc1 0 = ccp2 input/output is multiplexed with rb3 www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 392 ? 2012 microchip technology inc. register 26-6: config4l: co nfiguration register 4 low r/p-1 r/p-0 r/p-1 u-0 u-0 r/p-1 u-0 r/p-1 debug (2) xinst icprt (3) ? ?lvp (1) ?stvren bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is un programmed x = bit is unknown bit 7 debug : background debugger enable bit (2) 1 = background debugger disabled, rb6 and rb7 configured as general purpose i/o pins 0 = background debugger enabled, rb6 and rb7 ar e dedicated to in-circuit debug bit 6 xinst: extended instruction set enable bit 1 = instruction set extension and indexed addressing mode enabled 0 = instruction set extension and index ed addressing mode disabled (legacy mode) bit 5 icprt: dedicated in-circuit (icd) port enable bit (3) 1 = icport enabled (icd function on dedicated icd pins) 0 = icport disabled (icd function on default icd pins, rb6/7) bit 4-3 unimplemented: read as ? 0 ? bit 2 lvp: single-supply icsp enable bit 1 = single-supply icsp enabled 0 = single-supply icsp disabled bit 1 unimplemented: read as ? 0 ? bit 0 stvren: stack full/underflow reset enable bit 1 = stack full/underflow will cause reset 0 = stack full/underflow will not cause reset note 1: can only be changed by a programmer in high-voltage programming mode. 2: the debug bit is managed automatically by device developm ent tools including debuggers and programmers. for normal device operations, this bi t should be maintained as a ? 1 ?. 3: available only on 44-pin tqfp package devices. program this bit clear on all other devices. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 393 pic18(l)f2x/45k50 register 26-7: config5l: co nfiguration register 5 low u-0 u-0 u-0 u-0 r/c-1 r/c-1 r/c-1 r/c-1 ? ? ? ?cp3 (1) cp2 (1) cp1 cp0 bit 7 bit 0 legend: r = readable bit u = unimplemented bit, read as ?0? -n = value when device is unpr ogrammed c = clearable only bit bit 7-4 unimplemented: read as ? 0 ? bit 3 cp3: code protection bit (1) 1 = block 3 not code-protected 0 = block 3 code-protected bit 2 cp2: code protection bit (1) 1 = block 2 not code-protected 0 = block 2 code-protected bit 1 cp1: code protection bit 1 = block 1 not code-protected 0 = block 1 code-protected bit 0 cp0: code protection bit 1 = block 0 not code-protected 0 = block 0 code-protected note 1: available on pic18(l)f45k 50 and pic18(l)f25k50 devices. register 26-8: config5h: co nfiguration register 5 high r/c-1 r/c-1 u-0 u-0 u-0 u-0 u-0 u-0 cpd cpb ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed c = clearable only bit bit 7 cpd: data eeprom code protection bit 1 = data eeprom not code-protected 0 = data eeprom code-protected bit 6 cpb: boot block code protection bit 1 = boot block not code-protected 0 = boot block code-protected bit 5-0 unimplemented: read as ? 0 ? www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 394 ? 2012 microchip technology inc. register 26-9: config6l: co nfiguration register 6 low u-0 u-0 u-0 u-0 r/c-1 r/c-1 r/c-1 r/c-1 ? ? ? ?wrt3 (1) wrt2 (1) wrt1 wrt0 bit 7 bit 0 legend: r = readable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed c = clearable only bit bit 7-4 unimplemented: read as ? 0 ? bit 3 wrt3: write protection bit (1) 1 = block 3 not write-protected 0 = block 3 write-protected bit 2 wrt2: write protection bit (1) 1 = block 2 not write-protected 0 = block 2 write-protected bit 1 wrt1: write protection bit 1 = block 1 not write-protected 0 = block 1 write-protected bit 0 wrt0: write protection bit 1 = block 0 not write-protected 0 = block 0 write-protected note 1: available on pic18(l)f45k50 and pic18(l)f25k50 devices. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 395 pic18(l)f2x/45k50 register 26-10: config6h: co nfiguration register 6 high r/c-1 r/c-1 r/c-1 u-0 u-0 u-0 u-0 u-0 wrtd wrtb wrtc (1) ? ? ? ? ? bit 7 bit 0 legend: r = readable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed c = clearable only bit bit 7 wrtd: data eeprom write protection bit 1 = data eeprom not write-protected 0 = data eeprom write-protected bit 6 wrtb: boot block write protection bit 1 = boot block not write-protected 0 = boot block write-protected bit 5 wrtc: configuration register write protection bit (1) 1 = configuration registers not write-protected 0 = configuration registers write-protected bit 4-0 unimplemented: read as ? 0 ? note 1: this bit is read-only in normal execution mode; it can be written only in icsp? mode. register 26-11: config7l: co nfiguration register 7 low u-0 u-0 u-0 u-0 r/c-1 r/c-1 r/c-1 r/c-1 ? ? ? ? ebtr3 (1) ebtr2 (1) ebtr1 ebtr0 bit 7 bit 0 legend: r = readable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed c = clearable only bit bit 7-4 unimplemented: read as ? 0 ? bit 3 ebtr3: table read protection bit (1) 1 = block 3 not protected from table reads executed in other blocks 0 = block 3 protected from table reads executed in other blocks bit 2 ebtr2 : table read protection bit (1) 1 = block 2 not protected from table reads executed in other blocks 0 = block 2 protected from table reads executed in other blocks bit 1 ebtr1: table read protection bit 1 = block 1 not protected from table reads executed in other blocks 0 = block 1 protected from table reads executed in other blocks bit 0 ebtr0: table read protection bit 1 = block 0 not protected from table reads executed in other blocks 0 = block 0 protected from table reads executed in other blocks note 1: available on pic18(l)f45k50 and pic18(l)f25k50 devices. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 396 ? 2012 microchip technology inc. register 26-12: config7h: co nfiguration register 7 high u-0 r/c-1 u-0 u-0 u-0 u-0 u-0 u-0 ? ebtrb ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed c = clearable only bit bit 7 unimplemented: read as ? 0 ? bit 6 ebtrb: boot block table read protection bit 1 = boot block not protected from table reads executed in other blocks 0 = boot block protected from table reads executed in other blocks bit 5-0 unimplemented: read as ? 0 ? register 26-13: devid1: device id register 1 rrrrrrrr dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 bit 7 bit 0 legend: r = readable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed c = clearable only bit bit 7-5 dev<2:0>: device id bits these bits, together with dev<10:3> in devid2, determine the device id. see table 26-2 for complete device id list. bit 4-0 rev<4:0>: revision id bits these bits indicate the device revision. register 26-14: devid2: device id register 2 rrrrrrrr dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 bit 7 bit 0 legend: r = readable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed c = clearable only bit bit 7-0 dev<10:3>: device id bits these bits, together with dev<2:0> in devid1, determine the device id. see table 26-2 for complete device id list. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 397 pic18(l)f2x/45k50 table 26-2: device id table for the pic18(l)f2x/45k50 family dev<10:3> dev<2:0> part number 0101 1100 000 PIC18F45K50 001 pic18f25k50 011 pic18f24k50 100 pic18lf45k50 101 pic18lf25k50 111 pic18lf24k50 www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 398 ? 2012 microchip technology inc. 26.3 watchdog timer (wdt) for pic18(l)f2x/45k50 devices, the wdt is driven by the intrc source. when the wdt is enabled, the clock source is also enabled. the nominal wdt period is 4 ms and has the same stability as the intrc oscillator. the 4 ms period of the wdt is multiplied by a 16-bit postscaler. any output of the wdt postscaler is selected by a multiplexer, controlled by bits in configu- ration register 2h. available periods range from 4 ms to 131.072 seconds (2.18 minutes). the wdt and postscaler are cleared when any of the following events occur: a sleep or clrwdt instruction is executed, the ircf bits of the osccon register are changed or a clock failure has occurred. figure 26-1: wdt block diagram note 1: the clrwdt and sleep instructions clear the wdt and postscaler counts when executed. 2: changing the setting of the ircf bits of the osccon register clears the wdt and postscaler counts. 3: when a clrwdt instruction is executed, the postscaler count will be cleared. intrc source wdt wake-up reset wdt counter programmable postscaler 1:1 to 1:32,768 enable wdt wdtps<3:0> swdten wdten clrwdt 4 from power reset all device resets sleep ? 128 change on ircf bits managed modes www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 399 pic18(l)f2x/45k50 26.3.1 control register register 26-15 shows the wdtcon register. this is a readable and writable register which contains a control bit that allows software to override the wdt enable configuration bit, but only if the configuration bit has disabled the wdt. 26.4 register definitions: wdt control table 26-4: configuration registers associated with watchdog timer register 26-15: wdtcon: wat chdog timer control register u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ?swdten (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-1 unimplemented: read as ? 0 ? bit 0 swdten: software enable or disable the watchdog timer bit (1) 1 = wdt is turned on 0 = wdt is turned off (reset value) note 1: this bit has no effect unless the configuration bit, wdten<1:0>, is set to 10b (swdten enabled). table 26-3: registers associated with watchdog timer name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page rcon ipen sboren ? ri to pd por bor 68 wdtcon ? ? ? ? ? ? ?swdten 399 legend: ? = unimplemented, read as ? 0 ?. shaded bits are not used by the watchdog timer. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page config2h ? ? wdtps<3:0> wdten<1:0> 390 legend: ? = unimplemented, read as ? 0 ?. shaded bits are not used by the watchdog timer. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 400 ? 2012 microchip technology inc. 26.5 program verification and code protection the overall structure of the code protection on the pic18 flash devices differs significantly from other pic ? microcontroller devices. the user program memory is divided into three or five blocks, depending on the device. one of these is a boot block of 0.5k or 2k bytes, depending on the device. the remainder of the memory is divided into individual blocks on binary boundaries. each of the blocks has three code protection bits associated with them. they are: ? code-protect bit (cpn) ? write-protect bit (wrtn) ? external block table read bit (ebtrn) figure 26-2 shows the program memory organization for 16 and 32-kbyte devices and the specific code protection bit associated with each block. the actual locations of the bits are summarized in table 26-5 . figure 26-2: code-protected prog ram memory for pic18(l)f2x/45k50 memory size/device block code protection controlled by: 16 kbytes (pic18(l)f24k50) 32 kbytes (pic18(l)fx5k50) boot block (000h-7ffh) boot block (000h-7ffh) cpb, wrtb, ebtrb block 0 (800h-1fffh) block 0 (800h-1fffh) cp0, wrt0, ebtr0 block 1 (2000h-3fffh) block 1 (2000h-3fffh) cp1, wrt1, ebtr1 unimplemented read ? 0 ?s (4000h-1fffffh) block 2 (4000h-5fffh) cp2, wrt2, ebtr2 block 3 (6000h-7fffh) cp3, wrt3, ebtr3 unimplemented read ? 0 ?s (8000h-1fffffh) (unimplemented memory space) table 26-5: configuration registers associated with code protection file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 300008h config5l ? ? ? ?cp3 (1) cp2 (1) cp1 cp0 300009h config5h cpd cpb ? ? ? ? ? ? 30000ah config6l ? ? ? ?wrt3 (1) wrt2 (1) wrt1 wrt0 30000bh config6h wrtd wrtb wrtc (2) ? ? ? ? ? 30000ch config7l ? ? ? ? ebtr3 (1) ebtr2 (1) ebtr1 ebtr0 30000dh config7h ? ebtrb ? ? ? ? ? ? legend: shaded bits are unimplemented. note 1: available on pic18(l)f45k50 and pic18(l)f25k50 devices only. 2: in user mode, this bit is read-only and cannot be self-programmed. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 401 pic18(l)f2x/45k50 26.5.1 program memory code protection the program memory may be read to or written from any location using the table read and table write instructions. the device id may be read with table reads. the configuration registers may be read and written with the table read and table write instructions. in normal execution mode, the cpn bits have no direct effect. cpn bits inhibit external reads and writes. a block of user memory may be protected from table writes if the wrtn configuration bit is ? 0 ?. the ebtrn bits control table reads. for a block of user memory with the ebtrn bit cleared to ? 0 ?, a table read instruction that executes from within that block is allowed to read. a table read instruction that executes from a location outside of that block is not allowed to read and will result in reading ? 0 ?s. figures 26-3 through 26-5 illustrate table write and table read protection. figure 26-3: table write (wrtn) disallowed note: code protection bits may only be written to a ? 0 ? from a ? 1 ? state. it is not possible to write a ? 1 ? to a bit in the ? 0 ? state. code pro- tection bits are only set to ? 1 ? by a full chip erase or block erase function. the full chip erase and block erase functions can only be initiated via icsp? or an external programmer. 000000h 0007ffh 000800h 001fffh 002000h 003fffh 004000h 005fffh 006000h 007fffh wrtb, ebtrb = 11 wrt0, ebtr0 = 01 wrt1, ebtr1 = 11 wrt2, ebtr2 = 11 wrt3, ebtr3 = 11 tblwt* tblptr = 0008ffh pc = 001ffeh tblwt* pc = 005ffeh register values program memory configuration bit settings results: all table writes disabled to blockn whenever wrtn = 0 . www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 402 ? 2012 microchip technology inc. figure 26-4: external block table read (ebtrn) disallowed figure 26-5: internal block table read (ebtrn) allowed wrtb, ebtrb = 11 wrt0, ebtr0 = 10 wrt1, ebtr1 = 11 wrt2, ebtr2 = 11 wrt3, ebtr3 = 11 tblrd* tblptr = 0008ffh pc = 003ffeh results: all table reads from external blocks to blockn are disabled whenever ebtrn = 0 . tablat register returns a value of ? 0 ?. register values program memory configuration bit settings 000000h 0007ffh 000800h 001fffh 002000h 003fffh 004000h 005fffh 006000h 007fffh wrtb, ebtrb = 11 wrt0, ebtr0 = 10 wrt1, ebtr1 = 11 wrt2, ebtr2 = 11 wrt3, ebtr3 = 11 tblrd* tblptr = 0008ffh pc = 001ffeh register values program memory configuration bit settings results: table reads permitted within blockn, even when ebtrbn = 0 . tablat register returns the value of the data at the location tblptr. 000000h 0007ffh 000800h 001fffh 002000h 003fffh 004000h 005fffh 006000h 007fffh www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 403 pic18(l)f2x/45k50 26.5.2 data eeprom code protection the entire data eeprom is protected from external reads and writes by two bits: cpd and wrtd. cpd inhibits external reads and writes of data eeprom. wrtd inhibits internal and external writes to data eeprom. the cpu can always read data eeprom under normal operation, regardless of the protection bit settings. 26.5.3 configuration register protection the configuration registers can be write-protected. the wrtc bit controls protection of the configuration registers. in normal execution mode, the wrtc bit is readable only. wrtc can only be written via icsp or an external programmer. 26.6 id locations eight memory locations (200000h-200007h) are designated as id locations, where the user can store checksum or other code identification numbers. these locations are both readable and writable during normal execution through the tblrd and tblwt instructions or during program/verify. the id locations can be read when the device is code-protected. 26.7 in-circuit serial programming pic18(l)f2x/45k50 devices can be serially programmed while in the end application circuit. this is simply done with two lines for clock and data and three other lines for power, ground and the programming voltage. this allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. 26.8 in-circuit debugger when the debug configuration bit is programmed to a ? 0 ?, the in-circuit debugger functionality is enabled. this function allows simple debugging functions when used with mplab ? ide. when the microcontroller has this feature enabled, some resources are not available for general use. table 26-6 shows which resources are required by the background debugger. table 26-6: debugger resources to use the in-circuit debugger function of the microcontroller, the design must implement in-circuit serial programming connections to the following pins: ?mclr /v pp /re3 ?v dd ?v ss ?rb7 ?rb6 this will interface to the in-circuit debugger module available from microchip or one of the third party development tool companies. 26.9 special icport features (44-pin tqfp package only) under specific circumstances, the no connect (nc) pins of devices in 44-pin tqfp packages can provide additional functionality. these features are controlled by device configuration bits and are available only in this package type and pin count. 26.9.1 dedicated icd/icsp port the 44-pin tqfp devices can use nc pins to provide an alternate port for in-circuit debugging (icd) and in- circuit serial programming (icsp). these pins are col- lectively known as the dedicated icsp/icd port, since they are not shared with any other function of the device. when implemented, the dedicated port activates three nc pins to provide an alternate device reset, data and clock ports. none of these ports overlap with standard i/o pins, making the i/o pins available to the user?s application. the dedicated icsp/icd port is enabled by setting the icprt configuration bit. the port functions the same way as the legacy icsp/icd port on rb6/rb7. table 26-7 identifies the functionally equivalent pins for icsp and icd purposes. table 26-7: equivalent pins for legacy and dedicated icd/icsp? ports i/o pins: rb6, rb7 pin name pin type pin function legacy port dedicated port mclr /v pp / re3 nc/icrst / icv pp p device reset and programming enable rb6/iocb6/ pgc nc/icck/ icpgc i serial clock rb7/iocb7/ pgd nc/icdt/ icpgd i/o serial data legend: i = input, o = output, p = power www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 404 ? 2012 microchip technology inc. 26.10 single-supply icsp programming the lvp configuration bit enables single-supply icsp programming (formerly known as low-voltage icsp programming or lvp). when single-supply program- ming is enabled, the microcontroller can be programmed without requiring high voltage being applied to the mclr /v pp /re3 pin. see ? pic18(l)f2x/4xk50 flash memory programming specification ? (ds41630) for more details about low voltage programming. the lvp bit may be set or cleared only when using standard high-voltage programming (v ihh applied to the mclr /v pp /re3 pin). once lvp has been disabled, only the standard high-voltage programming is available and must be used to program the device. memory that is not code-protected can be erased using either a block erase, or erased row by row, then written at any specified v dd . if code-protected memory is to be erased, a block erase is required. note 1: high-voltage programming is always available, regardless of the state of the lvp bit, by applying v ihh to the mclr pin. 2: by default, single-supply icsp is enabled in unprogrammed devices (as supplied from microchip) and erased devices. 3: while in low-voltage icsp mode, mclr is always enabled, regardless of the mclre bit, and the re3 pin can no longer be used as a general purpose input. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 405 pic18(l)f2x/45k50 27.0 instruction set summary pic18(l)f2x/45k50 device s incorporate the standard set of 75 pic18 core instructions, as well as an extended set of eight new instructions, for the optimization of code that is recursive or that utilizes a software stack. the extended set is discussed later in this section. 27.1 standard instruction set the standard pic18 instruction set adds many enhancements to the previous pic ? mcu instruction sets, while maintaining an easy migration from these pic ? mcu instruction sets. most instructions are a single program memory word (16 bits), but there are four instructions that require two program memory locations. each single-word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. the instruction set is highly orthogonal and is grouped into four basic categories: ? byte-oriented operations ? bit-oriented operations ? literal operations ? control operations the pic18 instruction set summary in table 27-2 lists byte-oriented , bit-oriented , literal and control operations. table 27-1 shows the opcode field descriptions. most byte-oriented instructions have three operands: 1. the file register (specified by ?f?) 2. the destination of the result (specified by ?d?) 3. the accessed memory (specified by ?a?) the file register designator ?f? specifies which file register is to be used by the instruction. the destination designator ?d? specifies where the result of the opera- tion is to be placed. if ?d? is zero, the result is placed in the wreg register. if ?d? is one, the result is placed in the file register specified in the instruction. all bit-oriented instructions have three operands: 1. the file register (specified by ?f?) 2. the bit in the file register (specified by ?b?) 3. the accessed memory (specified by ?a?) the bit field designator ?b? selects the number of the bit affected by the operation, while the file register designator ?f? represents the number of the file in which the bit is located. the literal instructions may use some of the following operands: ? a literal value to be loaded into a file register (specified by ?k?) ? the desired fsr register to load the literal value into (specified by ?f?) ? no operand required (specified by ???) the control instructions may use some of the following operands: ? a program memory address (specified by ?n?) ? the mode of the call or return instructions (specified by ?s?) ? the mode of the table read and table write instructions (specified by ?m?) ? no operand required (specified by ???) all instructions are a single word, except for four double-word instructions. these instructions were made double-word to contain the required information in 32 bits. in the second word, the 4 msbs are ? 1 ?s. if this second word is executed as an instruction (by itself), it will execute as a nop . all single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruc- tion. in these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a nop . the double-word instructions execute in two instruction cycles. one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 ? s. if a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 ? s. two-word branch instructions (if true) would take 3 ? s. figure 27-1 shows the general formats that the instruc- tions can have. all examples use the convention ?nnh? to represent a hexadecimal number. the instruction set summary, shown in ta bl e 2 7 -2 , lists the standard instructions recognized by the microchip assembler (mpasm tm ). section 27.1.1 ?standard instruction set? provides a description of each instruction. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 406 ? 2012 microchip technology inc. table 27-1: opcode field descriptions field description a ram access bit a = 0 : ram location in access ram (bsr register is ignored) a = 1 : ram bank is specified by bsr register bbb bit address within an 8-bit file register (0 to 7). bsr bank select register. used to select the current ram bank. c, dc, z, ov, n alu status bits: c arry, d igit c arry, z ero, ov erflow, n egative. d destination select bit d = 0 : store result in wreg d = 1 : store result in file register f dest destination: either the wreg register or the specified register file location. f 8-bit register file address (00h to ffh) or 2-bit fsr designator (0h to 3h). f s 12-bit register file address (000h to ff fh). this is the source address. f d 12-bit register file address (000h to fffh). this is the destination address. gie global interrupt enable bit. k literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label label name. mm the mode of the tblptr register for the table read and table write instructions. only used with table read and table write instructions: * no change to register (such as tb lptr with table reads and writes) *+ post-increment register (such as tblptr with table reads and writes) *- post-decrement register (such as tblptr with table reads and writes) +* pre-increment register (such as tblptr with table reads and writes) n the relative address (2?s complement number) for relative branch instructions or the direct address for call / branch and return instructions. pc program counter. pcl program counter low byte. pch program counter high byte. pclath program counter high byte latch. pclatu program counter upper byte latch. pd power-down bit. prodh product of multiply high byte. prodl product of multiply low byte. s fast call/return mode select bit s = 0 : do not update into/from shadow registers s = 1 : certain registers loaded into/from shadow registers (fast mode) tblptr 21-bit table pointer (points to a program memory location). tablat 8-bit table latch. to time-out bit. tos top-of-stack. u unused or unchanged. wdt watchdog timer. wreg working register (accumulator). x don?t care (? 0 ? or ? 1 ?). the assembler will generate code with x = 0 . it is the recommended form of use for compatibility with all microchip software tools. z s 7-bit offset value for indirect addr essing of register files (source). z d 7-bit offset value for indirect addressing of register files (destination). { } optional argument. [text] indicates an indexed address. (text) the contents of text . [expr] ? 2012 microchip technology inc. ds30684a-page 407 pic18(l)f2x/45k50 figure 27-1: general format for instructions byte-oriented file register operations 15 10 9 8 7 0 d = 0 for result destination to be wreg register opcode d a f (file #) d = 1 for result destination to be file register (f) a = 0 to force access bank bit-oriented file register operations 15 12 11 9 8 7 0 opcode b (bit #) a f (file #) b = 3-bit position of bit in file register (f) literal operations 15 8 7 0 opcode k (literal) k = 8-bit immediate value byte to byte move operations (2-word) 15 12 11 0 opcode f (source file #) call , goto and branch operations 15 8 7 0 opcode n<7:0> (literal) n = 20-bit immediate value a = 1 for bsr to select bank f = 8-bit file register address a = 0 to force access bank a = 1 for bsr to select bank f = 8-bit file register address 15 12 11 0 1111 n<19:8> (literal) 15 12 11 0 1111 f (destination file #) f = 12-bit file register address control operations example instruction addwf myreg, w, b movff myreg1, myreg2 bsf myreg, bit, b movlw 7fh goto label 15 8 7 0 opcode n<7:0> (literal) 15 12 11 0 1111 n<19:8> (literal) call myfunc 15 11 10 0 opcode n<10:0> (literal) s = fast bit bra myfunc 15 8 7 0 opcode n<7:0> (literal) bc myfunc s www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 408 ? 2012 microchip technology inc. table 27-2: pic18 instruction set mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb byte-oriented operations addwf addwfc andwf clrf comf cpfseq cpfsgt cpfslt decf decfsz dcfsnz incf incfsz infsnz iorwf movf movff movwf mulwf negf rlcf rlncf rrcf rrncf setf subfwb subwf subwfb swapf tstfsz xorwf f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f s , f d f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a add wreg and f add wreg and carry bit to f and wreg with f clear f complement f compare f with wreg, skip = compare f with wreg, skip > compare f with wreg, skip < decrement f decrement f, skip if 0 decrement f, skip if not 0 increment f increment f, skip if 0 increment f, skip if not 0 inclusive or wreg with f move f move f s (source) to 1st word f d (destination) 2nd word move wreg to f multiply wreg with f negate f rotate left f through carry rotate left f (no carry) rotate right f through carry rotate right f (no carry) set f subtract f from wreg with borrow subtract wreg from f subtract wreg from f with borrow swap nibbles in f test f, skip if 0 exclusive or wreg with f 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 (2 or 3) 1 0010 0010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 0101 0101 0011 0110 0001 01da 00da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da ffff ffff 111a 001a 110a 01da 01da 00da 00da 100a 01da 11da 10da 10da 011a 10da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff c, dc, z, ov, n c, dc, z, ov, n z, n z z, n none none none c, dc, z, ov, n none none c, dc, z, ov, n none none z, n z, n none none none c, dc, z, ov, n c, z, n z, n c, z, n z, n none c, dc, z, ov, n c, dc, z, ov, n c, dc, z, ov, n none none z, n 1, 2 1, 2 1,2 2 1, 2 4 4 1, 2 1, 2, 3, 4 1, 2, 3, 4 1, 2 1, 2, 3, 4 4 1, 2 1, 2 1 1, 2 1, 2 1, 2 1, 2 4 1, 2 note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as i nput and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tmr0 register (and where applicable, ?d? = 1 ), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are two-word instructions. the se cond word of these instructions will be executed as a nop unless the first word of the instruction retrieves the information embe dded in these 16 bits. this ensur es that all program memory locations have a valid instruction. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 409 pic18(l)f2x/45k50 bit-oriented operations bcf bsf btfsc btfss btg f, b, a f, b, a f, b, a f, b, a f, b, a bit clear f bit set f bit test f, skip if clear bit test f, skip if set bit toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff none none none none none 1, 2 1, 2 3, 4 3, 4 1, 2 control operations bc bn bnc bnn bnov bnz bov bra bz call clrwdt daw goto nop nop pop push rcall reset retfie retlw return sleep n n n n n n n n n k, s ? ? k ? ? ? ? n s k s ? branch if carry branch if negative branch if not carry branch if not negative branch if not overflow branch if not zero branch if overflow branch unconditionally branch if zero call subroutine 1st word 2nd word clear watchdog timer decimal adjust wreg go to address 1st word 2nd word no operation no operation pop top of return stack (tos) push top of return stack (tos) relative call software device reset return from interrupt enable return with literal in wreg return from subroutine go into standby mode 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 1 1 2 1 1 1 1 2 1 2 2 2 1 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0000 0000 0000 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 1100 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 kkkk 0001 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s kkkk 001s 0011 none none none none none none none none none none to , pd c none none none none none none all gie/gieh, peie/giel none none to , pd 4 table 27-2: pic18 instruction set (continued) mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as i nput and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tmr0 register (and where applicable, ?d? = 1 ), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are two-word instructions. the se cond word of these instructions will be executed as a nop unless the first word of the instruction retrieves the information embe dded in these 16 bits. this ensures that all program memory locations have a valid instruction. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 410 ? 2012 microchip technology inc. literal operations addlw andlw iorlw lfsr movlb movlw mullw retlw sublw xorlw k k k f, k k k k k k k add literal and wreg and literal with wreg inclusive or literal with wreg move literal (12-bit) 2nd word to fsr(f) 1st word move literal to bsr<3:0> move literal to wreg multiply literal with wreg return with literal in wreg subtract wreg from literal exclusive or literal with wreg 1 1 1 2 1 1 1 2 1 1 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk c, dc, z, ov, n z, n z, n none none none none none c, dc, z, ov, n z, n data memory ? program memory operations tblrd* tblrd*+ tblrd*- tblrd+* tblwt* tblwt*+ tblwt*- tblwt+* table read table read with post-increment table read with post-decrement table read with pre-increment table write table write with post-increment table write with post-decrement table write with pre-increment 2 2 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 1010 1011 1100 1101 1110 1111 none none none none none none none none table 27-2: pic18 instruction set (continued) mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as i nput and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tmr0 register (and where applicable, ?d? = 1 ), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are two-word instructions. the se cond word of these instructions will be executed as a nop unless the first word of the instruction retrieves the information embe dded in these 16 bits. this ensur es that all program memory locations have a valid instruction. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 411 pic18(l)f2x/45k50 27.1.1 standard instruction set addlw add literal to w syntax: addlw k operands: 0 ? k ? 255 operation: (w) + k ? w status affected: n, ov, c, dc, z encoding: 0000 1111 kkkk kkkk description: the contents of w are added to the 8-bit literal ?k? and the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example : addlw 15h before instruction w = 10h after instruction w = 25h addwf add w to f syntax: addwf f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (w) + (f) ? dest status affected: n, ov, c, dc, z encoding: 0010 01da ffff ffff description: add w to register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank. if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f ?? 95 (5fh). see section 27.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example : addwf reg, 0, 0 before instruction w = 17h reg = 0c2h after instruction w = 0d9h reg = 0c2h note: all pic18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. if a label is used, the instruction format then becomes: {label} instruction argument(s). www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 412 ? 2012 microchip technology inc. addwfc add w and carry bit to f syntax: addwfc f {,d {,a}} operands: 0 ? f ? 255 d ?? [0,1] a ?? [0,1] operation: (w) + (f) + (c) ? dest status affected: n,ov, c, dc, z encoding: 0010 00da ffff ffff description: add w, the carry flag and data mem- ory location ?f?. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed in data memory location ?f?. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank. if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example : addwfc reg, 0, 1 before instruction carry bit = 1 reg = 02h w=4dh after instruction carry bit = 0 reg = 02h w = 50h andlw and literal with w syntax: andlw k operands: 0 ? k ? 255 operation: (w) .and. k ? w status affected: n, z encoding: 0000 1011 kkkk kkkk description: the contents of w are and?ed with the 8-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example : andlw 05fh before instruction w=a3h after instruction w = 03h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 413 pic18(l)f2x/45k50 andwf and w with f syntax: andwf f {,d {,a}} operands: 0 ? f ? 255 d ?? [0,1] a ?? [0,1] operation: (w) .and. (f) ? dest status affected: n, z encoding: 0001 01da ffff ffff description: the contents of w are and?ed with register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank. if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example : andwf reg, 0, 0 before instruction w = 17h reg = c2h after instruction w = 02h reg = c2h bc branch if carry syntax: bc n operands: -128 ? n ? 127 operation: if carry bit is ? 1 ? (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0010 nnnn nnnn description: if the carry bit is ? 1 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example : here bc 5 before instruction pc = address (here) after instruction if carry = 1; pc = address (here + 12) if carry = 0; pc = address (here + 2) www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 414 ? 2012 microchip technology inc. bcf bit clear f syntax: bcf f, b {,a} operands: 0 ? f ? 255 0 ? b ? 7 a ?? [0,1] operation: 0 ? f status affected: none encoding: 1001 bbba ffff ffff description: bit ?b? in register ?f? is cleared. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank. if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example : bcf flag_reg, 7, 0 before instruction flag_reg = c7h after instruction flag_reg = 47h bn branch if negative syntax: bn n operands: -128 ? n ? 127 operation: if negative bit is ? 1 ? (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0110 nnnn nnnn description: if the negative bit is ? 1 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example : here bn jump before instruction pc = address (here) after instruction if negative = 1; pc = address (jump) if negative = 0; pc = address (here + 2) www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 415 pic18(l)f2x/45k50 bnc branch if not carry syntax: bnc n operands: -128 ? n ? 127 operation: if carry bit is ? 0 ? (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0011 nnnn nnnn description: if the carry bit is ? 0 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example : here bnc jump before instruction pc = address (here) after instruction if carry = 0; pc = address (jump) if carry = 1; pc = address (here + 2) bnn branch if not negative syntax: bnn n operands: -128 ? n ? 127 operation: if negative bit is ? 0 ? (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0111 nnnn nnnn description: if the negative bit is ? 0 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example : here bnn jump before instruction pc = address (here) after instruction if negative = 0; pc = address (jump) if negative = 1; pc = address (here + 2) www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 416 ? 2012 microchip technology inc. bnov branch if not overflow syntax: bnov n operands: -128 ? n ? 127 operation: if overflow bit is ? 0 ? (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0101 nnnn nnnn description: if the overflow bit is ? 0 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example : here bnov jump before instruction pc = address (here) after instruction if overflow = 0; pc = address (jump) if overflow = 1; pc = address (here + 2) bnz branch if not zero syntax: bnz n operands: -128 ? n ? 127 operation: if zero bit is ? 0 ? (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0001 nnnn nnnn description: if the zero bit is ? 0 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example : here bnz jump before instruction pc = address (here) after instruction if zero = 0; pc = address (jump) if zero = 1; pc = address (here + 2) www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 417 pic18(l)f2x/45k50 bra unconditional branch syntax: bra n operands: -1024 ? n ? 1023 operation: (pc) + 2 + 2n ? pc status affected: none encoding: 1101 0nnn nnnn nnnn description: add the 2?s complement number ?2n? to the pc. since the pc will have incre- mented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is a two-cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation example : here bra jump before instruction pc = address (here) after instruction pc = address (jump) bsf bit set f syntax: bsf f, b {,a} operands: 0 ? f ? 255 0 ? b ? 7 a ?? [0,1] operation: 1 ? f status affected: none encoding: 1000 bbba ffff ffff description: bit ?b? in register ?f? is set. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank. if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f ?? 95 (5fh). see section 27.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example : bsf flag_reg, 7, 1 before instruction flag_reg = 0ah after instruction flag_reg = 8ah www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 418 ? 2012 microchip technology inc. btfsc bit test file, skip if clear syntax: btfsc f, b {,a} operands: 0 ? f ? 255 0 ? b ? 7 a ?? [0,1] operation: skip if (f) = 0 status affected: none encoding: 1011 bbba ffff ffff description: if bit ?b? in register ?f? is ? 0 ?, then the next instruction is skipped. if bit ?b? is ? 0 ?, then the next instruction fetched during the current instruction execution is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank. if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: three cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here false true btfsc : : flag, 1, 0 before instruction pc = address (here) after instruction if flag<1> = 0; pc = address (true) if flag<1> = 1; pc = address (false) btfss bit test file, skip if set syntax: btfss f, b {,a} operands: 0 ? f ? 255 0 ? b < 7 a ?? [0,1] operation: skip if (f) = 1 status affected: none encoding: 1010 bbba ffff ffff description: if bit ?b? in register ?f? is ? 1 ?, then the next instruction is skipped. if bit ?b? is ? 1 ?, then the next instruction fetched during the current instruction execution is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank. if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: three cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here false true btfss : : flag, 1, 0 before instruction pc = address (here) after instruction if flag<1> = 0; pc = address (false) if flag<1> = 1; pc = address (true) www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 419 pic18(l)f2x/45k50 btg bit toggle f syntax: btg f, b {,a} operands: 0 ? f ? 255 0 ? b < 7 a ?? [0,1] operation: (f ) ? f status affected: none encoding: 0111 bbba ffff ffff description: bit ?b? in data memory location ?f? is inverted. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank. if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example : btg portc, 4, 0 before instruction: portc = 0111 0101 [75h] after instruction: portc = 0110 0101 [65h] bov branch if overflow syntax: bov n operands: -128 ? n ? 127 operation: if overflow bit is ? 1 ? (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0100 nnnn nnnn description: if the overflow bit is ? 1 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example : here bov jump before instruction pc = address (here) after instruction if overflow = 1; pc = address (jump) if overflow = 0; pc = address (here + 2) www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 420 ? 2012 microchip technology inc. bz branch if zero syntax: bz n operands: -128 ? n ? 127 operation: if zero bit is ? 1 ? (pc) + 2 + 2n ? pc status affected: none encoding: 1110 0000 nnnn nnnn description: if the zero bit is ? 1 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example : here bz jump before instruction pc = address (here) after instruction if zero = 1; pc = address (jump) if zero = 0; pc = address (here + 2) call subroutine call syntax: call k {,s} operands: 0 ? k ? 1048575 s ?? [0,1] operation: (pc) + 4 ? tos, k ? pc<20:1>, if s = 1 (w) ? ws, (status) ? statuss, (bsr) ? bsrs status affected: none encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 110s k 19 kkk k 7 kkk kkkk kkkk 0 kkkk 8 description: subroutine call of entire 2-mbyte memory range. first, return address (pc + 4) is pushed onto the return stack. if ?s? = 1 , the w, status and bsr registers are also pushed into their respective shadow registers, ws, statuss and bsrs. if ?s? = 0 , no update occurs. then, the 20-bit value ?k? is loaded into pc<20:1>. call is a two-cycle instruction. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k?<7:0>, push pc to stack read literal ?k?<19:8>, write to pc no operation no operation no operation no operation example : here call there, 1 before instruction pc = address (here) after instruction pc = address (there) tos = address (here + 4) ws = w bsrs = bsr statuss = status www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 421 pic18(l)f2x/45k50 clrf clear f syntax: clrf f {,a} operands: 0 ? f ? 255 a ?? [0,1] operation: 000h ? f 1 ? z status affected: z encoding: 0110 101a ffff ffff description: clears the contents of the specified register. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank. if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example : clrf flag_reg, 1 before instruction flag_reg = 5ah after instruction flag_reg = 00h clrwdt clear watchdog timer syntax: clrwdt operands: none operation: 000h ? wdt, 000h ? wdt postscaler, 1 ? to, 1 ? pd status affected: to , pd encoding: 0000 0000 0000 0100 description: clrwdt instruction resets the watchdog timer. it also resets the post- scaler of the wdt. status bits, to and pd , are set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation process data no operation example : clrwdt before instruction wdt counter = ? after instruction wdt counter = 00h wdt postscaler = 0 to =1 pd =1 www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 422 ? 2012 microchip technology inc. comf complement f syntax: comf f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f ) ? dest status affected: n, z encoding: 0001 11da ffff ffff description: the contents of register ?f? are complemented. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank. if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example : comf reg, 0, 0 before instruction reg = 13h after instruction reg = 13h w=ech cpfseq compare f with w, skip if f = w syntax: cpfseq f {,a} operands: 0 ? f ? 255 a ? [0,1] operation: (f) ? (w), skip if (f) = (w) (unsigned comparison) status affected: none encoding: 0110 001a ffff ffff description: compares the contents of data memory location ?f? to the contents of w by performing an unsigned subtraction. if ?f? = w, then the fetched instruction is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank. if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f ?? 95 (5fh). see section 27.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: three cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here cpfseq reg, 0 nequal : equal : before instruction pc address = here w=? reg = ? after instruction if reg = w; pc = address (equal) if reg ? w; pc = address (nequal) www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 423 pic18(l)f2x/45k50 cpfsgt compare f with w, skip if f > w syntax: cpfsgt f {,a} operands: 0 ? f ? 255 a ? [0,1] operation: (f) ? ?? w), skip if (f) > (w) (unsigned comparison) status affected: none encoding: 0110 010a ffff ffff description: compares the contents of data memory location ?f? to the contents of the w by performing an unsigned subtraction. if the contents of ?f? are greater than the contents of wreg , then the fetched instruction is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank. if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: three cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here cpfsgt reg, 0 ngreater : greater : before instruction pc = address (here) w= ? after instruction if reg ? w; pc = address (greater) if reg ? w; pc = address (ngreater) cpfslt compare f with w, skip if f < w syntax: cpfslt f {,a} operands: 0 ? f ? 255 a ? [0,1] operation: (f) ? ?? w), skip if (f) < (w) (unsigned comparison) status affected: none encoding: 0110 000a ffff ffff description: compares the contents of data memory location ?f? to the contents of w by performing an unsigned subtraction. if the contents of ?f? are less than the contents of w, then the fetched instruction is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank. words: 1 cycles: 1(2) note: three cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here cpfslt reg, 1 nless : less : before instruction pc = address (here) w= ? after instruction if reg < w; pc = address (less) if reg ? w; pc = address (nless) www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 424 ? 2012 microchip technology inc. daw decimal adjust w register syntax: daw operands: none operation: if [w<3:0> > 9] or [dc = 1] then (w<3:0>) + 6 ? w<3:0>; else ( w<3:0>) ? w<3:0>; if [w<7:4> + dc > 9] or [c = 1] then ( w<7:4>) + 6 + dc ? w<7:4> ? ; c = 1; else (w<7:4>) + dc ? w<7:4> status affected: c encoding: 0000 0000 0000 0111 description: daw adjusts the eight-bit value in w, resulting from the earlier addition of two variables (each in packed bcd format) and produces a correct packed bcd result. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register w process data write w example1 : daw before instruction w=a5h c=0 dc = 0 after instruction w = 05h c=1 dc = 0 example 2 : before instruction w=ceh c=0 dc = 0 after instruction w = 34h c=1 dc = 0 decf decrement f syntax: decf f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) ? 1 ? dest status affected: c, dc, n, ov, z encoding: 0000 01da ffff ffff description: decrement register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank. if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f ?? 95 (5fh). see section 27.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example : decf cnt, 1, 0 before instruction cnt = 01h z=0 after instruction cnt = 00h z=1 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 425 pic18(l)f2x/45k50 decfsz decrement f, skip if 0 syntax: decfsz f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) ? 1 ? dest, skip if result = 0 status affected: none encoding: 0010 11da ffff ffff description: the contents of register ?f? are decremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 0 ?, the next instruction, which is already fetched, is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank. if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: three cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here decfsz cnt, 1, 1 goto loop continue before instruction pc = address (here) after instruction cnt = cnt - 1 if cnt = 0; pc = address (continue) if cnt ? 0; pc = address (here + 2) dcfsnz decrement f, skip if not 0 syntax: dcfsnz f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) ? 1 ? dest, skip if result ? 0 status affected: none encoding: 0100 11da ffff ffff description: the contents of register ?f? are decremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is not ? 0 ?, the next instruction, which is already fetched, is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank. if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f ?? 95 (5fh). see section 27.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: three cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here dcfsnz temp, 1, 0 zero : nzero : before instruction temp = ? after instruction temp = temp ? 1, if temp = 0; pc = address (zero) if temp ? 0; pc = address (nzero) www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 426 ? 2012 microchip technology inc. goto unconditional branch syntax: goto k operands: 0 ? k ? 1048575 operation: k ? pc<20:1> status affected: none encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 1111 k 19 kkk k 7 kkk kkkk kkkk 0 kkkk 8 description: goto allows an unconditional branch anywhere within entire 2-mbyte memory range. the 20-bit value ?k? is loaded into pc<20:1>. goto is always a two-cycle instruction. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k?<7:0>, no operation read literal ?k?<19:8>, write to pc no operation no operation no operation no operation example : goto there after instruction pc = address (there) incf increment f syntax: incf f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) + 1 ? dest status affected: c, dc, n, ov, z encoding: 0010 10da ffff ffff description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f?. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank. if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f ?? 95 (5fh). see section 27.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example : incf cnt, 1, 0 before instruction cnt = ffh z=0 c=? dc = ? after instruction cnt = 00h z=1 c=1 dc = 1 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 427 pic18(l)f2x/45k50 incfsz increment f, skip if 0 syntax: incfsz f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) + 1 ? dest, skip if result = 0 status affected: none encoding: 0011 11da ffff ffff description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 0 ?, the next instruction, which is already fetched, is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank. if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here incfsz cnt, 1, 0 nzero : zero : before instruction pc = address (here) after instruction cnt = cnt + 1 if cnt = 0; pc = address (zero) if cnt ? 0; pc = address (nzero) infsnz increment f, skip if not 0 syntax: infsnz f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) + 1 ? dest, skip if result ? 0 status affected: none encoding: 0100 10da ffff ffff description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is not ? 0 ?, the next instruction, which is already fetched, is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank. if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f ?? 95 (5fh). see section 27.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here infsnz reg, 1, 0 zero nzero before instruction pc = address (here) after instruction reg = reg + 1 if reg ? 0; pc = address (nzero) if reg = 0; pc = address (zero) www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 428 ? 2012 microchip technology inc. iorlw inclusive or literal with w syntax: iorlw k operands: 0 ? k ? 255 operation: (w) .or. k ? w status affected: n, z encoding: 0000 1001 kkkk kkkk description: the contents of w are ored with the eight-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example : iorlw 35h before instruction w=9ah after instruction w=bfh iorwf inclusive or w with f syntax: iorwf f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (w) .or. (f) ? dest status affected: n, z encoding: 0001 00da ffff ffff description: inclusive or w with register ?f?. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f?. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank. if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f ?? 95 (5fh). see section 27.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example : iorwf result, 0, 1 before instruction result = 13h w = 91h after instruction result = 13h w = 93h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 429 pic18(l)f2x/45k50 lfsr load fsr syntax: lfsr f, k operands: 0 ? f ? 2 0 ? k ? 4095 operation: k ? fsrf status affected: none encoding: 1110 1111 1110 0000 00ff k 7 kkk k 11 kkk kkkk description: the 12-bit literal ?k? is loaded into the file select register pointed to by ?f?. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k? msb process data write literal ?k? msb to fsrfh decode read literal ?k? lsb process data write literal ?k? to fsrfl example : lfsr 2, 3abh after instruction fsr2h = 03h fsr2l = abh movf move f syntax: movf f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: f ? dest status affected: n, z encoding: 0101 00da ffff ffff description: the contents of register ?f? are moved to a destination dependent upon the status of ?d?. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f?. location ?f? can be anywhere in the 256-byte bank. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank. if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f ?? 95 (5fh). see section 27.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write w example : movf reg, 0, 0 before instruction reg = 22h w=ffh after instruction reg = 22h w = 22h www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 430 ? 2012 microchip technology inc. movff move f to f syntax: movff f s ,f d operands: 0 ? f s ? 4095 0 ? f d ? 4095 operation: (f s ) ? f d status affected: none encoding: 1st word (source) 2nd word (destin.) 1100 1111 ffff ffff ffff ffff fff f s fff f d description: the contents of source register ?f s ? are moved to destination register ?f d ?. location of source ?f s ? can be anywhere in the 4096-byte data space (000h to fffh) and location of destination ?f d ? can also be anywhere from 000h to fffh. either source or destination can be w (a useful special situation). movff is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an i/o port). the movff instruction cannot use the pcl, tosu, tosh or tosl as the destination register. words: 2 cycles: 2 (3) q cycle activity: q1 q2 q3 q4 decode read register ?f? (src) process data no operation decode no operation no dummy read no operation write register ?f? (dest) example : movff reg1, reg2 before instruction reg1 = 33h reg2 = 11h after instruction reg1 = 33h reg2 = 33h movlb move literal to low nibble in bsr syntax: movlb k operands: 0 ? k ? 255 operation: k ? bsr status affected: none encoding: 0000 0001 kkkk kkkk description: the eight-bit literal ?k? is loaded into the bank select register (bsr). the value of bsr<7:4> always remains ? 0 ?, regardless of the value of k 7 :k 4 . words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write literal ?k? to bsr example : movlb 5 before instruction bsr register = 02h after instruction bsr register = 05h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 431 pic18(l)f2x/45k50 movlw move literal to w syntax: movlw k operands: 0 ? k ? 255 operation: k ? w status affected: none encoding: 0000 1110 kkkk kkkk description: the eight-bit literal ?k? is loaded into w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example : movlw 5ah after instruction w=5ah movwf move w to f syntax: movwf f {,a} operands: 0 ? f ? 255 a ? [0,1] operation: (w) ? f status affected: none encoding: 0110 111a ffff ffff description: move data from w to register ?f?. location ?f? can be anywhere in the 256-byte bank. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank. if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example : movwf reg, 0 before instruction w=4fh reg = ffh after instruction w=4fh reg = 4fh www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 432 ? 2012 microchip technology inc. mullw multiply literal with w syntax: mullw k operands: 0 ? k ? 255 operation: (w) x k ? prodh:prodl status affected: none encoding: 0000 1101 kkkk kkkk description: an unsigned multiplication is carried out between the contents of w and the 8-bit literal ?k?. the 16-bit result is placed in the prodh:prodl register pair. prodh contains the high byte. w is unchanged. none of the status flags are affected. note that neither overflow nor carry is possible in this operation. a zero result is possible but not detected. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write registers prodh: prodl example : mullw 0c4h before instruction w=e2h prodh = ? prodl = ? after instruction w=e2h prodh = adh prodl = 08h mulwf multiply w with f syntax: mulwf f {,a} operands: 0 ? f ? 255 a ? [0,1] operation: (w) x (f) ? prodh:prodl status affected: none encoding: 0000 001a ffff ffff description: an unsigned multiplication is carried out between the contents of w and the register file location ?f?. the 16-bit result is stored in the prodh:prodl register pair. prodh contains the high byte. both w and ?f? are unchanged. none of the status flags are affected. note that neither overflow nor carry is possible in this operation. a zero result is possible but not detected. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank. if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write registers prodh: prodl example : mulwf reg, 1 before instruction w=c4h reg = b5h prodh = ? prodl = ? after instruction w=c4h reg = b5h prodh = 8ah prodl = 94h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 433 pic18(l)f2x/45k50 negf negate f syntax: negf f {,a} operands: 0 ? f ? 255 a ? [0,1] operation: ( f ) + 1 ? f status affected: n, ov, c, dc, z encoding: 0110 110a ffff ffff description: location ?f? is negated using two?s complement. the result is placed in the data memory location ?f?. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank. if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example : negf reg, 1 before instruction reg = 0011 1010 [3ah] after instruction reg = 1100 0110 [c6h] nop no operation syntax: nop operands: none operation: no operation status affected: none encoding: 0000 1111 0000 xxxx 0000 xxxx 0000 xxxx description: no operation. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation example : none. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 434 ? 2012 microchip technology inc. pop pop top of return stack syntax: pop operands: none operation: (tos) ? bit bucket status affected: none encoding: 0000 0000 0000 0110 description: the tos value is pulled off the return stack and is discarded. the tos value then becomes the previous value that was pushed onto the return stack. this instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation pop tos value no operation example : pop goto new before instruction tos = 0031a2h stack (1 level down) = 014332h after instruction tos = 014332h pc = new push push top of return stack syntax: push operands: none operation: (pc + 2) ? tos status affected: none encoding: 0000 0000 0000 0101 description: the pc + 2 is pushed onto the top of the return stack. the previous tos value is pushed down on the stack. this instruction allows implementing a software stack by modifying tos and then pushing it onto the return stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode push pc + 2 onto return stack no operation no operation example : push before instruction tos = 345ah pc = 0124h after instruction pc = 0126h tos = 0126h stack (1 level down) = 345ah www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 435 pic18(l)f2x/45k50 rcall relative call syntax: rcall n operands: -1024 ? n ? 1023 operation: (pc) + 2 ? tos, (pc) + 2 + 2n ? pc status affected: none encoding: 1101 1nnn nnnn nnnn description: subroutine call with a jump up to 1k from the current location. first, return address (pc + 2) is pushed onto the stack. then, add the 2?s complement number ?2n? to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is a two-cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?n? push pc to stack process data write to pc no operation no operation no operation no operation example : here rcall jump before instruction pc = address (here) after instruction pc = address (jump) tos = address (here + 2) reset reset syntax: reset operands: none operation: reset all registers and flags that are affected by a mclr reset. status affected: all encoding: 0000 0000 1111 1111 description: this instruction provides a way to execute a mclr reset by software. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode start reset no operation no operation example : reset after instruction registers = reset value flags* = reset value www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 436 ? 2012 microchip technology inc. retfie return from interrupt syntax: retfie {s} operands: s ? [0,1] operation: (tos) ? pc, 1 ? gie/gieh or peie/giel, if s = 1 (ws) ? w, (statuss) ? status, (bsrs) ? bsr, pclatu, pclath are unchanged. status affected: gie/gieh, peie/giel. encoding: 0000 0000 0001 000s description: return from interrupt. stack is popped and top-of-stack (tos) is loaded into the pc. interrupts are enabled by setting either the high or low priority global interrupt enable bit. if ?s? = 1 , the contents of the shadow registers, ws, statuss and bsrs, are loaded into their corresponding registers, w, status and bsr. if ?s? = 0 , no update of these registers occurs. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation pop pc from stack set gieh or giel no operation no operation no operation no operation example : retfie 1 after interrupt pc = tos w=ws bsr = bsrs status = statuss gie/gieh, peie/giel = 1 retlw return literal to w syntax: retlw k operands: 0 ? k ? 255 operation: k ? w, (tos) ? pc, pclatu, pclath are unchanged status affected: none encoding: 0000 1100 kkkk kkkk description: w is loaded with the eight-bit literal ?k?. the program counter is loaded from the top of the stack (the return address). the high address latch (pclath) remains unchanged. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data pop pc from stack, write to w no operation no operation no operation no operation example : call table ; w contains table ; offset value ; w now has ; table value : table addwf pcl ; w = offset retlw k0 ; begin table retlw k1 ; : : retlw kn ; end of table before instruction w = 07h after instruction w = value of kn www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 437 pic18(l)f2x/45k50 return return from subroutine syntax: return {s} operands: s ? [0,1] operation: (tos) ? pc, if s = 1 (ws) ? w, (statuss) ? status, (bsrs) ? bsr, pclatu, pclath are unchanged status affected: none encoding: 0000 0000 0001 001s description: return from subroutine. the stack is popped and the top of the stack (tos) is loaded into the program counter. if ?s?= 1 , the contents of the shadow registers, ws, statuss and bsrs, are loaded into their corresponding registers, w, status and bsr. if ?s? = 0 , no update of these registers occurs. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation process data pop pc from stack no operation no operation no operation no operation example : return after instruction: pc = tos rlcf rotate left f through carry syntax: rlcf f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f pic18(l)f2x/45k50 ds30684a-page 438 ? 2012 microchip technology inc. rlncf rotate left f (no carry) syntax: rlncf f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f ? 2012 microchip technology inc. ds30684a-page 439 pic18(l)f2x/45k50 rrncf rotate right f (no carry) syntax: rrncf f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f pic18(l)f2x/45k50 ds30684a-page 440 ? 2012 microchip technology inc. sleep enter sleep mode syntax: sleep operands: none operation: 00h ? wdt, 0 ? wdt postscaler, 1 ? to , 0 ? pd status affected: to , pd encoding: 0000 0000 0000 0011 description: the power-down status bit (pd ) is cleared. the time-out status bit (to ) is set. the watchdog timer and its postscaler are cleared. the processor is put into sleep mode with the oscillator stopped. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation process data go to sleep example : sleep before instruction to =? pd =? after instruction to =1 ? pd =0 ? if wdt causes wake-up, this bit is cleared. subfwb subtract f from w with borrow syntax: subfwb f {,d {,a}} operands: 0 ?? f ?? 255 d ? [0,1] a ? [0,1] operation: (w) ? (f) ? (c ) ?? dest status affected: n, ov, c, dc, z encoding: 0101 01da ffff ffff description: subtract register ?f? and carry flag (borrow) from w (2?s complement method). if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored in register ?f?. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank. if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in index ed litera l offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example 1 : subfwb reg, 1, 0 before instruction reg = 3 w=2 c=1 after instruction reg = ff w=2 c=0 z=0 n = 1 ; result is negative example 2 : subfwb reg, 0, 0 before instruction reg = 2 w=5 c=1 after instruction reg = 2 w=3 c=1 z=0 n = 0 ; result is positive example 3 : subfwb reg, 1, 0 before instruction reg = 1 w=2 c=0 after instruction reg = 0 w=2 c=1 z = 1 ; result is zero n=0 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 441 pic18(l)f2x/45k50 sublw subtract w from literal syntax: sublw k operands: 0 ?? k ?? 255 operation: k ? (w) ?? w status affected: n, ov, c, dc, z encoding: 0000 1000 kkkk kkkk description w is subtracted from the eight-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example 1: sublw 02h before instruction w = 01h c=? after instruction w = 01h c = 1 ; result is positive z=0 n=0 example 2 : sublw 02h before instruction w = 02h c=? after instruction w = 00h c = 1 ; result is zero z=1 n=0 example 3 : sublw 02h before instruction w = 03h c=? after instruction w = ffh ; (2?s complement) c = 0 ; result is negative z=0 n=1 subwf subtract w from f syntax: subwf f {,d {,a}} operands: 0 ?? f ?? 255 d ? [0,1] a ? [0,1] operation: (f) ? (w) ?? dest status affected: n, ov, c, dc, z encoding: 0101 11da ffff ffff description: subtract w from register ?f? (2?s complement method). if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank. if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in index ed litera l offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example 1 : subwf reg, 1, 0 before instruction reg = 3 w=2 c=? after instruction reg = 1 w=2 c = 1 ; result is positive z=0 n=0 example 2 : subwf reg, 0, 0 before instruction reg = 2 w=2 c=? after instruction reg = 2 w=0 c=1; result is zero z=1 n=0 example 3 : subwf reg, 1, 0 before instruction reg = 1 w=2 c=? after instruction reg = ffh ;(2?s complement) w=2 c = 0 ; result is negative z=0 n=1 www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 442 ? 2012 microchip technology inc. subwfb subtract w from f with borrow syntax: subwfb f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f) ? (w) ? (c ) ?? dest status affected: n, ov, c, dc, z encoding: 0101 10da ffff ffff description: subtract w and the carry flag (borrow) from register ?f? (2?s comple- ment method). if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank. if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f ?? 95 (5fh). see section 27.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example 1 : subwfb reg, 1, 0 before instruction reg = 19h (0001 1001) w =0dh (0000 1101) c=1 after instruction reg = 0ch (0000 1100) w =0dh (0000 1101) c=1 z=0 n = 0 ; result is positive example 2 : subwfb reg, 0, 0 before instruction reg = 1bh (0001 1011) w =1ah (0001 1010) c=0 after instruction reg = 1bh (0001 1011) w = 00h c=1 z = 1 ; result is zero n=0 example 3: subwfb reg, 1, 0 before instruction reg = 03h (0000 0011) w =0eh (0000 1110) c=1 after instruction reg = f5h (1111 0101) ; [2?s comp] w =0eh (0000 1110) c=0 z=0 n = 1 ; result is negative swapf swap f syntax: swapf f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (f<3:0>) ? dest<7:4>, (f<7:4>) ? dest<3:0> status affected: none encoding: 0011 10da ffff ffff description: the upper and lower nibbles of register ?f? are exchanged. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed in register ?f?. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank. if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f ?? 95 (5fh). see section 27.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example : swapf reg, 1, 0 before instruction reg = 53h after instruction reg = 35h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 443 pic18(l)f2x/45k50 tblrd table read syntax: tblrd ( *; *+; *-; +*) operands: none operation: if tblrd *, (prog mem (tblptr)) ? tablat; tblptr ? no change; if tblrd *+, (prog mem (tblptr)) ? tablat; (tblptr) + 1 ? tblptr; if tblrd *-, (prog mem (tblptr)) ? tablat; (tblptr) ? 1 ? tblptr; if tblrd +*, (tblptr) + 1 ? tblptr; (prog mem (tblptr)) ? tablat; status affected: none encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *- =3 +* description: this instruction is used to read the contents of program memory (p.m.). to address the program memory, a pointer called table pointer (tblptr) is used. the tblptr (a 21-bit pointer) points to each byte in the program memory. tblptr has a 2-mbyte address range. tblptr[0] = 0 : least significant byte of program memory word tblptr[0] = 1 : most significant byte of program memory word the tblrd instruction can modify the value of tblptr as follows: ? no change ? post-increment ? post-decrement ? pre-increment words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation no operation no operation (read program memory) no operation no operation (write tab- lat) tblrd table read (continued) example1 : tblrd *+ ; before instruction tablat = 55h tblptr = 00a356h memory (00a356h) = 34h after instruction tablat = 34h tblptr = 00a357h example2 : tblrd +* ; before instruction tablat = aah tblptr = 01a357h memory (01a357h) = 12h memory (01a358h) = 34h after instruction tablat = 34h tblptr = 01a358h www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 444 ? 2012 microchip technology inc. tblwt table write syntax: tblwt ( *; *+; *-; +*) operands: none operation: if tblwt*, (tablat) ? holding register; tblptr ? no change; if tblwt*+, (tablat) ? holding register; (tblptr) + 1 ? tblptr; if tblwt*-, (tablat) ? holding register; (tblptr) ? 1 ? tblptr; if tblwt+*, (tblptr) + 1 ? tblptr; (tablat) ? holding register; status affected: none encoding: 0000 0000 0000 11nn nn=0 * =1 *+ =2 *- =3 +* description: this instruction uses the three lsbs of tblptr to determine which of the eight holding registers the tablat is written to. the holding registers are used to program the contents of program memory (p.m.). (refer to section 7.0 ?flash program memory? for additional details on programming flash memory.) the tblptr (a 21-bit pointer) points to each byte in the program memory. tblptr has a 2-mbyte address range. the lsb of the tblptr selects which byte of the program memory location to access. tblptr[0] = 0 : least significant byte of program memory word tblptr[0] = 1 : most significant byte of program memory word the tblwt instruction can modify the value of tblptr as follows: ? no change ? post-increment ? post-decrement ? pre-increment words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation no operation no operation (read tablat) no operation no operation (write to holding register ) tblwt table write (continued) example1 : tblwt *+; before instruction tablat = 55h tblptr = 00a356h holding register (00a356h) = ffh after instructions (table write completion) tablat = 55h tblptr = 00a357h holding register (00a356h) = 55h example 2 : tblwt +*; before instruction tablat = 34h tblptr = 01389ah holding register (01389ah) = ffh holding register (01389bh) = ffh after instruction (table write completion) tablat = 34h tblptr = 01389bh holding register (01389ah) = ffh holding register (01389bh) = 34h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 445 pic18(l)f2x/45k50 tstfsz test f, skip if 0 syntax: tstfsz f {,a} operands: 0 ? f ? 255 a ? [0,1] operation: skip if f = 0 status affected: none encoding: 0110 011a ffff ffff description: if ?f? = 0 , the next instruction fetched during the current instruction execution is discarded and a nop is executed, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank. if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: three cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here tstfsz cnt, 1 nzero : zero : before instruction pc = address (here) after instruction if cnt = 00h, pc = address (zero) if cnt ? 00h, pc = address (nzero) xorlw exclusive or literal with w syntax: xorlw k operands: 0 ?? k ?? 255 operation: (w) .xor. k ?? w status affected: n, z encoding: 0000 1010 kkkk kkkk description: the contents of w are xored with the 8-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example : xorlw 0afh before instruction w=b5h after instruction w=1ah www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 446 ? 2012 microchip technology inc. xorwf exclusive or w with f syntax: xorwf f {,d {,a}} operands: 0 ? f ? 255 d ? [0,1] a ? [0,1] operation: (w) .xor. (f) ?? dest status affected: n, z encoding: 0001 10da ffff ffff description: exclusive or the contents of w with register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in the register ?f?. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank. if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f ?? 95 (5fh). see section 27.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example : xorwf reg, 1, 0 before instruction reg = afh w=b5h after instruction reg = 1ah w=b5h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 447 pic18(l)f2x/45k50 27.2 extended instruction set in addition to the standard 75 instructions of the pic18 instruction set, pic18(l)f2x/45k50 devices also provide an optional extension to the core cpu functionality. the added features include eight additional instructions that augment indirect and indexed addressing operations and the implementation of indexed literal offset addressing mode for many of the standard pic18 instructions. the additional features of the extended instruction set are disabled by default. to enable them, users must set the xinst configuration bit. the instructions in the extended set can all be classified as literal operations, which either manipulate the file select registers, or use them for indexed addressing. two of the instructions, addfsr and subfsr , each have an additional special instantiation for using fsr2. these versions ( addulnk and subulnk ) allow for automatic return after execution. the extended instructions are specifically implemented to optimize re-entrant program code (that is, code that is recursive or that uses a software stack) written in high-level languages, particularly c. among other things, they allow users working in high-level languages to perform certain operations on data structures more efficiently. these include: ? dynamic allocation and deallocation of software stack space when entering and leaving subroutines ? function pointer invocation ? software stack pointer manipulation ? manipulation of variables located in a software stack a summary of the instructions in the extended instruc- tion set is provided in tab l e 2 7- 3 . detailed descriptions are provided in section 27.2.2 ?extended instruction set? . the opcode field descriptions in tab l e 2 7- 1 apply to both the standard and extended pic18 instruction sets. 27.2.1 extended instruction syntax most of the extended instructions use indexed arguments, using one of the file select registers and some offset to specify a source or destination register. when an argument for an instruction serves as part of indexed addressing, it is enclosed in square brackets (?[ ]?). this is done to indicate that the argument is used as an index or offset. mpasm? assembler will flag an error if it determines that an index or offset value is not bracketed. when the extended instruction set is enabled, brackets are also used to indicate index arguments in byte- oriented and bit-oriented instructions. this is in addition to other changes in their syntax. for more details, see section 27.2.3.1 ?extended instruction syntax with standard pic18 commands? . table 27-3: extensions to the pic18 instruction set note: the instruction set extension and the indexed literal offset addressing mode were designed for optimizing applications written in c; the user may likely never use these instructions directly in assembler. the syntax for these commands is pro- vided as a reference for users who may be reviewing code that has been generated by a compiler. note: in the past, square brackets have been used to denote optional arguments in the pic18 and earlier instruction sets. in this text and going forward, optional arguments are denoted by braces (?{ }?). mnemonic, operands description cycles 16-bit instruction word status affected msb lsb addfsr addulnk callw movsf movss pushl subfsr subulnk f, k k z s , f d z s , z d k f, k k add literal to fsr add literal to fsr2 and return call subroutine using wreg move z s (source) to 1st word f d (destination) 2nd word move z s (source) to 1st word z d (destination) 2nd word store literal at fsr2, decrement fsr2 subtract literal from fsr subtract literal from fsr2 and return 1 2 2 2 2 1 1 2 1110 1110 0000 1110 1111 1110 1111 1110 1110 1110 1000 1000 0000 1011 ffff 1011 xxxx 1010 1001 1001 ffkk 11kk 0001 0zzz ffff 1zzz xzzz kkkk ffkk 11kk kkkk kkkk 0100 zzzz ffff zzzz zzzz kkkk kkkk kkkk none none none none none none none none www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 448 ? 2012 microchip technology inc. 27.2.2 extended instruction set addfsr add literal to fsr syntax: addfsr f, k operands: 0 ? k ? 63 f ? [ 0, 1, 2 ] operation: fsr(f) + k ? fsr(f) status affected: none encoding: 1110 1000 ffkk kkkk description: the 6-bit literal ?k? is added to the contents of the fsr specified by ?f?. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to fsr example: addfsr 2, 23h before instruction fsr2 = 03ffh after instruction fsr2 = 0422h addulnk add literal to fsr2 and return syntax: addulnk k operands: 0 ? k ? 63 operation: fsr2 + k ? fsr2, (tos) ?? pc status affected: none encoding: 1110 1000 11kk kkkk description: the 6-bit literal ?k? is added to the contents of fsr2. a return is then executed by loading the pc with the tos. the instruction takes two cycles to execute; a nop is performed during the second cycle. this may be thought of as a special case of the addfsr instruction, where f = 3 (binary ? 11 ?); it operates only on fsr2. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to fsr no operation no operation no operation no operation example: addulnk 23h before instruction fsr2 = 03ffh pc = 0100h after instruction fsr2 = 0422h pc = (tos) note: all pic18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. if a label is used, the instruction syntax then becomes: {label} instruction argument(s). www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 449 pic18(l)f2x/45k50 callw subroutine call using wreg syntax: callw operands: none operation: (pc + 2) ? tos, (w) ? pcl, (pclath) ? pch, (pclatu) ? pcu status affected: none encoding: 0000 0000 0001 0100 description first, the return address (pc + 2) is pushed onto the return stack. next, the contents of w are written to pcl; the existing value is discarded. then, the contents of pclath and pclatu are latched into pch and pcu, respectively. the second cycle is executed as a nop instruction while the new next instruction is fetched. unlike call , there is no option to update w, status or bsr. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read wreg push pc to stack no operation no operation no operation no operation no operation example : here callw before instruction pc = address (here) pclath = 10h pclatu = 00h w = 06h after instruction pc = 001006h tos = address (here + 2) pclath = 10h pclatu = 00h w = 06h movsf move indexed to f syntax: movsf [z s ], f d operands: 0 ? z s ? 127 0 ? f d ? 4095 operation: ((fsr2) + z s ) ? f d status affected: none encoding: 1st word (source) 2nd word (destin.) 1110 1111 1011 ffff 0zzz ffff zzzz s ffff d description: the contents of the source register are moved to destination register ?f d ?. the actual address of the source register is determined by adding the 7-bit literal offset ?z s ? in the first word to the value of fsr2. the address of the destination register is specified by the 12-bit literal ?f d ? in the second word. both addresses can be anywhere in the 4096-byte data space (000h to fffh). the movsf instruction cannot use the pcl, tosu, tosh or tosl as the destination register. if the resultant source address points to an indirect addressing register, the value returned will be 00h. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode determine source addr determine source addr read source reg decode no operation no dummy read no operation write register ?f? (dest) example : movsf [05h], reg2 before instruction fsr2 = 80h contents of 85h = 33h reg2 = 11h after instruction fsr2 = 80h contents of 85h = 33h reg2 = 33h www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 450 ? 2012 microchip technology inc. movss move indexed to indexed syntax: movss [z s ], [z d ] operands: 0 ? z s ? 127 0 ? z d ? 127 operation: ((fsr2) + z s ) ? ((fsr2) + z d ) status affected: none encoding: 1st word (source) 2nd word (dest.) 1110 1111 1011 xxxx 1zzz xzzz zzzz s zzzz d description the contents of the source register are moved to the destination register. the addresses of the source and destination registers are determined by adding the 7-bit literal offsets ?z s ? or ?z d ?, respectively, to the value of fsr2. both registers can be located anywhere in the 4096-byte data memory space (000h to fffh). the movss instruction cannot use the pcl, tosu, tosh or tosl as the destination register. if the resultant source address points to an indirect addressing register, the value returned will be 00h. if the resultant destination address points to an indirect addressing register, the instruction will execute as a nop . words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode determine source addr determine source addr read source reg decode determine dest addr determine dest addr write to dest reg example : movss [05h], [06h] before instruction fsr2 = 80h contents of 85h = 33h contents of 86h = 11h after instruction fsr2 = 80h contents of 85h = 33h contents of 86h = 33h pushl store literal at fsr2, decrement fsr2 syntax: pushl k operands: 0 ??? k ? 255 operation: k ? (fsr2), fsr2 ? 1 ? fsr2 status affected: none encoding: 1111 1010 kkkk kkkk description: the 8-bit literal ?k? is written to the data memory address specified by fsr2. fsr2 is decremented by 1 after the operation. this instruction allows users to push values onto a software stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read ?k? process data write to destination example : pushl 08h before instruction fsr2h:fsr2l = 01ech memory (01ech) = 00h after instruction fsr2h:fsr2l = 01ebh memory (01ech) = 08h www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 451 pic18(l)f2x/45k50 subfsr subtract literal from fsr syntax: subfsr f, k operands: 0 ? k ? 63 f ? [ 0, 1, 2 ] operation: fsr(f) ? k ? fsrf status affected: none encoding: 1110 1001 ffkk kkkk description: the 6-bit literal ?k? is subtracted from the contents of the fsr specified by ?f?. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example : subfsr 2, 23h before instruction fsr2 = 03ffh after instruction fsr2 = 03dch subulnk subtract literal from fsr2 and return syntax: subulnk k operands: 0 ? k ? 63 operation: fsr2 ? k ? fsr2 (tos) ?? pc status affected: none encoding: 1110 1001 11kk kkkk description: the 6-bit literal ?k? is subtracted from the contents of the fsr2. a return is then executed by loading the pc with the tos. the instruction takes two cycles to execute; a nop is performed during the second cycle. this may be thought of as a special case of the subfsr instruction, where f = 3 (binary ? 11 ?); it operates only on fsr2. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination no operation no operation no operation no operation example : subulnk 23h before instruction fsr2 = 03ffh pc = 0100h after instruction fsr2 = 03dch pc = (tos) www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 452 ? 2012 microchip technology inc. 27.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode in addition to eight new commands in the extended set, enabling the extended instruction set also enables indexed literal offset addressing mode ( section 6.7.1 ?indexed addressing with literal offset? ). this has a significant impact on the way that many commands of the standard pic18 instruction set are interpreted. when the extended set is disabled, addresses embedded in opcodes are treated as literal memory locations: either as a location in the access bank (?a? = 0 ), or in a gpr bank designated by the bsr (?a? = 1 ). when the extended instruction set is enabled and ?a? = 0 , however, a file register argument of 5fh or less is interpreted as an offset from the pointer value in fsr2 and not as a literal address. for practical purposes, this means that all instructions that use the access ram bit as an argument ? that is, all byte-oriented and bit- oriented instructions, or almost half of the core pic18 instructions ? may behave differently when the extended instruction set is enabled. when the content of fsr2 is 00h, the boundaries of the access ram are essentially remapped to their original values. this may be useful in creating backward compatible code. if this technique is used, it may be necessary to save the value of fsr2 and restore it when moving back and forth between c and assembly routines in order to preserve the stack pointer. users must also keep in mind the syntax requirements of the extended instruction set (see section 27.2.3.1 ?extended instruction syntax with standard pic18 commands? ). although the indexed literal offset addressing mode can be very useful for dynamic stack and pointer manipulation, it can also be very annoying if a simple arithmetic operation is carried out on the wrong register. users who are accustomed to the pic18 programming must keep in mind that, when the extended instruction set is enabled, register addresses of 5fh or less are used for indexed literal offset addressing. representative examples of typical byte-oriented and bit-oriented instructions in the indexed literal offset addressing mode are provided on the following page to show how execution is affected. the operand condi- tions shown in the examples are applicable to all instructions of these types. 27.2.3.1 extended instruction syntax with standard pic18 commands when the extended instruction set is enabled, the file register argument, ?f?, in the standard byte-oriented and bit-oriented commands is replaced with the literal offset value, ?k?. as already noted, this occurs only when ?f? is less than or equal to 5fh. when an offset value is used, it must be indicated by square brackets (?[ ]?). as with the extended instructions, the use of brackets indicates to the compiler that the value is to be interpreted as an index or an offset. omitting the brackets, or using a value greater than 5fh within brackets, will generate an error in the mpasm assembler. if the index argument is properly bracketed for indexed literal offset addressing, the access ram argument is never specified; it will automatically be assumed to be ? 0 ?. this is in contrast to standard operation (extended instruction set disabled) when ?a? is set on the basis of the target address. declaring the access ram bit in this mode will also generate an error in the mpasm assembler. the destination argument, ?d?, functions as before. in the latest versions of the mpasm? assembler, language support for the extended instruction set must be explicitly invoked. this is done with either the command line option, /y , or the pe directive in the source listing. 27.2.4 considerations when enabling the extended instruction set it is important to note that the extensions to the instruc- tion set may not be beneficial to all users. in particular, users who are not writing code that uses a software stack may not benefit from using the extensions to the instruction set. additionally, the indexed literal offset addressing mode may create issues with legacy applications written to the pic18 assembler. this is because instructions in the legacy code may attempt to address registers in the access bank below 5fh. since these addresses are interpreted as literal offsets to fsr2 when the instruction set extension is enabled, the application may read or write to the wrong data addresses. when porting an application to the pic18(l)f2x/ 45k50, it is very important to consider the type of code. a large, re-entrant application that is written in ?c? and would benefit from efficient compilation will do well when using the instruction set extensions. legacy applications that heavily use the access bank will most likely not benefit from using the extended instruction set. note: enabling the pic18 instruction set extension may cause legacy applications to behave erratically or fail entirely. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 453 pic18(l)f2x/45k50 addwf add w to indexed (indexed literal offset mode) syntax: addwf [k] {,d} operands: 0 ? k ? 95 d ? [0,1] operation: (w) + ((fsr2) + k) ? dest status affected: n, ov, c, dc, z encoding: 0010 01d0 kkkk kkkk description: the contents of w are added to the contents of the register indicated by fsr2, offset by the value ?k?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read ?k? process data write to destination example : addwf [ofst] , 0 before instruction w = 17h ofst = 2ch fsr2 = 0a00h contents of 0a2ch = 20h after instruction w = 37h contents of 0a2ch = 20h bsf bit set indexed (indexed literal offset mode) syntax: bsf [k], b operands: 0 ? f ? 95 0 ? b ? 7 operation: 1 ? ((fsr2) + k) status affected: none encoding: 1000 bbb0 kkkk kkkk description: bit ?b? of the register indicated by fsr2, offset by the value ?k?, is set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example : bsf [flag_ofst], 7 before instruction flag_ofst = 0ah fsr2 = 0a00h contents of 0a0ah = 55h after instruction contents of 0a0ah = d5h setf set indexed (indexed literal offset mode) syntax: setf [k] operands: 0 ? k ? 95 operation: ffh ? ((fsr2) + k) status affected: none encoding: 0110 1000 kkkk kkkk description: the contents of the register indicated by fsr2, offset by ?k?, are set to ffh. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read ?k? process data write register example : setf [ofst] before instruction ofst = 2ch fsr2 = 0a00h contents of 0a2ch = 00h after instruction contents of 0a2ch = ffh www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 454 ? 2012 microchip technology inc. 27.2.5 special considerations with microchip mplab ? ide tools the latest versions of microchip?s software tools have been designed to fully support the extended instruction set of the pic18(l)f2x/45k50 family of devices. this includes the mplab c18 c compiler, mpasm assembly language and mplab integrated development environment (ide). when selecting a target device for software development, mplab ide will automatically set default configuration bits for that device. the default setting for the xinst configuration bit is ? 0 ?, disabling the extended instruction set and indexed literal offset addressing mode. for proper execution of applications developed to take advantage of the extended instruction set, xinst must be set during programming. to develop software for the extended instruction set, the user must enable support for the instructions and the indexed addressing mode in their language tool(s). depending on the environment being used, this may be done in several ways: ? a menu option, or dialog box within the environment, that allows the user to configure the language tool and its settings for the project ? a command line option ? a directive in the source code these options vary between different compilers, assemblers and development environments. users are encouraged to review the documentation accompanying their development systems for the appropriate information. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 455 pic18(l)f2x/45k50 28.0 development support the pic ? microcontrollers and dspic ? digital signal controllers are supported with a full range of software and hardware development tools: ? integrated development environment - mplab ? ide software ? compilers/assemblers/linkers - mplab c compiler for various device families - hi-tech c ? for various device families - mpasm tm assembler -mplink tm object linker/ mplib tm object librarian - mplab assembler/linker/librarian for various device families ? simulators - mplab sim software simulator ?emulators - mplab real ice? in-circuit emulator ? in-circuit debuggers - mplab icd 3 - pickit? 3 debug express ? device programmers - pickit? 2 programmer - mplab pm3 device programmer ? low-cost demonstration/development boards, evaluation kits, and starter kits 28.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. the mplab ide is a windows ? operating system-based application that contains: ? a single graphical interface to all debugging tools - simulator - programmer (sold separately) - in-circuit emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color-coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high-level source code debugging ? mouse over variable inspection ? drag and drop variables from source to watch windows ? extensive on-line help ? integration of select third party tools, such as iar c compilers the mplab ide allows you to: ? edit your source files (either c or assembly) ? one-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) ? debug using: - source files (c or assembly) - mixed c and assembly - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increased flexibility and power. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 456 ? 2012 microchip technology inc. 28.2 mplab c compilers for various device families the mplab c compiler code development systems are complete ansi c compilers for microchip?s pic18, pic24 and pic32 families of microcontrollers and the dspic30 and dspic33 families of digital signal control- lers. these compilers provide powerful integration capabilities, superior code optimization and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 28.3 hi-tech c for various device families the hi-tech c compiler code development systems are complete ansi c compilers for microchip?s pic family of microcontrollers and the dspic family of digital signal controllers. these compilers provide powerful integration capabilities, omniscient code generation and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. the compilers include a macro assembler, linker, pre- processor, and one-step driver, and can run on multiple platforms. 28.4 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for pic10/12/16/18 mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user-defined macros to streamline assembly code ? conditional assembly for multi-purpose source files ? directives that allow complete control over the assembly process 28.5 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c18 c compiler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 28.6 mplab assembler, linker and librarian for various device families mplab assembler produces relocatable machine code from symbolic assembly language for pic24, pic32 and dspic devices. mplab c compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: ? support for the entire device instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 457 pic18(l)f2x/45k50 28.7 mplab sim software simulator the mplab sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic ? dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab sim software simulator fully supports symbolic debugging using the mplab c compilers, and the mpasm and mplab assemblers. the soft- ware simulator offers the flexibility to develop and debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software development tool. 28.8 mplab real ice in-circuit emulator system mplab real ice in-circuit emulator system is microchip?s next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs pic ? flash mcus and dspic ? flash dscs with the easy-to-use, powerful graphical user interface of the mplab integrated development environment (ide), included with each kit. the emulator is connected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with in- circuit debugger systems (rj11) or with the new high- speed, noise tolerant, low-voltage differential signal (lvds) interconnection (cat5). the emulator is field upgradable through future firmware downloads in mplab ide. in upcoming releases of mplab ide, new devices will be supported, and new features will be added. mplab real ice offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 28.9 mplab icd 3 in-circuit debugger system mplab icd 3 in-circuit debugger system is micro- chip?s most cost effective high-speed hardware debugger/programmer for microchip flash digital sig- nal controller (dsc) and microcontroller (mcu) devices. it debugs and programs pic ? flash microcon- trollers and dspic ? dscs with the powerful, yet easy- to-use graphical user interface of mplab integrated development environment (ide). the mplab icd 3 in-circuit debugger probe is con- nected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with a connector compatible with the mplab icd 2 or mplab real ice systems (rj-11). mplab icd 3 supports all mplab icd 2 headers. 28.10 pickit 3 in-circuit debugger/ programmer and pickit 3 debug express the mplab pickit 3 allows debugging and program- ming of pic ? and dspic ? flash microcontrollers at a most affordable price point using the powerful graphical user interface of the mplab integrated development environment (ide). the mplab pickit 3 is connected to the design engineer?s pc using a full speed usb interface and can be connected to the target via an microchip debug (rj-11) connector (compatible with mplab icd 3 and mplab real ice). the connector uses two device i/o pins and the reset line to imple- ment in-circuit debugging and in-circuit serial pro- gramming?. the pickit 3 debug express include the pickit 3, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 458 ? 2012 microchip technology inc. 28.11 pickit 2 development programmer/debugger and pickit 2 debug express the pickit? 2 development programmer/debugger is a low-cost development tool with an easy to use inter- face for programming and debugging microchip?s flash families of microcontrollers. the full featured windows ? programming interface supports baseline (pic10f, pic12f5xx, pic16f5xx), midrange (pic12f6xx, pic16f), pic18f, pic24, dspic30, dspic33, and pic32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many microchip serial eeprom products. with microchip?s powerful mplab integrated development environment (ide) the pickit? 2 enables in-circuit debugging on most pic ? microcon- trollers. in-circuit-debugging runs, halts and single steps the program while the pic microcontroller is embedded in the application. when halted at a break- point, the file registers can be examined and modified. the pickit 2 debug express include the pickit 2, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software. 28.12 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various package types. the icsp? cable assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an mmc card for file storage and data applications. 28.13 demonstration/development boards, evaluation kits, and starter kits a wide variety of demonstration, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully func- tional systems. most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demon- stration/development board series of circuits, microchip has a line of evaluation kits and demonstration software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. also available are starter kits that contain everything needed to experience the specified device. this usually includes a single application and debug capability, all on one board. check the microchip web page ( www.microchip.com ) for the complete list of demonstration, development and evaluation kits. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 459 pic18(l)f2x/45k50 29.0 electrical characteristics absolute maximum ratings (?) ambient temperature under bias................................................................................................. ............. .-40c to +85c storage temperature ............................................................................................................ .................. -65c to +150c voltage on any pin with respect to v ss (except v dd , v usb 3 v 3 , d+, d- and mclr ) ....................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss pic18lf2x/45k50.................................................................................................... -0.3v to +4 .5v pic18f2x/45k50...................................................................................................... -0.3v to + 6.5v voltage on v usb 3 v 3 pin with respect to v ss ...........................................................................................-0.3v to +4.0v (3) voltage on d+ and d- pins with respect to v ss ........................................................................ -0.3v to (v usb 3 v 3 + 0.3v) voltage on mclr with respect to v ss (note 2) ............................................................................................0v to +11.0v total power dissipation (note 1) ............................................................................................................................... 1.0w maximum current out of v ss pin (-40c to +85c) .............................................................................................. 300 ma maximum current into v dd pin (-40c to +85c) ................................................................................................ 200 ma input clamp current, i ik (v i < 0 or v i > v dd ) ??????????????????????????????????????????????????????????????? ??????????????????????????????????????????????????????? ? 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ??????????????????????????????????????????????????????????????? ??????????????????????????????????????????????? ? 20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by ? all ports (-40c to +85c)........................................................................................... 200 ma maximum current sourced by all ports (-40c to +85c) .......................................................................... ............185 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd ? ? i oh } + ? {(v dd ? v oh ) x i oh } + ? (v ol x i ol ) 2: voltage spikes below v ss at the mclr /v pp /re3 pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 ? should be used when applying a ?low? level to the mclr /v pp / re3 pin, rather than pulling this pin directly to v ss . 3: v usb 3 v 3 must always be ? v dd + 0.3v. v usb 3 v 3 must also be maintained ? v dd - 0.3v on pic18lf2x/45k50 devices. ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 460 ? 2012 microchip technology inc. figure 29-1: pic18lf2x/45k50 family voltage-frequency graph (industrial temperature) figure 29-2: pic18f2x/45k50 family voltage-frequency graph (industrial temperature) frequency (mhz) voltage 3.6v 1.8v 3.0v 2.7v 2.3v 16 20 note 1: maximum frequency 4 mhz, 1.8v to 2.7v, -40c to +85c 2: maximum frequency 48 mhz, 2.7v to 3.6v, -40c to +85c 5.5v 5.0v 4.0v 48 4 frequency (mhz) voltage 3.6v 1.8v 3.0v 2.7v 2.3v 30 40 note 1: maximum frequency 20 mhz, 2.3v to 2.7v, -40c to +85c 2: maximum frequency 48 mhz, 2.7v to 5.5v, -40c to +85c 5.5v 5.0v 4.0v 48 20 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 461 pic18(l)f2x/45k50 29.1 dc characteristics: supply voltage, pic18(l)f2x/45k50 pic18(l)f2x/45k50 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c param no. symbol characteristic min typ max units conditions d001 v dd supply voltage pic18lf2x/45k50 1.8 ? 3.6 v regulator disabled pic18f2x/45k50 2.3 ? 5.5 v regulator enabled d001b v usb 3 v 3 usb supply voltage 3.0 3.3 3.6 v usb module enabled d001c d001d v usb 3 v 3 capacitor charging (pic18f2x/45k50) charging current ?200?a source/sink capability when charging is complete ?0.0?ma d002 v dr ram data retention voltage (1) 1.5 ? ? v d003 v por v dd start voltage to ensure internal power-on reset signal ? ? 0.7 v see section on power-on reset for details d004 s vdd v dd rise rate to ensure internal power-on reset signal 0.05 ? ? v/ms see section on power-on reset for details d005 v bor brown-out reset voltage borv<1:0> = 11 (2) 1.75 1.9 2.05 v borv<1:0> = 10 2.05 2.2 2.35 v borv<1:0> = 01 2.35 2.5 2.65 v borv<1:0> = 00 (3) 2.65 2.85 3.05 v d006 v lpbor low-power brown-ou t reset (lpbor) voltage 1.8v ? 2.1 v note 1: this is the limit to which v dd can be lowered in sleep mode, or during a device reset, without losing ram data. 2: on lf devices with bor enabled, operation is supported until a bor occurs. this is valid although v dd may be below the minimum rated supply voltage. 3: with bor enabled, full-speed operation (f osc = 48 mhz) is supported until a bor occurs. this is valid although v dd may be below the minimum voltage for this frequency. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 462 ? 2012 microchip technology inc. 29.2 dc characteristics: power-down current, pic18(l)f2x/45k50 pic18lf2x/45k50 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c pic18f2x/45k50 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c param no. device characteristics typ +25c typ +60c max +85c units conditions v dd notes power-down base current (ipd) (1) d006 sleep mode 0.01 0.04 2 ? a1.8v wdt, bor, fvr and sosc disabled, all peripherals inactive 0.01 0.06 2 ? a3.0v 12 13 25 ? a 2.3v 13 14 30 ? a 3.0v 13 14 35 ? a 5.0v power-down module differential current (delta ipd) d007 watchdog timer 0.3 0.3 2.5 ? a1.8v 0.5 0.5 2.5 ? a3.0v 0.35 0.35 5.0 ? a 2.3v 0.5 0.5 5.0 ? a 3.0v 0.5 0.5 5.0 ? a 5.0v d008 brown-out reset (2) 88.515 ? a2.0v 99.515 ? a3.0v 3.4 3.4 15 ? a 2.3v 3.8 3.8 15 ? a 3.0v 5.2 5.2 15 ? a 5.0v d010 high/low voltage detect (2) 6.5 6.7 15 ? a2.0v 77.515 ? a3.0v 2.1 2.1 15 ? a 2.3v 2.4 2.4 15 ? a 3.0v 3.2 3.2 15 ? a 5.0v d011 secondary oscillator 0.5 1 3 ? a1.8v 32 khz on sosc 0.6 1.1 4 ? a3.0v 0.5 1 3 ? a 2.3v 0.6 1.1 4 ? a 3.0v 0.6 1.1 5 ? a 5.0v note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: on lf devices, the bor, hlvd and fvr enable internal band gap reference. with more than one of these modules enabled, the current consumption will be less than the sum of the specifications. on f devices, the internal band gap reference is always enabled and its current consumption is included in the power- down base current (i pd ). 3: a/d converter differential currents apply only in run mode. in sleep or idle mode both the adc and the frc turn off as soon as conversion (if any) is complete. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 463 pic18(l)f2x/45k50 d015 comparators 7718 ? a1.8v lp mode 7718 ? a3.0v 7 7 18 ? a 2.3v 7 7 18 ? a 3.0v 8 8 20 ? a 5.0v d16 comparators 38 38 95 ? a1.8v hp mode 40 40 105 ? a3.0v 39 39 95 ? a 2.3v 40 40 105 ? a 3.0v 40 40 105 ? a 5.0v d017 dac 12 12 22 ? a1.8v 20 20 35 ? a3.0v 15 15 30 ? a 2.3v 20 20 35 ? a 3.0v 32 32 60 ? a 5.0v d018 fvr (2) 15 16 25 ? a1.8v 15 16 25 ? a3.0v 28 28 45 ? a 2.3v 31 31 55 ? a 3.0v 66 66 100 ? a 5.0v d013 a/d converter (3) 185 185 370 ? a1.8v a/d on, not converting 210 210 400 ? a3.0v 200 200 380 ? a 2.3v 210 210 400 ? a 3.0v 250 250 450 ? a 5.0v 29.2 dc characteristics: power-down current, pic18(l)f2x/45k50 (continued) pic18lf2x/45k50 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c pic18f2x/45k50 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c param no. device characteristics typ +25c typ +60c max +85c units conditions v dd notes note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: on lf devices, the bor, hlvd and fvr enable internal band gap reference. with more than one of these modules enabled, the current consumption will be less than the sum of the specifications. on f devices, the internal band gap reference is always enabled and its current consumption is included in the power- down base current (i pd ). 3: a/d converter differential currents apply only in run mode. in sleep or idle mode both the adc and the frc turn off as soon as conversion (if any) is complete. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 464 ? 2012 microchip technology inc. 29.3 dc characteristics: rc run supply current, pic18(l)f2x/45k50 pic18lf2x/45k50 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c pic18f2x/45k50 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c param no. device characteristics typ max units conditions d020 supply current (i dd ) (1),(2) 3.6 23 ? a-40c v dd = 1.8v f osc = 31 khz ( rc_run mode, intrc source) 3.9 25 ? a +25c 3.9 ? ? a +60c 3.9 28 ? a +85c d021 8.1 26 ? a-40c v dd = 3.0v 8.4 30 ? a +25c 8.6 ? ? a +60c 8.7 35 ? a +85c d022 16 35 ? a -40c v dd = 2.3v f osc = 31 khz ( rc_run mode, intrc source) 17 35 ? a +25c 18 35 ? a +85c d023 18 50 ? a -40c v dd = 3.0v 20 50 ? a +25c 21 50 ? a +85c d024 19 55 ? a -40c v dd = 5.0v 21 55 ? a +25c 22 55 ? a +85c note 1: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. test condition: all peripheral module control bits in pmd0 and pmd1 set to ? 1 ?. 2: the test conditions for all i dd measurements in active operation mode are: all i/o pins set as outputs driven to vss; mclr = v dd ; osc1 = external square wave, from rail-to-rail (pri_run and pri_idle only). www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 465 pic18(l)f2x/45k50 d030 0.35 0.50 ma -40c to +85c v dd = 1.8v f osc = 1 mhz ( rc_run mode, hfintosc source) d031 0.45 0.65 ma -40c to +85c v dd = 3.0v d032 0.40 0.60 ma -40c to +85c v dd = 2.3v f osc = 1 mhz ( rc_run mode, hfintosc source) d033 0.50 0.65 ma -40c to +85c v dd = 3.0v d034 0.55 0.75 ma -40c to +85c v dd = 5.0v d035 1.3 2.0 ma -40c to +85c v dd = 1.8v f osc = 16 mhz ( rc_run mode, hfintosc source) d036 2.2 3.0 ma -40c to +85c v dd = 3.0v d037 1.7 2.0 ma -40c to +85c v dd = 2.3v f osc = 16 mhz ( rc_run mode, hfintosc source) d038 2.2 3.0 ma -40c to +85c v dd = 3.0v d039 2.5 3.5 ma -40c to +85c v dd = 5.0v d041 6.2 8.5 ma -40c to +85c v dd = 3.0v f osc = 48 mhz ( rc_run mode, hfintosc + pll source) d043 6.2 8.5 ma -40c to +85c v dd = 3.0v f osc = 48 mhz ( rc_run mode, hfintosc + pll source) d044 6.8 9.5 ma -40c to +85c v dd = 5.0v 29.3 dc characteristics: rc run supply current, pic18(l)f2x/45k50 (continued) pic18lf2x/45k50 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c pic18f2x/45k50 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c param no. device characteristics typ max units conditions note 1: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. test condition: all peripheral module control bits in pmd0 and pmd1 set to ? 1 ?. 2: the test conditions for all i dd measurements in active operation mode are: all i/o pins set as outputs driven to vss; mclr = v dd ; osc1 = external square wave, from rail-to-rail (pri_run and pri_idle only). www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 466 ? 2012 microchip technology inc. 29.4 dc characteristics: rc idle supply current, pic18(l)f2x/45k50 pic18lf2x/45k50 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c pic18f2x/45k50 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c param no. device characteristics typ max units conditions d045 supply current (i dd ) (1),(2) 0.5 18 ? a -40c v dd = 1.8v f osc = 31 khz ( rc_idle mode, intrc source) 0.6 18 ? a+25c 0.7 ? ? a+60c 0.75 20 ? a+85c d046 1.1 20 ? a -40c v dd = 3.0v 1.2 20 ? a+25c 1.3 ? ? a+60c 1.4 22 ? a+85c d047 17 30 ? a -40c v dd = 2.3v f osc = 31 khz ( rc_idle mode, intrc source) 13 30 ? a +25c 14 30 ? a +85c d048 19 35 ? a -40c v dd = 3.0v 15 35 ? a +25c 16 35 ? a +85c d049 21 40 ? a -40c v dd = 5.0v 15 40 ? a +25c 16 40 ? a +85c note 1: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. test condition: all peripheral module control bits in pmd0 and pmd1 set to ? 1 ?. 2: the test conditions for all i dd measurements in active operation mode are: all i/o pins set as outputs driven to vss; mclr = v dd ; osc1 = external square wave, from rail-to-rail (pri_run and pri_idle only). www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 467 pic18(l)f2x/45k50 d055 0.25 0.40 ma -40c to +85c v dd = 1.8v f osc = 1 mhz ( rc_idle mode, hfintosc source) d056 0.35 0.50 ma -40c to +85c v dd = 3.0v d057 0.30 0.45 ma -40c to +85c v dd = 2.3v f osc = 1 mhz ( rc_idle mode, hfintosc source) d058 0.40 0.50 ma -40c to +85c v dd = 3.0v d059 0.45 0.60 ma -40c to +85c v dd = 5.0v d060 0.50 0.7 ma -40c to +85c v dd = 1.8v f osc = 16 mhz ( rc_idle mode, hfintosc source) d061 0.80 1.1 ma -40c to +85c v dd = 3.0v d062 0.65 1.0 ma -40c to +85c v dd = 2.3v f osc = 16 mhz ( rc_idle mode, hfintosc source) d063 0.80 1.1 ma -40c to +85c v dd = 3.0v d064 0.95 1.2 ma -40c to +85c v dd = 5.0v d066 2.5 3.5 ma -40c to +85c v dd = 3.0v f osc = 48 mhz ( rc_idle mode, hfintosc + pll source) d068 2.5 3.5 ma -40c to +85c v dd = 3.0v f osc = 48 mhz ( rc_idle mode, hfintosc + pll source) d069 3.0 4.5 ma -40c to +85c v dd = 5.0v 29.4 dc characteristics: rc idle supply current, pic18(l)f2x/45k50 (continued) pic18lf2x/45k50 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c pic18f2x/45k50 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c param no. device characteristics typ max units conditions note 1: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. test condition: all peripheral module control bits in pmd0 and pmd1 set to ? 1 ?. 2: the test conditions for all i dd measurements in active operation mode are: all i/o pins set as outputs driven to vss; mclr = v dd ; osc1 = external square wave, from rail-to-rail (pri_run and pri_idle only). www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 468 ? 2012 microchip technology inc. 29.5 dc characteristics: primary run supply current, pic18(l)f2x/45k50 pic18lf2x/45k50 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c pic18f2x/45k50 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c param no. device characteristics typ max units conditions d070 supply current (i dd ) (1),(2) 0.11 0.20 ma -40c to +85c v dd = 1.8v f osc = 1 mhz ( pri_run mode, ecm source) d071 0.17 0.25 ma -40c to +85c v dd = 3.0v d072 0.15 0.25 ma -40c to +85c v dd = 2.3v f osc = 1 mhz ( pri_run mode, ecm source) d073 0.20 0.30 ma -40c to +85c v dd = 3.0v d074 0.25 0.35 ma -40c to +85c v dd = 5.0v d075 1.45 2.0 ma -40c to +85c v dd = 1.8v f osc = 20 mhz ( pri_run mode, ech source) d076 2.60 3.5 ma -40c to +85c v dd = 3.0v d077 1.95 2.5 ma -40c to +85c v dd = 2.3v f osc = 20 mhz ( pri_run mode, ech source) d078 2.65 3.5 ma -40c to +85c v dd = 3.0v d079 2.95 4.5 ma -40c to +85c v dd = 5.0v d080 7.5 10 ma -40c to +85c v dd = 3.0v f osc = 48 mhz ( pri_run , ech oscillator) d081 7.5 10 ma -40c to +85c v dd = 3.0v f osc = 48 mhz ( pri_run mode, ech source) d082 8.5 11.5 ma -40c to +85c v dd = 5.0v d083 1.0 1.5 ma -40c to +85c v dd = 1.8v f osc = 4 mhz 16 mhz internal ( pri_run mode, ecm + pll source) d084 1.8 3.0 ma -40c to +85c v dd = 3.0v d085 1.4 2.0 ma -40c to +85c v dd = 2.3v f osc = 4 mhz 16 mhz internal ( pri_run mode, ecm + pll source) d086 1.85 2.5 ma -40c to +85c v dd = 3.0v d087 2.1 3.0 ma -40c to +85c v dd = 5.0v d088 6.35 9.0 ma -40c to +85c v dd = 3.0v f osc = 16 mhz 48 mhz internal ( pri_run mode, ech + pll source) d089 6.35 9.0 ma -40c to +85c v dd = 3.0v f osc = 16 mhz 48 mhz internal ( pri_run mode, ech + pll source) d090 7.0 10 ma -40c to +85c v dd = 5.0v note 1: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. test condition: all peripheral module control bits in pmd0 and pmd1 set to ? 1 ?. 2: the test conditions for all i dd measurements in active operation mode are: all i/o pins set as outputs driven to vss; mclr = v dd ; osc1 = external square wave, from rail-to-rail (pri_run and pri_idle only). www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 469 pic18(l)f2x/45k50 29.6 dc characteristics: primary idle supply current, pic18(l)f2x/45k50 pic18lf2x/45k50 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c pic18f2x/45k50 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c param no. device characteristics typ max units conditions d100 supply current (i dd ) (1),(2) 0.030 0.050 ma -40c to +85c v dd = 1.8v fosc = 1 mhz ( pri_idle mode, ecm source) d101 0.045 0.065 ma -40c to +85c v dd = 3.0v d102 0.06 0.12 ma -40c to +85c v dd = 2.3v fosc = 1 mhz ( pri_idle mode, ecm source) d103 0.08 0.15 ma -40c to +85c v dd = 3.0v d104 0.13 0.20 ma -40c to +85c v dd = 5.0v d105 0.45 0.8 ma -40c to +85c v dd = 1.8v fosc = 20 mhz ( pri_idle mode, ech source) d106 0.70 1.0 ma -40c to +85c v dd = 3.0v d107 0.55 0.8 ma -40c to +85c v dd = 2.3v fosc = 20 mhz ( pri_idle mode, ech source) d108 0.75 1.0 ma -40c to +85c v dd = 3.0v d109 0.90 1.2 ma -40c to +85c v dd = 5.0v d110 2.25 3.0 ma -40c to +85c v dd = 3.0v fosc = 48 mhz ( pri_idle mode, ech source) d111 2.25 3.0 ma -40c to +85c v dd = 3.0v fosc = 48 mhz ( pri_idle mode, ech source) d112 2.60 3.5 ma -40c to +85c v dd = 5.0v d113 0.35 0.6 ma -40c to +85c v dd = 1.8v fosc = 4 mhz 16 mhz internal ( pri_idle mode, ecm + pll source) d114 0.55 0.8 ma -40c to +85c v dd = 3.0v d115 0.45 0.6 ma -40c to +85c v dd = 2.3v fosc = 4 mhz 16 mhz internal ( pri_idle mode, ecm + pll source) d116 0.60 0.9 ma -40c to +85c v dd = 3.0v d117 0.70 1.0 ma -40c to +85c v dd = 5.0v d118 2.2 3.0 ma -40c to +85c v dd = 3.0v fosc = 16 mhz 48 mhz internal ( pri_idle mode, ech + pll source) d119 2.2 3.0 ma -40c to +85c v dd = 3.0v fosc = 16 mhz 48 mhz internal ( pri_idle mode, ech + pll source) d120 2.5 3.5 ma -40c to +85c v dd = 5.0v note 1: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. test condition: all peripheral module control bits in pmd0 and pmd1 set to ? 1 ?. 2: the test conditions for all i dd measurements in active operation mode are: all i/o pins set as outputs driven to vss; mclr = v dd ; osc1 = external square wave, from rail-to-rail (pri_run and pri_idle only). www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 470 ? 2012 microchip technology inc. . 29.7 dc characteristics: secondary oscillator supply current, pic18(l)f2x/45k50 pic18lf2x/45k50 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c pic18f2x/45k50 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c param no. device characteristics typ max units conditions d130 supply current (i dd ) (1),( 2) 3.5 23 ? a -40c v dd = 1.8v fosc = 32 khz ( sec_run mode, sosc source) 3.7 25 ? a+25c 3.8 ? ? a+60c 4.0 28 ? a+85c d131 6.2 26 ? a -40c v dd = 3.0v 6.4 30 ? a+25c 6.5 ? ? a+60c 6.8 35 ? a+85c d132 15 35 ? a -40c v dd = 2.3v fosc = 32 khz ( sec_run mode, sosc source) 16 35 ? a +25c 17 35 ? a +85c d133 18 50 ? a -40c v dd = 3.0v 19 50 ? a +25c 21 50 ? a +85c d134 19 55 ? a -40c v dd = 5.0v 20 55 ? a +25c 22 55 ? a +85c note 1: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. test condition: all peripheral module control bits in pmd0 and pmd1 set to ? 1 ?. 2: the test conditions for all i dd measurements in active operation mode are: all i/o pins set as outputs driven to vss; mclr = v dd ; sosci / sosco = complementary external square wave, from rail-to-rail. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 471 pic18(l)f2x/45k50 d135 0.9 18 ? a -40c v dd = 1.8v fosc = 32 khz ( sec_idle mode, sosc source) 1.0 18 ? a+25c 1.1 ? ? a+60c 1.3 20 ? a+85c d136 1.3 20 ? a -40c v dd = 3.0v 1.4 20 ? a+25c 1.5 ? ? a+60c 1.8 22 ? a+85c d137 12 30 ? a -40c v dd = 2.3v fosc = 32 khz ( sec_idle mode, sosc source) 13 30 ? a +25c 14 30 ? a +85c d138 13 35 ? a -40c v dd = 3.0v 14 35 ? a +25c 16 35 ? a +85c d139 14 40 ? a -40c v dd = 5.0v 15 40 ? a +25c 16 40 ? a +85c 29.7 dc characteristics: secondary oscillator supply current, pic18(l)f2x/45k50 pic18lf2x/45k50 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c pic18f2x/45k50 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c param no. device characteristics typ max units conditions note 1: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. test condition: all peripheral module control bits in pmd0 and pmd1 set to ? 1 ?. 2: the test conditions for all i dd measurements in active operation mode are: all i/o pins set as outputs driven to vss; mclr = v dd ; sosci / sosco = complementary external square wave, from rail-to-rail. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 472 ? 2012 microchip technology inc. 29.8 dc characteristics:input/output characteristics, pic18(l)f2x/45k50 dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ? +85c param no. symbol characteristic min typ? max units conditions v il input low voltage i/o port: d140 with ttl buffer ? ? 0.8 v 4.5v ? v dd ? 5.5v d140a ? ? 0.15 v dd v1.8v ? v dd ? 4.5v d141 with schmitt trigger buffer ??0.2v dd v2.0v ? v dd ? 5.5v with i 2 c? levels ? ? 0.3 v dd v with smbus levels ? ? 0.8 v 2.7v ? v dd ? 5.5v d142 mclr , osc1 (rc mode) (1) ??0.2v dd v d142a osc1 (hs mode) ? ? 0.3 v dd v v ih input high voltage i/o ports: ? ? d147 with ttl buffer 2.0 ? ? v 4.5v ? v dd ?? 5.5v d147a 0.25 v dd + 0.8 ??v1.8v ? v dd ? 4.5v d148 with schmitt trigger buffer 0.8 v dd ??v2.0v ? v dd ? 5.5v with i 2 c? levels 0.7 v dd ??v with smbus levels 2.1 ? ? v 2.7v ? v dd ? 5.5v d149 mclr 0.8 v dd ??v d150a osc1 (hs mode) 0.7 v dd ??v d150b osc1 (rc mode) (1) 0.9 v dd ??v i il input leakage i/o and mclr (2),(3) v ss ?? v pin ?? v dd , pin at high-impedance d155 i/o ports and mclr ? ? ? 0.1 0.7 4 50 100 200 na na na ?? +25c (4) +60c +85c i pu weak pull-up current (4) d158 i purb portb weak pull-up current 25 25 85 130 200 300 ? a ? a v dd = 3.3v, v pin = v ss v dd = 5.0v, v pin = v ss note 1: in rc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic ? device be driven with an external clock while in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: parameter is characterized but not tested. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 473 pic18(l)f2x/45k50 v ol output low voltage d159 i/o ports ??0.6v i ol = 8 ma, v dd = 5v i ol = 6 ma, v dd = 3.3v i ol = 1.8 ma, v dd = 1.8v v oh output high voltage (3) d161 i/o ports v dd - 0.7 ? ? v i oh = 3.5 ma, v dd = 5v i oh = 3 ma, v dd = 3.3v i oh = 1 ma, v dd = 1.8v 29.8 dc characteristics:input/output characteristics, pic18(l)f2x/45k50 (continued) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ? +85c param no. symbol characteristic min typ? max units conditions note 1: in rc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic ? device be driven with an external clock while in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: parameter is characterized but not tested. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 474 ? 2012 microchip technology inc. 29.9 memory programming requirements dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c param no. sym characteristic min typ? max units conditions internal program memory programming specifications (1) d170 v pp voltage on mclr /v pp pin 8 ? 9 v (note 3), (note 4) d171 i ddp supply current during programming ??10ma data eeprom memory d172 e d byte endurance 100k ? ? e/w -40 ? c to +85 ? c d173 v drw v dd for read/write v ddmin ? v ddmax v using eecon to read/ write d175 t dew erase/write cycle time ? 3 4 ms d176 t retd characteristic retention ? 40 ? year provided no other specifications are violated d177 t ref number of total erase/write cycles before refresh (2) 1m 10m ? e/w -40c to +85c program flash memory d178 e p cell endurance 10k ? ? e/w -40 ? c to +85 ? c (note 5) d179 v pr v dd for read v ddmin ? v ddmax v d181 v iw v dd for row erase or write 2.2 ? v ddmax v pic18lf2x/45k50 d182 v iw v ddmin ? v ddmax v pic18f2x/45k50 d183 t iw self-timed write cycle time ? 2 ? ms d184 t retd characteristic retention ? 40 ? year provided no other specifications are violated ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: these specifications are for programming the on-chip program memory through the use of table write instructions. 2: refer to section 8.8 ?using the data eeprom? for a more detailed discussion on data eeprom endurance. 3: required only if single-supply programming is disabled. 4: the mplab icd 2 does not support variable v pp output. circuitry to limit the icd 2 v pp voltage must be placed between the icd 2 and target system when programming or debugging with the icd 2. 5: self-write and block erase. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 475 pic18(l)f2x/45k50 29.10 usb module specifications operating conditions-40c ? t a ? +85c (unless otherwise state) param no. sym characteristic min typ max units conditions d313 v usb usb voltage 3.0 ? 3.6 v voltage on v usb 3 v 3 pin must be in this range for proper usb operation d314 i il input leakage on pin ? ? 1 ? av ss ?? v pin ?? v dd pin at ? high ? impedance d315 v ilusb input low voltage for usb buffer ??0.8vfor v usb 3 v 3 range d316 v ihusb input high voltage for usb buffer 2.0 ? ? v for v usb 3 v 3 range d318 v difs differential input sensitivity ? ? 0.2 v the difference between d+ and d- must exceed this value while v cm is met d319 v cm differential common mode range 0.8 ? 2.5 v d320 z out driver output impedance (1) 28 ? 44 ? d321 v ol voltage output low 0.0 ? 0.3 v 1.5 k ?? load connected to 3.6v d322 v oh voltage output high 2.8 ? 3.6 v 1.5 k ?? load connected to ground note 1: the d+ and d- signal lines have been built-in impedance matching resistors. no external resistors, capacitors or magnetic components are necessary on the d+/d- signal paths between the pic18(l)f2x/ 45k50 family device and usb cable. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 476 ? 2012 microchip technology inc. 29.11 analog characteristics table 29-1: comparator specifications operating conditions: 1.8v < vdd < 5.5v, -40c < ta < +85c (unless otherwise stated) param no. sym characteristics min typ max units comments cm01 v ioff input offset voltage ? 3 30 mv high-power mode v ref = v dd /2 ? 4 40 mv low-power mode v ref = v dd /2 cm02 v icm input common-mode voltage v ss ?v dd v cm04* t resp response time (1) ? 200 400 ns high-power mode ? 600 3500 ns low-power mode cm05* t mc 2 ov comparator mode change to output valid ?? 10 ? s * these parameters are characterized but not tested. note 1: response time measured with one comparator input at v dd /2, while the other input transitions from v ss to v dd . table 29-2: digital-to-analog converter (dac) specifications operating conditions: 2.0v < v dd < 5.5v, -40c < t a < +85c (unless otherwise stated) param no. sym characteristics min typ max units comments cv01* c lsb step size (2) ?v dd /32 ? v cv02* c acc absolute accuracy ? ? ?? 1/2 lsb ? v src ?? 2.0v cv03* c r unit resistor value (r) ? 5k ? ? cv04* c st settling time (1) ??10 ? s cv05* v src + dac positive reference v src - +2 ? v dd v cv06* v src - dac negative reference v ss ?v src + -2 v cv07* ? v src dac reference range (v src + - v src -) 2?v dd v * these parameters are characterized but not tested. note 1: settling time measured while cvrr = 1 and cvr3:cvr0 transitions from ? 0000 ? to ? 1111 ?. 2: see section 23.0 ?digital-to-analog converter (dac) module? for more information. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 477 pic18(l)f2x/45k50 figure 29-3: high/low-volta ge detect characteristics table 29-3: fixed voltage reference (fvr) specifications operating conditions: -40c < ta < +85c (unless otherwise stated) param no. sym characteristics min typ max units comments vr01 v rout vr voltage output to adc 0.973 1.024 1.085 v 1x output, v dd ?? 2.5v 1.946 2.048 2.171 v 2x output, v dd ?? 2.5v 3.891 4.096 4.342 v 4x output, v dd ?? 4.75v (pic18f2x/45k50) vr02 v rout vr voltage output all other modules 0.942 1.024 1.096 v 1x output, v dd ?? 2.5v 1.884 2.048 2.191 v 2x output, v dd ?? 2.5v 3.768 4.096 4.383 v 4x output, v dd ?? 4.75v (pic18f2x/45k50) vr04* t stable settling time ? 25 100 ? s 0 to 85c * these parameters are characterized but not tested. table 29-4: charge time measurement unit (ctmu) specifications operating conditions: 1.8v < vdd < 5.5v, -40c < ta < +85c (unless otherwise stated) param no. sym characteristics min typ (1) max units comments ct01 i out 1 ctmu current source, base range ?0.55? ? airng<1:0> = 01 ct02 i out 2 ctmu current source, 10x range ?5.5? ? airng<1:0> = 10 ct03 i out 3 ctmu current source, 100x range ?55? ? airng<1:0> = 11 v dd ? 3.0v note 1: nominal value at center point of current trim range (ctmuicon<7:2> = 000000 ). v hlvd hlvdif v dd (hlvdif set by hardware) (hlvdif can be cleared by software) www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 478 ? 2012 microchip technology inc. table 29-5: high/low-volt age detect characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c param no. symbol characteristic hlvdl<3:0> min typ? max units conditions hlvd voltage on v dd transition high-to- low 0000 1.69 1.84 1.99 v 0001 1.92 2.07 2.22 v 0010 2.08 2.28 2.48 v 0011 2.24 2.44 2.64 v 0100 2.34 2.54 2.74 v 0101 2.54 2.74 2.94 v 0110 2.62 2.87 3.12 v 0111 2.76 3.01 3.26 v 1000 3.00 3.30 3.60 v 1001 3.18 3.48 3.78 v 1010 3.44 3.69 3.94 v 1011 3.66 3.91 4.16 v 1100 3.90 4.15 4.40 v 1101 4.11 4.41 4.71 v 1110 4.39 4.74 5.09 v 1111 v(hlvdin pin) v ? production tested at t amb = 25c. specifications over temperature limits ensured by characterization. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 479 pic18(l)f2x/45k50 29.12 ac (timing) characteristics 29.12.1 timing parameter symbology the timing parameter symbols have been created using one of the following formats: 1. tpps2pps 3. t cc : st (i 2 c? specifications only) 2. tpps 4. ts (i 2 c specifications only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clko rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t13cki mc mclr wr wr uppercase letters and their meanings: s f fall p period hhigh rrise i invalid (high-impedance) v valid l low z high-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c specifications only) cc hd hold su setup st dat data input hold sto stop condition sta start condition www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 480 ? 2012 microchip technology inc. 29.12.2 timing conditions the temperature and voltages specified in tab l e 2 9- 6 apply to all timing specifications unless otherwise noted. figure 29-4 specifies the load conditions for the timing specifications. table 29-6: temperature and voltage specifications ? ac figure 29-4: load conditions for de vice timing specifications ac characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ?? +85c operating voltage v dd range as described in section 29.1 ?dc characteristics: supply voltage, pic18(l)f2x/45k50? and section 29.9 ?memory programming requirements? . v dd /2 c l r l pin pin v ss v ss c l r l =464 ? c l = 50 pf for all pins except osc2/clko and including d and e outputs as ports load condition 1 load condition 2 legend : www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 481 pic18(l)f2x/45k50 29.12.3 timing diagrams and specifications figure 29-5: external clock timing (all modes exce pt pll) osc1 clko q4 q1 q2 q3 q4 q1 1 2 3 3 4 4 table 29-7: external clock timing requirements param. no. symbol characteristic min max units conditions 1a f osc external clkin frequency (1) dc dc dc 4 16 48 mhz mhz mhz ec, ecio oscillator mode (low power) ec, ecio oscillator mode (medium power) ec, ecio oscillator mode (high power) oscillator frequency (1) dc 4 mhz rc oscillator mode 5 200 khz lp oscillator mode 0.1 4 mhz xt oscillator mode 4 4 mhz hs oscillator mode, v dd < 2.7v 4 16 mhz hs oscillator mode, v dd ?? 2.7v, medium-power mode (hsmp) 4 20 mhz hs oscillator mode, v dd ?? 2.7v, high-power mode (hshp) 1t osc external clkin period (1) 0.25 62.5 20.8 ? ? ? ? s ns ns ec, ecio oscillator mode (low power) ec, ecio oscillator mode (medium power) ec, ecio oscillator mode (high power) oscillator period (1) 250 ? ns rc oscillator mode 5 200 ? s lp oscillator mode 0.25 250 10 250 ? s ns xt oscillator mode hs oscillator mode, v dd < 2.7v 62.5 250 ns hs oscillator mode, v dd ?? 2.7v, medium-power mode (hsmp) 50 250 ns hs oscillator mode, v dd ?? 2.7v, high-power mode (hshp) 2t cy instruction cycle time (1) 83.3 ? ns t cy = 4/f osc 3t os l, t os h external clock in (osc1) high or low time 2.5 ? ? s lp oscillator mode 30 ? ns xt oscillator mode 10 ? ns hs oscillator mode 4t os r, t os f external clock in (osc1) rise or fall time ? 50 ns lp oscillator mode ? 20 ns xt oscillator mode ? 7.5 ns hs oscillator mode note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period for all configurations except pll. all specified values are based on characterization data for that particular oscillator type under standard operating condi- tions with the device executing code. exceeding these specif ied limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?min.? values with an external clock applied to the osc1/clkin pin. when an external cloc k input is used, the ?max.? cycle time limit is ?dc? (no clock) for all devices. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 482 ? 2012 microchip technology inc. table 29-8: pll clock timing specifications param. no. sym characteristic min max units conditions f10 f osc 4xpll oscillator frequency range 4 5 mhz v dd < 2.7v, -40c to +85c 412mhz 2.7v ? v dd , -40c to +85c f10b f osc 3xpll oscillator frequency range 4 4 mhz 2.7v ? v dd , -40c to +85c f11 f sys on-chip vco system frequency 16 20 mhz v dd < 2.7v, -40c to +85c 16 48 mhz 2.7v ? v dd , -40c to +85c f12 t rc pll start-up time (lock time) ? 2 ms table 29-9: ac characteristics:internal oscillators accuracy (pic18(l)f2x/45k50) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c param. no. min typ max units conditions oa1 hf-intosc accuracy (1) -2 1 +2 % +0c to +70c -3 ? +2 % +70c to +85c -5 ? +5 % -40c to 85c oa1b hf-intosc accuracy with active clock tuning (act) -0.20 0.05 +0.20 % -40c to +85c (2) , active clock tune is enabled and locked. oa1c osctune step size tbd tbd tbd % oa2 intrc accuracy @ freq = 31 khz 26.5625 ? 35.9375 khz -40c to +85c legend: tbd = to be determined. note 1: frequency calibrated at 25c. osctune register can be used to compensate for temperature drift. 2: accuracy measured with respect to reference source. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 483 pic18(l)f2x/45k50 figure 29-6: clko and i/o timing note: refer to figure 29-4 for load conditions. osc1 clko i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value table 29-10: clko and i/ o timing requirements param. no. symbol characteristic min typ max units conditions 10 tosh2ckl osc1 ? to clko ? ? 75 200 ns (note 1) 11 tosh2ckh osc1 ? to clko ? ? 75 200 ns (note 1) 12 tckr clko rise time ? 35 100 ns (note 1) 13 tckf clko fall time ? 35 100 ns (note 1) 14 tckl2iov clko ? to port out valid ? ? 0.5 t cy + 20 ns (note 1) 15 tiov2ckh port in valid before clko ? 0.25 t cy + 25 ? ? ns (note 1) 16 tckh2ioi port in hold after clko ? 0??ns (note 1) 17 tosh2iov osc1 ? (q1 cycle) to port out valid ? 50 150 ns 18 tosh2ioi osc1 ? (q2 cycle) to port input invalid (i/o in hold time) 100 ? ? ns 19 tiov2osh port input valid to osc1 ?? (i/o in setup time) 0 ? ? ns 20 tior port output rise time ? ? 40 15 72 32 ns ns v dd = 1.8v v dd = 3.3v - 5.0v 21 tiof port output fall time ? ? 28 15 55 30 ns ns v dd = 1.8v v dd = 3.3v - 5.0v 22? t inp intx pin high or low time 20 ? ? ns 23? t rbp rb<7:4> change kbix high or low time t cy ??ns ? these parameters are asynchr onous events not related to any internal clock edges. note 1: measurements are taken in rc m ode, where clko output is 4 x t osc . www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 484 ? 2012 microchip technology inc. figure 29-7: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 29-8: brown-out r eset timing v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 29-4 for load conditions. v dd bv dd 35 v bgap = 1.2v v ivrst enable internal internal reference 36 reference voltage voltage stable www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 485 pic18(l)f2x/45k50 note 1: minimum pulse width that will consistently trigger a reset or interrupt. shorter pulses may in termittently trigger a response. figure 29-9: timer0 and timer1 external clock timings table 29-11: reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements param. no. symbol characteristic min typ max units conditions 30 tmcl mclr pulse width (low) 2 ? ? ? s 31 t wdt watchdog timer time-out period (no postscaler) 3.5 4.1 4.7 ms 1:1 prescaler 32 t ost oscillation start-up timer period 1024 t osc ? 1024 t osc ?t osc = osc1 period 33 t pwrt power-up timer period 54.8 64.4 74.1 ms 34 t ioz i/o high-impedance from mclr low or watchdog timer reset ?2? ? s 35 t bor brown-out reset pulse width 200 1 ?? ? sv dd ? b vdd (see d005 ) 36 t ivrst internal reference voltage stable ? 25 35 ? s 37 t hlvd high/low-voltage detect pulse width 200 1 ?? ? sv dd ? v hlvd 38 t csd cpu start-up time 5 ? 10 ? s 39 t iobst time for hf-intosc to stabilize ? 0.25 1 ms note: refer to figure 29-4 for load conditions. 46 47 45 48 41 42 40 t0cki t1cki/t3cki tmr0 or tmr1 www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 486 ? 2012 microchip technology inc. figure 29-10: capture/compare/pwm timings (all ccp modules) table 29-12: timer0 and timer1/3 external clock requirements param. no. symbol characteristic min max units conditions 40 tt0h t0cki high pulse width no prescaler 0.5 t cy + 20 ? ns with prescaler 10 ? ns 41 tt0l t0cki low pulse width no prescaler 0.5 t cy + 20 ? ns with prescaler 10 ? ns 42 tt0p t0cki period no prescaler t cy + 10 ? ns with prescaler greater of: 20 ns or (t cy + 40)/n ? ns n = prescale value (1, 2, 4,..., 256) 45 tt1h txcki high time synchronous, no prescaler 0.5 t cy + 20 ? ns synchronous, with prescaler 10 ? ns asynchronous 30 ? ns 46 tt1l txcki low time synchronous, no prescaler 0.5 t cy + 5 ? ns synchronous, with prescaler 10 ? ns asynchronous 30 ? ns 47 tt1p txcki input period synchronous greater of: 20 ns or (t cy + 40)/n ? ns n = prescale value (1, 2, 4, 8) asynchronous 60 ? ns ft1 txcki clock input frequency range dc 50 khz 48 tcke2tmri delay from external txcki clock edge to timer increment 2 t osc 7 t osc ? note: refer to figure 29-4 for load conditions. ccpx (capture mode) 50 51 52 ccpx 53 54 (compare or pwm mode) www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 487 pic18(l)f2x/45k50 figure 29-11: example spi ma ster mode timing (cke = 0 ) table 29-13: capture/compare/pwm requirements (all ccp modules) param . no. symbol characteristic min max units conditions 50 tccl ccpx input low time no prescaler 0.5 t cy + 20 ? ns with prescaler 10 ? ns 51 tcch ccpx input high time no prescaler 0.5 t cy + 20 ? ns with prescaler 10 ? ns 52 tccp ccpx input period 3 t cy + 40 n ?nsn = prescale value (1, 4 or 16) 53 tccr ccpx output fall time ? 25 ns 54 tccf ccpx output fall time ? 25 ns ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 70 71 72 73 74 75, 76 78 79 80 79 78 msb lsb bit 6 - - - - - -1 msb in lsb in bit 6 - - - -1 note: refer to figure 29-4 for load conditions. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 488 ? 2012 microchip technology inc. figure 29-12: example spi ma ster mode timing (cke = 1 ) table 29-14: example spi mode requirements (master mode, cke = 0 or 1 ) param. no. symbol characteristic min max units conditions 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 25 ? ns 74 tsch2dil, ts c l 2 d i l hold time of sdi data input to sck edge 25 ? ns 75 tdor sdo data output rise time ? 30 ns 76 tdof sdo data output fall time ? 20 ns 78 tscr sck output rise time (master mode) ?30ns 79 tscf sck output fall time (master mode) ? 20 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge ? 20 ns 81 tdov2sch, tdov2scl sdo data output setup to sck edge t cy ?ns ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 81 71 72 74 75, 76 78 80 msb 79 73 msb in bit 6 - - - - - -1 lsb in bit 6 - - - -1 lsb note: refer to figure 29-4 for load conditions. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 489 pic18(l)f2x/45k50 figure 29-13: example spi slave mode timing (cke = 0 ) ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78 sdi msb lsb bit 6 - - - - - -1 msb in bit 6 - - - -1 lsb in 83 note: refer to figure 29-4 for load conditions. table 29-15: example spi mode requirements (slave mode timing, cke = 0 or 1 ) param. no. symbol characteristic min max units conditions 70 tssl2sch, tssl2scl ss ? to sck ? or sck ? input t cy ?ns 71 tsch sck input high time continuous 25 ? ns 72 tscl sck input low time continuous 30 ? ns 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 25 ? ns 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 25 ? ns 75 tdor sdo data output rise time ? 30 ns 76 tdof sdo data output fall time ? 20 ns 77 tssh2doz ss ? to sdo output high-impedance 10 50 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge ? 60 ns 82 tssl2dov sdo data output valid after ss ? edge ? 60 ns 83 tsch2ssh, tscl2ssh ss ? after sck edge 1.5 t cy + 40 ? ns www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 490 ? 2012 microchip technology inc. figure 29-14: example spi slave mode timing (cke = 1 ) figure 29-15: i 2 c? bus start/stop bits timing ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 70 71 72 82 sdi 74 75, 76 msb bit 6 - - - - - -1 lsb 77 msb in bit 6 - - - -1 lsb in 80 83 note: refer to figure 29-4 for load conditions. note: refer to figure 29-4 for load conditions. 91 92 93 scl sda start condition stop condition 90 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 491 pic18(l)f2x/45k50 figure 29-16: i 2 c? bus data timing table 29-16: i 2 c? bus start/stop bits requirements (slave mode) param. no. symbol characteristic min max units conditions 90 t su : sta start condition 100 khz mode 4700 ? ns only relevant for repeated start condition setup time 400 khz mode 600 ? 91 t hd : sta start condition 100 khz mode 4000 ? ns after this period, the first clock pulse is generated hold time 400 khz mode 600 ? 92 t su : sto stop condition 100 khz mode 4700 ? ns setup time 400 khz mode 600 ? 93 t hd : sto stop condition 100 khz mode 4000 ? ns hold time 400 khz mode 600 ? note: refer to figure 29-4 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 492 ? 2012 microchip technology inc. table 29-17: i 2 c? bus data requirements (slave mode) param. no. symbol characteristic min max units conditions 100 t high clock high time 100 khz mode 4.0 ? ? s must operate at a minimum of 1.5 mhz 400 khz mode 0.6 ? ? s must operate at a minimum of 10 mhz ssp module 1.5 t cy ? 101 t low clock low time 100 khz mode 4.7 ? ? s must operate at a minimum of 1.5 mhz 400 khz mode 1.3 ? ? s must operate at a minimum of 10 mhz ssp module 1.5 t cy ? 102 t r sda and scl rise time 100 khz mode ? 1000 ns 400 khz mode 20 + 0.1 c b 300 ns c b is specified to be from 10 to 400 pf 103 t f sda and scl fall time 100 khz mode ? 300 ns 400 khz mode 20 + 0.1 c b 300 ns c b is specified to be from 10 to 400 pf 90 t su : sta start condition setup time 100 khz mode 4.7 ? ? s only relevant for repeated start condition 400 khz mode 0.6 ? ? s 91 t hd : sta start condition hold time 100 khz mode 4.0 ? ? s after this period, the first clock pulse is generated 400 khz mode 0.6 ? ? s 106 t hd : da t data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 ? s 107 t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns 92 t su : sto stop condition setup time 100 khz mode 4.7 ? ? s 400 khz mode 0.6 ? ? s 109 t aa output valid from clock 100 khz mode ? 3500 ns (note 1) 400 khz mode ? ? ns 110 t buf bus free time 100 khz mode 4.7 ? ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? ? s d102 c b bus capacitive loading ? 400 pf note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast mode i 2 c bus device can be used in a standard mode i 2 c bus system but the requirement, t su : dat ? 250 ns, must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line, t r max. + t su : dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification), before the scl line is released. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 493 pic18(l)f2x/45k50 figure 29-17: master ssp i 2 c? bus start/stop bits timing waveforms figure 29-18: master ssp i 2 c? bus data timing note: refer to figure 29-4 for load conditions. 91 93 scl sda start condition stop condition 90 92 table 29-18: master ssp i 2 c? bus start/stop bits requirements param. no. symbol characteristic min max units conditions 90 t su : sta start condition 100 khz mode 2(t osc )(brg + 1) ? ns only relevant for repeated start condition setup time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? 91 t hd : sta start condition 100 khz mode 2(t osc )(brg + 1) ? ns after this period, the first clock pulse is generated hold time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? 92 t su : sto stop condition 100 khz mode 2(t osc )(brg + 1) ? ns setup time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? 93 t hd : sto stop condition 100 khz mode 2(t osc )(brg + 1) ? ns hold time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? note 1: maximum pin capacitance = 10 pf for all i 2 c pins. note: refer to figure 29-4 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 494 ? 2012 microchip technology inc. table 29-19: master ssp i 2 c? bus data requirements param. no. symbol characteristic min max units conditions 100 t high clock high time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 101 t low clock low time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 102 t r sda and scl rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) ? 300 ns 103 t f sda and scl fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) ? 100 ns 90 t su : sta start condition setup time 100 khz mode 2(t osc )(brg + 1) ? ms only relevant for repeated start condition 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 91 t hd : sta start condition hold time 100 khz mode 2(t osc )(brg + 1) ? ms after this period, the first clock pulse is generated 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 106 t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 ms 107 t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns 92 t su : sto stop condition setup time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 109 t aa output valid from clock 100 khz mode ? 3500 ns 400 khz mode ? 1000 ns 1 mhz mode (1) ??ns 110 t buf bus free time 100 khz mode 4.7 ? ms time the bus must be free before a new trans- mission can start 400 khz mode 1.3 ? ms d102 c b bus capacitive loading ? 400 pf note 1: maximum pin capacitance = 10 pf for all i 2 c pins. 2: a fast mode i 2 c bus device can be used in a standard mode i 2 c bus system, but parameter 107 ? 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line, parameter 102 + parameter 107 = 1000 + 250 = 1250 ns (for 100 khz mode), before the scl line is released. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 495 pic18(l)f2x/45k50 figure 29-19: eusart synchrono us transmission (master/slave) timing figure 29-20: eusart synchro nous receive (master/slave) timing 121 121 120 122 tx/ck rx/dt pin pin note: refer to figure 29-4 for load conditions. table 29-20: eusart synchrono us transmission requirements param. no. symbol characteristic min max units conditions 120 tckh2dtv sync xmit (master & slave) clock high to data out valid ?40ns 121 tckrf clock out rise time and fall time (master mode) ?20ns 122 tdtrf data out rise time and fall time ?20ns 125 126 tx/ck rx/dt pin pin note: refer to figure 29-4 for load conditions. table 29-21: eusart synchro nous receive requirements param. no. symbol characteristic min max units conditions 125 tdtv2ckl sync rcv (master & slave) data setup before ck ? (dt setup time) 10 ? ns 126 tckl2dtl data hold after ck ? (dt hold time) 15 ? ns www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 496 ? 2012 microchip technology inc. figure 29-21: a/d conversion timing table 29-22: a/d converter characteristics:pic18(l)f2x/45k50 pic18(l)f2x/45k50 standard operating conditions (unless otherwise stated) operating temperature tested at +25c param. no. symbol characteristic min typ max units conditions a01 n r resolution ? ? 10 bits ? v ref ? 3.0v a03 e il integral linearity error ? 0.5 1 lsb ? v ref = 3.0v a04 e dl differential linearity error ? 0.5 1 lsb ? v ref ? 3.0v a06 e off offset error ? 0.7 2 lsb ? v ref ? 3.0v a07 e gn gain error ? 0.7 2 lsb ? v ref ? 3.0v a08 e totl total error ? 0.8 3 lsb ? v ref ? 3.0v a20 ? v ref reference voltage range (v refh ? v refl ) 2?v dd v a21 v refh reference voltage high v dd /2 ? v dd + 0.3 v a22 v refl reference voltage low v ss ? 0.3v ? v dd /2 v a25 v ain analog input voltage v refl ?v refh v a30 z ain recommended impedance of analog voltage source ?? 3k ? note: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes. 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data (note 2) 987 21 0 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 2: this is a minimal rc delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. .. . . . . t cy www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 497 pic18(l)f2x/45k50 table 29-23: a/d conversion requirements (pic18(l)f2x/45k50) standard operating conditions (unless otherwise stated) operating temperature tested at +25c param. no. symbol characteristic min typ max units conditions 130 t ad a/d clock period 1 ? 25 ? s-40 ? c to +85 ? c 131 t cnv conversion time (not including acquisition time) (note 1) 12 ? 12 t ad 132 t acq acquisition time (note 2) 1.4 ? ? ? sv dd = 3v, rs = 50 ? 135 t swc switching time from convert ? sample ? ? (note 3) 136 t dis discharge time 2 ? 2 t ad note 1: adres register may be read on the following t cy cycle. 2: the time for the holding capacitor to acquire the ?new? input voltage when the voltage changes full scale after the conversion (v dd to v ss or v ss to v dd ). the source impedance ( r s ) on the input channels is 50 ? . 3: on the following cycle of the device clock. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 498 ? 2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 499 pic18(l)f2x/45k50 30.0 dc and ac characteristics graphs and charts graphs and charts are not available at this time. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 500 ? 2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 501 pic18(l)f2x/45k50 31.0 packaging information 31.1 package marking information legend: xx...x customer-specific information or microchip part number y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 28-lead spdip (.300?) example pic18f25k50 0810017 3 e 28-lead soic (7.50 mm) example yywwnnn xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx pic18f25k50 3 e 28-lead ssop (5.30 mm) example pic18f25k50 0810017 3 e -i/ss -i/sp -i/so 0810017 www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 502 ? 2012 microchip technology inc. package marking information (continued) legend: xx...x customer-specific information or microchip part number y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 28-lead qfn (6x6 mm) example xxxxxxxx xxxxxxxx yywwnnn pin 1 pin 1 18f25k50 -i/ml 0810017 40-lead pdip (600 mil) example xxxxxxxxxxxxxxxxxx yywwnnn xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx pi1 3 e -i/p 3 e 0810017 40-lead uqfn (5x5x0.5 mm) example pin 1 pin 1 pic18f -i/mv 0810017 3 e 45k50 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 503 pic18(l)f2x/45k50 package marking information (continued) legend: xx...x customer-specific information or microchip part number y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 44-lead tqfp (10x10x1 mm) example xxxxxxxxxx yywwnnn xxxxxxxxxx xxxxxxxxxx 1 ip 11 3 e www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 504 ? 2012 microchip technology inc. 31.2 package details the following sections give the technical details of the packages. note 1 n 12 d e1 eb c e l a2 e b b1 a1 a 3 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 505 pic18(l)f2x/45k50 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 506 ? 2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 507 pic18(l)f2x/45k50 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 508 ? 2012 microchip technology inc. l l1 c a2 a1 a e e1 d n 1 2 note 1 b e www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 509 pic18(l)f2x/45k50 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 510 ? 2012 microchip technology inc. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 511 pic18(l)f2x/45k50 www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 512 ? 2012 microchip technology inc. www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 513 pic18(l)f2x/45k50 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 514 ? 2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 515 pic18(l)f2x/45k50 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 516 ? 2012 microchip technology inc. a e e1 d d1 e b note 1 note 2 n 123 c a1 l a2 l1 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 517 pic18(l)f2x/45k50 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 518 ? 2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 519 pic18(l)f2x/45k50 appendix a: revision history revision a (august 2012) initial release. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 520 ? 2012 microchip technology inc. appendix b: device differences the differences between the devices listed in this data sheet are shown in tab l e b - 1 . table b-1: device differences features (1) pic18f24k50 pic18lf24k50 pic18f25k50 pic18lf25k50 PIC18F45K50 pic18lf45k50 program memory (bytes) 16384 16384 32768 32768 32768 32768 v dd range 2.3v to 5.5v 1.8v to 3.6v 2.3v to 5.5v 1.8v to 3.6v 2.3v to 5.5v 1.8v to 3.6v i/o ports ports a, b, c, (e) ports a, b, c, (e) ports a, b, c, (e) ports a, b, c, (e) ports a, b, c, d, e ports a, b, c, d, e 10-bit analog-to-digital module 14 input channels 14 input channels 14 input channels 14 input channels 25 input channels 25 input channels packages 28-pin pdip 28-pin soic 28-pin ssop 28-pin qfn 28-pin pdip 28-pin soic 28-pin ssop 28-pin qfn 28-pin pdip 28-pin soic 28-pin ssop 28-pin qfn 28-pin pdip 28-pin soic 28-pin ssop 28-pin qfn 40-pin pdip 40-pin uqfn 44-pin tqfp 40-pin pdip 40-pin uqfn 44-pin tqfp www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 521 pic18(l)f2x/45k50 index a a/d analog port pins, configuring................................... 312 associated registers ................................................ 312 conversions .............................................................. 303 converter characteristics ......................................... 496 discharge.................................................................. 304 selecting and configuring acquisition time ............. 300 absolute maximum ratings .............................................. 459 ac (timing) characteristics .............................................. 479 load conditions for device timing specifications.... 480 parameter symbology .............................................. 479 temperature and voltage specifications .................. 480 timing conditions ..................................................... 480 ac characteristics internal rc accuracy ................................................ 482 access bank mapping with indexed literal offset mode.................. 98 ackstat ......................................................................... 248 ackstat status flag ...................................................... 248 active clock tuning associated registers .................................................. 53 adc .................................................................................. 299 acquisition requirements ......................................... 310 block diagram........................................................... 299 calculating acquisition time..................................... 310 channel selection..................................................... 300 configuration............................................................. 300 conversion clock...................................................... 301 conversion procedure .............................................. 305 internal sampling switch (r ss ) i mpedance .............. 310 interrupts................................................................... 301 operation .................................................................. 303 operation during sleep ............................................ 304 port configuration ..................................................... 300 power management.................................................. 304 reference voltage (v ref )......................................... 300 result formatting...................................................... 302 source impedance.................................................... 310 special event trigger................................................ 304 starting an a/d conversion ...................................... 302 adcon0 register............................................................. 306 adcon1 register............................................................. 307 adcon2 register............................................................. 308 addfsr ........................................................................... 448 addlw ............................................................................. 411 addulnk......................................................................... 448 addwf ............................................................................. 411 addwfc .......................................................................... 412 adresh register (adfm = 0) ......................................... 309 adresh register (adfm = 1) ......................................... 309 adresl register (adfm = 0).......................................... 309 adresl register (adfm = 1).......................................... 309 analog input connection considerations.......................... 317 analog-to-digital converter. see adc andlw ............................................................................. 412 andwf ............................................................................. 413 assembler mpasm assembler................................................... 456 b bank select register (bsr)................................................ 84 baudcon register.......................................................... 281 bc..................................................................................... 413 bcf .................................................................................. 414 bf ............................................................................. 248, 250 bf status flag .......................................................... 248, 250 block diagrams (ccp) capture mode operation ............................... 182 adc .......................................................................... 299 adc transfer function ............................................. 311 analog input model........................................... 311, 317 ccp pwm ................................................................ 188 comparator 1............................................................ 314 compare................................................................... 185 crystal operation........................................................ 38 ctmu ....................................................................... 323 ctmu current source calibration circuit ................ 326 ctmu typical connections and internal configuration for pulse delay generation ........ 334 ctmu typical connections and internal configuration for time measurement ............... 333 digital-to-analog converter (dac) ........................... 348 eusart receive ..................................................... 270 eusart transmit .................................................... 269 external por circuit (slow v dd power-up) ............... 69 external rc mode ...................................................... 39 fail-safe clock monitor (fscm)................................. 47 generic i/o port........................................................ 135 high/low-voltage detect with external input ........... 380 interrupt logic........................................................... 118 on-chip reset circuit................................................. 67 pic18(l)f2x/45k50 ................................................... 14 pwm (enhanced) ..................................................... 192 reads from flash program memory ........................ 103 resonator operation .................................................. 38 self tuning ................................................................. 50 table read operation ................................................ 99 table write operation .............................................. 100 table writes to flash program memory ................... 105 timer0 in 16-bit mode .............................................. 163 timer0 in 8-bit mode ................................................ 162 timer1 ...................................................................... 165 timer1 gate.............................................. 171, 172, 173 timer2/4/6 ................................................................ 177 usb interrupt logic .................................................. 366 usb peripheral and options .................................... 351 voltage reference.................................................... 345 voltage reference output buffer example .............. 348 watchdog timer ....................................................... 398 bn..................................................................................... 414 bnc .................................................................................. 415 bnn .................................................................................. 415 bnov ............................................................................... 416 bnz .................................................................................. 416 bor. see brown-out reset. bov .................................................................................. 419 bra .................................................................................. 417 break character (12-bit) transmit and receive ............... 289 brown-out reset (bor)...................................................... 70 detecting .................................................................... 70 disabling in sleep mode............................................. 70 minimum enable time................................................ 70 software enabled ....................................................... 70 bsf................................................................................... 417 btfsc .............................................................................. 418 www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 522 ? 2012 microchip technology inc. btfss............................................................................... 418 btg................................................................................... 419 bz...................................................................................... 420 c c compilers mplab c18 .............................................................. 456 call ................................................................................. 420 callw.............................................................................. 449 capture module. see enhanced capture/compare/ pwm(eccp) capture/compare/pwm.................................................... 181 capture/compare/pwm (ccp) associated registers w/ capture .............. 184, 187, 191 associated registers w/ compare ............................ 187 associated registers w/ pwm .......................... 191, 205 capture mode ........................................................... 181 ccpx pin configuration ............................................ 182 compare mode ......................................................... 185 ccpx pin configuration .................................... 185 software interrupt mode ........................... 182, 185 special event trigger........................................ 186 timer1 mode resource ............................ 182, 185 prescaler................................................................... 183 pwm mode duty cycle......................................................... 189 effects of reset................................................. 190 example pwm frequencies and resolutions, 20 mhz ................................ 190 example pwm frequencies and resolutions, 32 mhz ................................ 190 example pwm frequencies and resolutions, 8 mhz................................... 190 operation in sleep mode .................................. 190 resolution ......................................................... 190 system clock frequency changes................... 190 pwm operation ........................................................ 188 pwm overview ......................................................... 188 pwm period .............................................................. 189 pwm setup ............................................................... 188 ccptmrs0 register ........................................................ 209 ccpxcon (eccpx) register ........................................... 206 clock accuracy with asynchronous operation ................. 278 clock sources external modes ........................................................... 37 ec ....................................................................... 37 hs ....................................................................... 38 lp........................................................................ 38 ost..................................................................... 37 rc....................................................................... 39 xt ....................................................................... 38 internal modes ............................................................ 39 frequency selection ........................................... 41 intosc .............................................................. 39 intoscio........................................................... 39 lfintosc .......................................................... 41 clock switching................................................................... 44 clrf................................................................................. 421 clrwdt........................................................................... 421 cm1con0 register .......................................................... 319 cm2con1 register .......................................................... 320 code examples 16 x 16 signed multiply routine ............................... 116 16 x 16 unsigned multiply routine ........................... 116 8 x 8 signed multiply routine ................................... 115 8 x 8 unsigned multiply routine ............................... 115 a/d conversion......................................................... 305 capacitance calibration routine .............................. 330 capacitive touch switch routine ............................. 332 changing between capture prescalers.................... 183 clearing ram using indirect addressing ................... 94 computed goto using an offset value.................... 81 current calibration routine ...................................... 328 data eeprom read ................................................ 111 data eeprom refresh routine............................... 112 data eeprom write ................................................ 111 erasing a flash program memory row.................... 104 fast register stack .................................................... 81 initializing porta..................................................... 135 initializing portb..................................................... 140 initializing portc .................................................... 144 initializing portd .................................................... 148 initializing porte..................................................... 151 reading a flash program memory word ................. 103 saving status, wreg and bsr registers in ram .. 132 setup for ctmu calibration routines ...................... 327 writing to flash program memory .................... 106?107 code protection ................................................................ 385 comf ............................................................................... 422 comparator associated registers ................................................ 321 operation .................................................................. 313 operation during sleep ............................................ 317 response time......................................................... 315 comparator module c1 output state versus input conditions................. 315 comparator specifications................................................ 476 comparator voltage reference (cv ref ) effects of a reset ..................................................... 317 comparator voltage reference (cv ref ) response time......................................................... 315 comparators c2out as t1 gate................................................... 168 effects of a reset ..................................................... 317 compare module. see enhanced capture/compare/ pwm (eccp) computed goto................................................................ 81 config1h register......................................................... 388 config2h register......................................................... 390 config2l register ......................................................... 389 config3h register......................................................... 391 config4l register ......................................................... 392 config5h register......................................................... 393 config5l register ......................................................... 393 config6h register......................................................... 395 config6l register ......................................................... 394 config7h register......................................................... 396 config7l register ......................................................... 395 configuration bits ............................................................. 385 configuration register protection..................................... 403 context saving during interrupts...................................... 132 cpfseq ........................................................................... 422 cpfsgt ........................................................................... 423 cpfslt ............................................................................ 423 ctmu associated registers ................................................ 337 calibrating ................................................................ 326 creating a delay with................................................ 334 effects of a reset ..................................................... 335 initialization ............................................................... 325 measuring capacitance with..................................... 331 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 523 pic18(l)f2x/45k50 measuring time with................................................. 333 operation .................................................................. 324 operation during idle mode...................................... 334 operation during sleep mode .................................. 334 customer change notification service ............................. 531 customer notification service........................................... 531 customer support............................................................. 531 cv ref voltage reference specifications ......................... 476 d data addressing modes...................................................... 94 comparing addressing modes with the extended instruction set enabled...................................... 97 direct........................................................................... 94 indexed literal offset.................................................. 96 instructions affected ........................................... 96 indirect ........................................................................ 94 inherent and literal ..................................................... 94 data eeprom code protection ........................................................ 403 data eeprom memory associated registers ................................................ 113 eeadr and eeadrh registers .............................. 109 eecon1 and eecon2 registers ............................ 109 operation during code-protect ................................ 112 protection against spurious write ............................ 112 reading..................................................................... 111 using......................................................................... 112 write verify ............................................................... 111 writing....................................................................... 111 data memory ...................................................................... 84 access bank ............................................................... 87 and the extended instruction set................................ 96 bank select register (bsr)........................................ 84 general purpose registers......................................... 87 special function registers ......................................... 87 daw.................................................................................. 424 dc and ac characteristics ............................................... 499 dc characteristics input/output .............................................................. 472 power-down current ................................................ 462 primary idle supply current...................................... 469 primary run supply current ..................................... 468 rc idle supply current ............................................. 466 rc run supply current ............................................ 464 secondary oscillator supply current........................ 470 supply voltage.......................................................... 461 dcfsnz ........................................................................... 425 decf ................................................................................ 424 decfsz............................................................................ 425 development support ....................................................... 455 device differences............................................................ 520 device overview details on individual family members ........................ 12 features (table)........................................................... 13 new core features..................................................... 11 other special features ............................................... 12 device reset timers........................................................... 71 pll lock time-out...................................................... 71 power-up timer (pwrt) ............................................ 71 time-out sequence..................................................... 71 devid1 register............................................................... 396 devid2 register............................................................... 396 digital-to-analog converter (dac).................................... 347 associated registers ................................................ 350 effects of a reset...................................................... 348 direct addressing ............................................................... 95 e eccp/ccp. see enhanced capture/compare/pwm eccpxas register........................................................... 210 eecon1 register..................................................... 101, 110 effect on standard pic instructions.................................. 452 effects of power managed modes on various clock sources ............................................................ 42 effects of reset pwm mode............................................................... 190 electrical characteristics .................................................. 459 enhanced capture/compare/pwm (eccp)..................... 181 enhanced pwm mode.............................................. 192 auto-restart ..................................................... 200 auto-shutdown ................................................. 199 direction change in full-bridge output mode.. 198 full-bridge application...................................... 196 full-bridge mode .............................................. 196 half-bridge application ..................................... 195 half-bridge application examples .................... 201 half-bridge mode.............................................. 195 output relationships (active-high and active-low)............................................... 193 output relationships diagram.......................... 194 programmable dead band delay..................... 201 shoot-through current...................................... 201 start-up considerations.................................... 203 enhanced universal synchronous asynchronous receiver transmitter (eusart) .............................. 269 equations estimating usb transceiver current consumption . 374 errata .................................................................................... 9 eusart ........................................................................... 269 asynchronous mode................................................. 271 12-bit break transmit and receive .................. 289 associated registers, receive......................... 277 associated registers, transmit........................ 273 auto-wake-up on break ................................... 287 baud rate generator (brg) ............................ 282 clock accuracy................................................. 278 receiver ........................................................... 274 setting up 9-bit mode with address detect ...... 276 transmitter ....................................................... 271 baud rate generator (brg) associated registers........................................ 283 auto baud rate detect..................................... 286 baud rate error, calculating............................ 282 baud rates, asynchronous modes .................. 283 formulas........................................................... 282 high baud rate select (brgh bit) .................. 282 clock polarity synchronous mode........................................... 290 data polarity asynchronous receive..................................... 274 asynchronous transmit.................................... 271 synchronous mode........................................... 290 interrupts asychronous receive....................................... 275 asynchronous receive..................................... 275 asynchronous transmit.................................... 271 synchronous master mode............................... 290, 295 associated registers, receive......................... 294 associated registers, transmit................ 291, 296 reception ......................................................... 293 transmission .................................................... 290 www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 524 ? 2012 microchip technology inc. synchronous slave mode associated registers, receive ......................... 297 reception.......................................................... 297 transmission..................................................... 295 extended instruction set addfsr ................................................................... 448 addulnk................................................................. 448 and using mplab tools ........................................... 454 callw...................................................................... 449 considerations for use ............................................. 452 movsf ..................................................................... 449 movss ..................................................................... 450 pushl ...................................................................... 450 subfsr ................................................................... 451 subulnk ................................................................. 451 syntax ....................................................................... 447 f fail-safe clock monitor............................................... 47, 385 fail-safe condition clearing ....................................... 47 fail-safe detection ..................................................... 47 fail-safe operation ..................................................... 47 reset or wake-up from sleep..................................... 47 fast register stack............................................................. 80 fixed voltage reference (fvr) associated registers ................................................ 346 flash program memory....................................................... 99 associated registers ................................................ 107 control registers ...................................................... 100 eecon1 and eecon2 .................................... 100 tablat (table latch) register........................ 102 tblptr (table pointer) register ..................... 102 erase sequence ....................................................... 104 erasing ...................................................................... 104 operation during code-protect ................................ 107 reading..................................................................... 103 table pointer boundaries based on operation....................... 102 table pointer boundaries ......................................... 102 table reads and table writes ................................... 99 write sequence ........................................................ 105 writing to.................................................................. 105 protection against spurious writes .................. 107 unexpected termination................................... 107 write verify ....................................................... 107 g goto................................................................................ 426 guidelines for getting started with pic18(l)f2x/45k50 microcontrollers.......................................................... 25 h hardware multiplier ........................................................... 115 introduction ............................................................... 115 operation .................................................................. 115 performance comparison ......................................... 115 high/low-voltage detect .................................................. 379 applications............................................................... 382 associated registers ................................................ 383 characteristics .......................................................... 478 current consumption ................................................ 381 effects of a reset...................................................... 383 operation .................................................................. 380 during sleep ..................................................... 383 setup......................................................................... 381 start-up time ............................................................ 381 typical low-voltage detect application ................... 382 hlvd. see high/low-voltage detect. .............................. 379 i i 2 c mode (mssp) bus collision during a repeated start condition................... 257 during a stop condition ................................... 258 effects of a reset ..................................................... 253 i 2 c clock rate w/brg.............................................. 260 multi-master communication, bus collision and arbitration ......................................................... 254 multi-master mode .................................................... 253 stop condition timing .............................................. 252 i 2 c mode (msspx) acknowledge sequence timing ............................... 252 master mode operation.......................................................... 244 reception ......................................................... 250 start condition timing .............................. 246, 247 transmission .................................................... 248 read/write bit information (r/w bit) ........................ 229 slave mode transmission .................................................... 234 sleep operation........................................................ 253 id locations.............................................................. 385, 403 incf ................................................................................. 426 incfsz............................................................................. 427 in-circuit debugger........................................................... 403 in-circuit serial programming (icsp)....................... 385, 403 indexed literal offset addressing and standard pic18 instructions.............................. 452 indexed literal offset mode.............................................. 452 indirect addressing ............................................................. 95 infsnz............................................................................. 427 instruction cycle ................................................................. 82 clocking scheme........................................................ 82 instruction flow/pipelining .................................................. 82 instruction set................................................................... 405 addlw..................................................................... 411 addwf..................................................................... 411 addwf (indexed literal offset mode) ..................... 453 addwfc .................................................................. 412 andlw..................................................................... 412 andwf..................................................................... 413 bc............................................................................. 413 bcf .......................................................................... 414 bn............................................................................. 414 bnc .......................................................................... 415 bnn .......................................................................... 415 bnov ....................................................................... 416 bnz .......................................................................... 416 bov .......................................................................... 419 bra .......................................................................... 417 bsf........................................................................... 417 bsf (indexed literal offset mode) ........................... 453 btfsc ...................................................................... 418 btfss ...................................................................... 418 btg .......................................................................... 419 bz ............................................................................. 420 call......................................................................... 420 clrf ........................................................................ 421 clrwdt .................................................................. 421 comf ....................................................................... 422 cpfseq ................................................................... 422 cpfsgt ................................................................... 423 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 525 pic18(l)f2x/45k50 cpfslt .................................................................... 423 daw.......................................................................... 424 dcfsnz ................................................................... 425 decf ........................................................................ 424 decfsz.................................................................... 425 extended instruction set........................................... 447 general format......................................................... 407 goto ....................................................................... 426 incf.......................................................................... 426 incfsz ..................................................................... 427 infsnz ..................................................................... 427 iorlw ...................................................................... 428 iorwf ...................................................................... 428 lfsr......................................................................... 429 movf........................................................................ 429 movff ..................................................................... 430 movlb ..................................................................... 430 movlw .................................................................... 431 movwf .................................................................... 431 mullw ..................................................................... 432 mulwf..................................................................... 432 negf ........................................................................ 433 nop .......................................................................... 433 opcode field descriptions........................................ 406 pop .......................................................................... 434 push ........................................................................ 434 rcall ...................................................................... 435 reset ...................................................................... 435 retfie ..................................................................... 436 retlw ..................................................................... 436 return ................................................................... 437 rlcf......................................................................... 437 rlncf ...................................................................... 438 rrcf ........................................................................ 438 rrncf ....................... .............................................. 439 setf......................................................................... 439 setf (indexed literal offset mode) ......................... 453 sleep ...................................................................... 440 subfwb................................................................... 440 sublw ..................................................................... 441 subwf ..................................................................... 441 subwfb................................................................... 442 swapf ..................................................................... 442 tblrd ...................................................................... 443 tblwt...................................................................... 444 tstfsz .................................................................... 445 xorlw..................................................................... 445 xorwf..................................................................... 446 intcon register.............................................................. 120 intcon registers ............................................................ 119 intcon2 register............................................................ 121 intcon3 register............................................................ 122 internal oscillator block hfintosc frequency drift ........................................ 41 pll in hfintosc modes........................................... 42 internal rc oscillator use with wdt ........................................................... 398 internal sampling switch (r ss ) i mpedance ...................... 310 internet address................................................................ 531 interrupt sources .............................................................. 385 adc .......................................................................... 301 interrupt-on-change (rb7:rb4) ............................... 140 intn pin .................................................................... 132 portb, interrupt-on-change ................................... 132 tmr0 ........................................................................ 132 tmr0 overflow......................................................... 163 interrupts configuration word with act sources ....................... 53 tmr1........................................................................ 170 iorlw .............................................................................. 428 iorwf.............................................................................. 428 ipr registers.................................................................... 119 ipr1 register ................................................................... 129 ipr2 register ................................................................... 130 ipr3 register ................................................................... 131 l lfsr ................................................................................ 429 low-voltage icsp programming. see single-supply icsp programming m map..................................................................................... 85 master clear (mclr ).......................................................... 69 master synchronous serial port. see msspx memory organization data memory .............................................................. 84 program memory........................................................ 77 microchip internet web site.............................................. 531 movf ............................................................................... 429 movff ............................................................................. 430 movlb ............................................................................. 430 movlw ............................................................................ 431 movsf ............................................................................. 449 movss............................................................................. 450 movwf ............................................................................ 431 mplab asm30 assembler, linker, librarian ................... 456 mplab integrated development environment software.. 455 mplab pm3 device programmer .................................... 458 mplab real ice in-circuit emulator system ................ 457 mplink object linker/mplib object librarian ................ 456 msspx.............................................................................. 213 spi mode.................................................................. 216 sspxbuf register ................................................... 219 sspxsr register ..................................................... 219 mullw............................................................................. 432 mulwf............................................................................. 432 n negf................................................................................ 433 nop .................................................................................. 433 o osccon register........................................................ 35, 36 oscillator configuration ec............................................................................... 31 ecio........................................................................... 31 hs............................................................................... 31 hspll ........................................................................ 31 lp ............................................................................... 31 rc .............................................................................. 31 xt ............................................................................... 31 oscillator control ................................................................ 33 oscillator selection ........................................................... 385 oscillator settings for usb ................................................. 49 oscillator start-up timer (ost) .................................... 43, 71 oscillator switching fail-safe clock monitor .............................................. 47 two-speed clock start-up ......................................... 45 osctune register............................................................ 40 www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 526 ? 2012 microchip technology inc. p p1a/p1b/p1c/p1d. see enhanced capture/compare/ pwm (eccp) ............................................................ 192 packaging information ...................................................... 501 marking ..................................................................... 501 pie registers .................................................................... 119 pie1 register .................................................................... 126 pie2 register .................................................................... 127 pie3 register3 .................................................................. 128 pir1 register.................................................................... 123 pir2 register.................................................................... 124 pll frequency multiplier .................................................... 42 pop................................................................................... 434 por. see power-on reset. porta associated registers ................................................ 137 porta register ....................................................... 135 trisa register ......................................................... 135 portb associated registers ................................................ 143 portb register ....................................................... 140 portc associated registers ................................................ 147 portc register ....................................................... 144 portd associated registers ................................................ 151 portd register ....................................................... 148 trisd register......................................................... 148 porte associated registers ................................................ 152 porte register ....................................................... 151 power managed modes ...................................................... 55 and a/d operation .................................................... 304 effects on clock sources............................................ 42 entering....................................................................... 55 exiting idle and sleep modes ..................................... 62 by interrupt.......................................................... 62 by reset.............................................................. 63 by wdt time-out................................................ 62 without a start-up delay..................................... 63 idle modes .................................................................. 60 pri_idle ............................................................ 60 rc_idle............................................................. 62 sec_idle........................................................... 61 multiple sleep functions ............................................. 56 run modes.................................................................. 56 pri_run ............................................................ 56 sec_run........................................................... 56 selecting ..................................................................... 55 sleep mode ................................................................. 59 summary (table) ......................................................... 55 power supply pins .............................................................. 26 power-on reset (por) ....................................................... 69 power-up timer (pwrt) ............................................ 71 time-out sequence..................................................... 71 power-up delays................................................................. 43 power-up timer (pwrt)..................................................... 43 prescaler, timer0.............................................................. 163 pri_idle mode .................................................................. 60 pri_run mode .................................................................. 56 program counter................................................................. 78 pcl, pch and pcu registers.................................... 78 pclath and pclatu registers ............................... 78 program memory and extended instruction set...................................... 98 code protection ........................................................ 401 instructions ................................................................. 83 two-word ........................................................... 83 interrupt vector ........................................................... 77 look-up tables ........................................................... 81 map and stack (diagram) ........................................... 77 reset vector............................................................... 77 program verification and code protection ....................... 400 associated registers ................................................ 400 pstrxcon register ........................................................ 211 push................................................................................ 434 push and pop instructions............................................... 80 pushl.............................................................................. 450 pwm (eccp module) pwm steering........................................................... 202 steering synchronization.......................................... 202 pwm mode. see enhanced capture/compare/pwm ...... 192 pwm steering................................................................... 202 pwmxcon register......................................................... 211 r ram. see data memory. rc_idle mode................................................................... 62 rc_run............................................................................. 56 rcall .............................................................................. 435 rcon register................................................................... 68 bit status during initialization ..................................... 75 rcreg............................................................................. 276 rcsta register ............................................................... 280 reader response............................................................. 532 register rcreg register ...................................................... 286 register file........................................................................ 87 registers adcon0 (adc control 0) ........................................ 306 adcon1 (adc control 1) ........................................ 307 adcon2 (adc control 2) ........................................ 308 adresh (adc result high) with adfm = 0) .......... 309 adresh (adc result high) with adfm = 1) .......... 309 adresl (adc result low) with adfm = 0)............ 309 adresl (adc result low) with adfm = 1)............ 309 baudcon (baud rate control)............................... 281 baudcon (eusart baud rate control) ............... 281 bdnstat (buffer descriptor n status, cpu mode) . 362 bdnstat (buffer descriptor n status, sie mode) ... 363 ccptmrs0 (pwm timer selection control 0) ........ 209 ccpxcon (eccpx control)..................................... 206 cm1con0 (c1 control)............................................ 319 cm2con1 (c2 control)............................................ 320 config1h (configuration 1 high) ........................... 388 config2h (configuration 2 high) ........................... 390 config2l (configuration 2 low) ............................ 389 config3h (configuration 3 high) ........................... 391 config4l (configuration 4 low) ............................ 392 config5h (configuration 5 high) ........................... 393 config5l (configuration 5 low) ............................ 393 config6h (configuration 6 high) ........................... 395 config6l (configuration 6 low) ............................ 394 config7h (configuration 7 high) ........................... 396 config7l (configuration 7 low) ............................ 395 ctmuconh (ctmu control high) .......................... 335 ctmuconl (ctmu control low) ........................... 336 ctmuicon (ctmu current control) ....................... 337 devid1 (device id 1)............................................... 396 devid2 (device id 2)............................................... 396 eccpxas (ccpx auto-shutdown control) .............. 210 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 527 pic18(l)f2x/45k50 eecon1 (data eeprom control 1) ................ 101, 110 hlvdcon (high/low-voltage detect control)......... 379 intcon (interrupt control)....................................... 120 intcon2 (interrupt control 2).................................. 121 intcon3 (interrupt control 3).................................. 122 ipr1 (peripheral interrupt priority 1)......................... 129 ipr2 (peripheral interrupt priority 2)......................... 130 ipr3 (peripheral interrupt priority)............................ 131 osccon (oscillator control) ............................... 35, 36 osctune (oscillator tuning) .................................... 40 pie1 (peripheral interrupt enable 1)......................... 126 pie2 (peripheral interrupt enable 2)......................... 127 pie3 (peripheral interrupt enable] ............................ 128 pir1 (peripheral interrupt request 1) ...................... 123 pir2 (peripheral interrupt request 2) ...................... 124 pstrxcon (pwm steering control) ....................... 211 pwmxcon (enhanced pwm control) ..................... 211 rcon (reset control) ........................................ 68, 131 rcsta (receive status and control)....................... 280 slrcon (port slew rate control)........................ 159 srcon0 (sr latch control 0) ................................. 342 srcon1 (sr latch control 1) ................................. 343 sspxadd (msspx address and baud rate, i 2 c mode) ......................................................... 267 sspxcon1 (msspx control 1) ................................ 262 sspxcon2 (sspx control 2) ................................... 264 sspxmsk (sspx mask) ........................................... 266 sspxstat (sspx status) ........................................ 261 status...................................................................... 93 stkptr (stack pointer) ............................................. 80 t0con (timer0 control)........................................... 161 t1con (timer1 control)........................................... 174 t1gcon (timer1 gate control) ............................... 175 txsta (transmit status and control) ...................... 279 ucfg (usb configuration)....................................... 355 ucon (usb control) ................................................ 353 ueie (usb error interrupt enable) ........................... 371 ueir (usb error interrupt status) ............................ 370 uepn (usb endpoint n control) ............................... 358 uie (usb interrupt enable)....................................... 369 uir (usb interrupt status) ....................................... 367 ustat (usb status) ................................................ 357 vrefcon0 .............................................................. 346 vrefcon1 .............................................................. 349 vrefcon2 .............................................................. 350 wdtcon (watchdog timer control) ....................... 399 reset .............................................................................. 435 reset state of registers ..................................................... 75 resets............................................................................... 385 brown-out reset (bor) ............................................ 385 oscillator start-up timer (ost) ................................ 385 power-on reset (por) ............................................. 385 power-up timer (pwrt) .......................................... 385 retfie ............................................................................. 436 retlw ............................................................................. 436 return ........................................................................... 437 return address stack ......................................................... 78 return stack pointer (stkptr) ......................................... 79 revision history ................................................................ 519 rlcf................................................................................. 437 rlncf .............................................................................. 438 rrcf ................................................................................ 438 rrncf .................. ........................................................... 439 s sec_idle mode ................................................................ 61 sec_run mode................................................................. 56 setf ................................................................................ 439 shoot-through current ...................................................... 201 single-supply icsp programming. sleep .............................................................................. 440 sleep osc1 and osc2 pin states....................................... 43 sleep mode ........................................................................ 59 slew rate ......................................................................... 153 slrcon register ............................................................ 159 software simulator (mplab sim) .................................... 457 spbrg ............................................................................. 282 spbrgh .......................................................................... 282 special event trigger ....................................................... 304 special function registers ................................................. 87 map............................................................................. 88 spi mode (msspx) associated registers................................................ 223 spi clock.................................................................. 219 sr latch associated registers................................................ 343 effects of a reset ..................................................... 339 srcon0 register ............................................................ 342 srcon1 register ............................................................ 343 sspov ............................................................................. 250 sspov status flag .......................................................... 250 sspxadd register........................................................... 267 sspxcon1 register ........................................................ 262 sspxcon2 register ........................................................ 264 sspxmsk register........................................................... 266 sspxstat register ......................................................... 261 r/w bit ..................................................................... 229 st block diagram ............................................................ 50 stack full/underflow resets............................................... 80 standard instructions........................................................ 405 status register ............................................................... 93 stkptr register ............................................................... 80 subfsr ........................................................................... 451 subfwb .......................................................................... 440 sublw ............................................................................. 441 subulnk......................................................................... 451 subwf............................................................................. 441 subwfb .......................................................................... 442 swapf ............................................................................. 442 t t0con register ............................................................... 161 t1con register ............................................................... 174 t1gcon register ............................................................ 175 table pointer operations (table)....................................... 102 table reads/table writes .................................................. 81 tblrd .............................................................................. 443 tblwt ............................................................................. 444 time-out in various situations (table)................................. 72 timer0 .............................................................................. 161 associated registers................................................ 163 operation.................................................................. 162 overflow interrupt ..................................................... 163 prescaler .................................................................. 163 prescaler assignment (psa bit)............................... 163 prescaler select (t0ps2:t0ps0 bits) ...................... 163 prescaler. see prescaler, timer0. www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 528 ? 2012 microchip technology inc. reads and writes in 16-bit mode ............................. 162 source edge select (t0se bit)................................. 162 source select (t0cs bit).......................................... 162 switching prescaler assignment............................... 163 timer1 ............................................................................... 165 associated registers.................................................. 176 asynchronous counter mode ................................... 167 reading and writing ......................................... 167 clock source selection ............................................. 166 interrupt..................................................................... 170 operation .................................................................. 166 operation during sleep ............................................ 170 oscillator ................................................................... 167 prescaler................................................................... 167 timer1 gate selecting source............................................... 168 tmr1h register ....................................................... 165 tmr1l register........................................................ 165 timer2 associated registers.................................................. 180 timer2/4/6 ......................................................................... 177 associated registers.................................................. 180 timers timer1 t1con.............................................................. 174 t1gcon ........................................................... 175 timing diagrams a/d conversion ......................................................... 496 acknowledge sequence ........................................... 252 asynchronous reception .......................................... 277 asynchronous transmission ..................................... 272 asynchronous transmission (back to back) ............ 273 auto wake-up bit (wue) during normal operation . 288 auto wake-up bit (wue) during sleep .................... 288 automatic baud rate calculator ............................... 287 baud rate generator with clock arbitration ............. 245 brg reset due to sda arbitration during start condition........................................................... 256 brown-out reset (bor) ............................................ 484 bus collision during a repeated start condition (case 1) ............................................................ 257 bus collision during a repeated start condition (case 2) ............................................................ 257 bus collision during a start condition (scl = 0) ..... 256 bus collision during a stop condition (case 1) ....... 258 bus collision during a stop condition (case 2) ....... 258 bus collision during start condition (sda only) ...... 255 bus collision for transmit and acknowledge............ 254 capture/compare/pwm (ccp)................................. 486 clko and i/o ........................................................... 483 clock synchronization .............................................. 242 clock/instruction cycle ............................................... 82 comparator output ................................................... 313 eusart synchronous receive (master/slave) ....... 495 eusart synchronous transmission (master/slave)................................................... 495 example spi master mode (cke = 0) ...................... 487 example spi master mode (cke = 1) ...................... 488 example spi master mode timing ........................... 487 example spi slave mode (cke = 0) ........................ 489 example spi slave mode (cke = 1) ........................ 490 external clock (all modes except pll)..................... 481 fail-safe clock monitor (fscm) ................................. 48 first start bit timing ................................................. 246 full-bridge pwm output ........................................... 197 half-bridge pwm output .................................. 195, 201 high/low-voltage detect characteristics ................. 477 high-voltage detect operation (vdirmag = 1) ...... 382 i 2 c bus data............................................................. 491 i 2 c bus start/stop bits ............................................. 490 i 2 c master mode (7 or 10-bit transmission) ............ 249 i 2 c master mode (7-bit reception)........................... 251 i 2 c stop condition receive or transmit mode......... 252 internal oscillator switch timing ................................ 46 low-voltage detect operation (vdirmag = 0) ....... 381 master ssp i 2 c bus data......................................... 493 master ssp i 2 c bus start/stop bits ......................... 493 pwm auto-shutdown ................................................ 200 firmware restart .............................................. 200 pwm direction change ............................................ 198 pwm direction change at near 100% duty cycle... 199 pwm output (active-high) ....................................... 193 pwm output (active-low) ........................................ 194 repeat start condition ............................................. 247 reset, watchdog timer (wdt), oscillator start-up timer (ost), power-up timer (pwrt) ............ 484 send break character sequence ............................. 289 slow rise time (mclr tied to v dd , v dd rise > t pwrt )................................................................ 73 spi mode (master mode).......................................... 219 synchronous reception (master mode, sren) ....... 294 synchronous transmission ...................................... 291 synchronous transmission (through txen) ........... 291 time-out sequence on por w/pll enabled (mclr tied to v dd ) ........................................... 74 time-out sequence on power-up (mclr not tied to v dd , case 1) .......................................... 72 time-out sequence on power-up (mclr not tied to v dd , case 2) .......................................... 73 time-out sequence on power-up (mclr tied to v dd , v dd rise < t pwrt ) ................................ 72 timer0 and timer1 external clock ........................... 485 timer1 incrementing edge ....................................... 171 transition for entry to sec_run mode ..................... 57 transition for entry to sleep mode ............................. 60 transition for wake from sleep (hspll) ................... 60 transition from rc_run mode to pri_run mode ... 58 transition from sec_run mode to pri_run mode (hspll).................................................... 57 transition timing for entry to idle mode..................... 61 transition timing for wake from idle to run mode .... 61 timing diagrams and specifications ................................ 481 a/d conversion requirements ................................. 497 capture/compare/pwm requirements .................... 487 clko and i/o requirements.................................... 483 eusart synchronous receive requirements........ 495 eusart synchronous transmission requirements 495 example spi mode requirements (master mode, cke = 0)................................... 488 (slave mode, cke = 0)..................................... 489 external clock requirements ................................... 481 i 2 c bus data requirements (slave mode) ............... 492 i 2 c bus start/stop bits requirements (slave mode) 491 master ssp i 2 c bus data requirements ................. 494 master ssp i 2 c bus start/stop bits requirements.. 493 pll clock ................................................................. 482 reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements ................................................... 485 timer0 and timer1 external clock requirements.... 486 www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 529 pic18(l)f2x/45k50 top-of-stack access ........................................................... 78 tstfsz ............................................................................ 445 two-speed clock start-up mode ........................................ 45 two-speed start-up .......................................................... 385 two-word instructions example cases........................................................... 83 txreg.............................................................................. 271 txsta register ................................................................ 279 brgh bit .................................................................. 282 u universal serial bus address register (uaddr) ...................................... 359 associated registers ................................................ 376 buffer descriptor table ............................................. 360 buffer descriptors ..................................................... 360 address validation ............................................ 363 assignment in different buffering modes ......... 365 bdnstat register (cpu mode) ...................... 361 bdnstat register (sie mode) ........................ 363 byte count ........................................................ 363 example ............................................................ 360 memory map ..................................................... 364 ownership......................................................... 360 ping-pong buffering.......................................... 364 register summary ............................................ 365 status and configuration .................................. 360 class specifications and drivers .............................. 378 descriptors................................................................ 378 endpoint control ....................................................... 358 enumeration.............................................................. 378 external pull-up resistors......................................... 356 eye pattern test enable ........................................... 356 firmware and drivers................................................ 375 frame number registers.......................................... 359 frames...................................................................... 377 internal pull-up resistors.......................................... 356 internal transceiver .................................................. 354 interrupts................................................................... 366 and usb transactions ...................................... 366 layered framework .................................................. 377 oscillator requirements............................................ 375 overview ........................................................... 351, 377 ping-pong buffer configuration ................................ 356 power........................................................................ 377 power modes ............................................................ 372 bus power only ................................................ 372 dual power with self-power dominance .......... 373 self-power only................................................ 372 ram .......................................................................... 359 memory map ..................................................... 359 speed........................................................................ 378 status and control .................................................... 352 transfer types.......................................................... 377 ufrmh:ufrml registers ....................................... 359 usb. see universal serial bus. v voltage reference (vr) specifications............................................................ 477 v ref . s ee adc reference voltage vrefcon0 register ........................................................ 346 vrefcon1 (digital-to-analog converter control 0) register..................................................................... 349 vrefcon2 (digital-to-analog converter control 1) register..................................................................... 350 w wake-up on break ............................................................ 287 watchdog timer (wdt)............................................ 385, 398 associated registers................................................ 399 control register........................................................ 399 programming considerations ................................... 398 wcol ....................................................... 245, 248, 250, 252 wcol status flag.................................... 245, 248, 250, 252 wdtcon register ........................................................... 399 www address ................................................................. 531 www, on-line support ..................... .................................. 9 x xorlw ............................................................................ 445 xorwf ............................................................................ 446 www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 530 ? 2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 531 pic18(l)f2x/45k50 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 532 ? 2012 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip product. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds30684a pic18(l)f2x/45k50 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 533 pic18(l)f2x/45k50 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern package temperature range device device: PIC18F45K50, pic18lf45k50 pic18f25k50, pic18lf25k50 pic18f24k50, pic18lf24k50 tape and reel option: blank = standard packaging (tube or tray) t = tape and reel (1), (2) temperature range: i= -40 ? c to +85 ? c (industrial) package: ml = qfn mv = uqfn p=pdip pt = tqfp (thin quad flatpack) so = soic sp = skinny plastic dip ss = ssop pattern: qtp, sqtp, code or special requirements (blank otherwise) examples: a) PIC18F45K50-i/p 301 = industrial temp., pdip package, qtp pattern #301. b) pic18lf25k50-i/so = industrial temp., soic package. c) PIC18F45K50-i/p = industrial temp., pdip package. d) pic18f24k50t-i/ml = tape and reel, industrial temp., qfn package. note 1: tape and reel option is available for ml, mv, pt, so and ss packages with industrial temperature range only. 2: tape and reel identifier only appears in catalog part number description. this identifier is used for ordering purposes and is not printed on the device package. [x] (2) tape and reel option - www.datasheet.net/ datasheet pdf - http://www..co.kr/ pic18(l)f2x/45k50 ds30684a-page 534 ? 2012 microchip technology inc. notes: www.datasheet.net/ datasheet pdf - http://www..co.kr/ ? 2012 microchip technology inc. ds30684a-page 535 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, app lication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2012, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-62076-509-8 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == www.datasheet.net/ datasheet pdf - http://www..co.kr/ ds30684a-page 536 ? 2012 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://www.microchip.com/ support web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 indianapolis noblesville, in tel: 317-773-8323 fax: 317-773-5453 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8569-7000 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - chongqing tel: 86-23-8980-9588 fax: 86-23-8980-9500 china - hangzhou tel: 86-571-2819-3187 fax: 86-571-2819-3189 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4123 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - osaka tel: 81-66-152-7160 fax: 81-66-152-9310 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-5778-366 fax: 886-3-5770-955 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-330-9305 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 worldwide sales and service 11/29/11 www.datasheet.net/ datasheet pdf - http://www..co.kr/ |
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